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URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

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  • This comparison shows the changes necessary to convert path 
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    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/trunk/rtl/verilog/aeMB_regfile.v
1,5 → 1,5
/*
* $Id: aeMB_regfile.v,v 1.14 2007-04-27 15:15:49 sybreon Exp $
* $Id: aeMB_regfile.v,v 1.15 2007-04-30 15:56:50 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
27,6 → 27,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.14 2007/04/27 15:15:49 sybreon
* Fixed simulation bug.
*
* Revision 1.13 2007/04/27 04:22:40 sybreon
* Fixed minor synthesis bug.
*
140,8 → 143,8
wire [31:0] wDWBDAT;
reg [31:0] sDWBDAT;
reg [31:0] rDWBDAT;
assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
assign wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
assign dwb_dat_o = rDWBDAT;
assign wDWBDAT = dwb_dat_i;
 
/**
RAM Based Register File
/trunk/rtl/verilog/aeMB_aslu.v
1,5 → 1,5
/*
* $Id: aeMB_aslu.v,v 1.7 2007-04-27 00:23:55 sybreon Exp $
* $Id: aeMB_aslu.v,v 1.8 2007-04-30 15:56:50 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
25,6 → 25,10
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.7 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
*
* Revision 1.6 2007/04/26 14:29:53 sybreon
* Made minor performance optimisations.
*
57,7 → 61,6
 
output [DSIZ-1:0] dwb_adr_o;
output [3:0] dwb_sel_o;
//input [31:0] dwb_dat_i;
output [31:0] rRESULT;
output [3:0] rDWBSEL;
209,7 → 212,7
 
reg [3:0] rDWBSEL, xDWBSEL;
assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
assign dwb_sel_o = {rDWBSEL[0],rDWBSEL[1],rDWBSEL[2],rDWBSEL[3]};
assign dwb_sel_o = rDWBSEL;
 
always @(/*AUTOSENSE*/rOPC or wADD)
case (wADD[1:0])
/trunk/sim/verilog/testbench.v
1,5 → 1,5
/*
* $Id: testbench.v,v 1.3 2007-04-27 15:18:43 sybreon Exp $
* $Id: testbench.v,v 1.4 2007-04-30 15:56:50 sybreon Exp $
*
* AEMB Generic Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
24,6 → 24,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.3 2007/04/27 15:18:43 sybreon
* Minor updates as sw/c/aeMB_testbench.c got updated.
*
* Revision 1.2 2007/04/25 22:15:05 sybreon
* Added support for 8-bit and 16-bit data types.
*
44,8 → 47,8
always #5 sys_clk_i = ~sys_clk_i;
 
initial begin
$dumpfile("dump.vcd");
$dumpvars(1,dut);
//$dumpfile("dump.vcd");
//$dumpvars(1,dut);
end
initial begin
82,9 → 85,9
wire [DSIZ-1:0] dwb_adr_o;
wire [31:0] dwb_dat_t;
assign dwb_dat_i = ram[dadr];
assign iwb_dat_i = ram[iadr];
assign dwb_dat_t = ram[dwb_adr_o[DSIZ-1:2]];
assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
assign {dwb_dat_t} = ram[dwb_adr_o[DSIZ-1:2]];
always @(posedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
94,13 → 97,13
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[7:0]};
4'h2: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[15:8],dwb_dat_t[7:0]};
4'h4: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:24],dwb_dat_o[23:16],dwb_dat_t[15:0]};
4'h8: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:24],dwb_dat_t[23:0]};
4'h3: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[15:0]};
4'hC: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:16],dwb_dat_t[15:0]};
4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:0]};
4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
4'h2: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
4'h4: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
4'h8: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]};
4'h3: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
4'hC: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
endcase // case (dwb_sel_o)
end
end
108,7 → 111,7
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
ram[i] <= 32'h0;
ram[i] <= $random;
end
#1 $readmemh("aeMB.rom",ram);
end
139,7 → 142,7
if (dwb_we_o & (dwb_dat_o == "PASS")) begin
$display("\tPASS");
end
if (iwb_dat_i == 32'h000000b8) begin
if (iwb_dat_i == 32'hb8000000) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
end
/trunk/sw/c/aeMB_testbench.c
1,5 → 1,5
/*
* $Id: aeMB_testbench.c,v 1.5 2007-04-27 15:17:59 sybreon Exp $
* $Id: aeMB_testbench.c,v 1.6 2007-04-30 15:57:10 sybreon Exp $
*
* AEMB Function Verification C Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
25,6 → 25,10
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.5 2007/04/27 15:17:59 sybreon
* Added code documentation.
* Added new tests that test floating point, modulo arithmetic and multiplication/division.
*
* Revision 1.4 2007/04/25 22:15:05 sybreon
* Added support for 8-bit and 16-bit data types.
*
250,16 → 254,16
int* mpi = (int*)0xFFFFFFFF;
 
// Number of each test to run
int max = 5;
int max = 3;
 
// Fibonacci Test
if (fib_test(max) == -1) { *mpi = 0x4C494146; }
if (fib_test(max) == -1) { *mpi = 0x4641494C; }
 
// Euclid Test
if (euclid_test(max) == -1) { *mpi = 0x4C494146; }
if (euclid_test(max) == -1) { *mpi = 0x4641494C; }
 
// Newton-Rhapson Test
if (newton_test(max) == -1) { *mpi = 0x4C494146; }
if (newton_test(max) == -1) { *mpi = 0x4641494C; }
// ALL PASSED
return 0;

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