OpenCores
URL https://opencores.org/ocsvn/ax8/ax8/trunk

Subversion Repositories ax8

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 30 to Rev 31
    ↔ Reverse comparison
  •

Rev 30 → Rev 31

/trunk/sim/rtl_sim/bin/compile.do File deleted
/trunk/sw/echo1200.hex File deleted
/trunk/sw/hex2rom.cpp File deleted
/trunk/sw/xrom.cpp File deleted
/trunk/sw/sine2313.hex File deleted
/trunk/syn/xilinx/run/a90s1200_leo.bat File deleted
/trunk/syn/xilinx/run/a90s1200.bat File deleted
/trunk/syn/xilinx/run/a90s2313_leo.bat File deleted
/trunk/syn/xilinx/run/a90s2313.bat File deleted
/trunk/syn/xilinx/bin/a90s2313.prj File deleted
/trunk/syn/xilinx/bin/a90s1200.tcl File deleted
/trunk/syn/xilinx/bin/a90s1200.pin File deleted
/trunk/syn/xilinx/bin/a90s1200.scr File deleted
/trunk/syn/xilinx/bin/a90s2313.tcl File deleted
/trunk/syn/xilinx/bin/a90s1200.prj File deleted
/trunk/syn/xilinx/bin/a90s2313.pin File deleted
/trunk/syn/xilinx/bin/a90s2313.scr File deleted
/trunk/bench/vhdl/StimLog.vhd File deleted
/trunk/bench/vhdl/AsyncLog.vhd File deleted
/trunk/bench/vhdl/TestBench1200.vhd File deleted
/trunk/bench/vhdl/TestBench2313.vhd File deleted
/trunk/bench/vhdl/AsyncStim.vhd File deleted
/trunk/rtl/vhdl/AX8.vhd File deleted
/trunk/rtl/vhdl/AX_UART.vhd File deleted
/trunk/rtl/vhdl/AX_TC16.vhd File deleted
/trunk/rtl/vhdl/A90S2313.vhd File deleted
/trunk/rtl/vhdl/AX_Reg.vhd File deleted
/trunk/rtl/vhdl/AX_TC8.vhd File deleted
/trunk/rtl/vhdl/AX_Pack.vhd File deleted
/trunk/rtl/vhdl/AX_Reg2.vhd File deleted
/trunk/rtl/vhdl/AX_RAM.vhd File deleted
/trunk/rtl/vhdl/AX_ALU.vhd File deleted
/trunk/rtl/vhdl/AX_DPRAM.vhd File deleted
/trunk/rtl/vhdl/AX_Port.vhd File deleted
/trunk/rtl/vhdl/AX_PCS.vhd File deleted
/trunk/rtl/vhdl/A90S1200.vhd File deleted
/ax8/trunk/sw/xrom.cpp
0,0 → 1,414
//
// Xilinx VHDL ROM generator
//
// Version : 0244
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
// Not all address/data widths produce working code
// Requires stl to compile
//
// File history :
//
// 0220 : Initial release
//
// 0221 : Fixed block ROMs with partial bytes
//
// 0241 : Updated for WebPack 5.1
//
// 0244 : Added -n option and component declaration
//
 
#include <stdio.h>
#include <string>
#include <vector>
#include <iostream>
 
using namespace std;
 
#if !(defined(max)) && _MSC_VER
// VC fix
#define max __max
#endif
 
int main (int argc, char *argv[])
{
cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0244\n";
 
try
{
unsigned long aWidth;
unsigned long dWidth;
unsigned long select = 0;
unsigned long length = 0;
char z = 0;
 
if (argc < 4)
{
cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
cerr << "\nThe options can be:\n";
cerr << " -[decimal number] = SelectRAM usage in 1/16 parts\n";
cerr << " -z = use tri-state buses\n";
cerr << " -n [decimal size] = limit rom size\n";
cerr << "\nExample:\n";
cerr << " xrom Test_ROM 13 8 -6\n\n";
return -1;
}
 
int result;
 
result = sscanf(argv[2], "%lu", &aWidth);
if (result < 1)
{
throw "Error in address bits argument!\n";
}
 
result = sscanf(argv[3], "%lu", &dWidth);
if (result < 1)
{
throw "Error in data bits argument!\n";
}
 
int argument = 4;
 
while (argument < argc)
{
char tmpC = 0;
unsigned long tmpL = 0;
 
result = sscanf(argv[argument], "%c%lu", &tmpC, &tmpL);
if (result < 1 || tmpC != '-' )
{
throw "Error in options!\n";
}
 
if (result < 2)
{
sscanf(argv[argument], "%c%c", &tmpC, &tmpC);
if (tmpC != 'z' && tmpC != 'n')
{
throw "Unkown option!\n";
}
if (tmpC == 'z')
{
z = tmpC;
}
else
{
argument++;
 
if (argument == argc)
{
throw "No memory size argument!\n";
}
 
result = sscanf(argv[argument], "%lu", &tmpL);
if (!result)
{
throw "Memory size not a number!\n";
}
length = tmpL;
}
}
else
{
select = tmpL;
}
argument++;
}
 
unsigned long selectIter = 0;
unsigned long blockIter = 0;
unsigned long bytes = (dWidth + 7) / 8;
 
if (!select)
{
blockIter = ((1UL << aWidth) + 511) / 512;
if (length && length < blockIter * 512)
{
blockIter = (length + 511) / 512;
}
}
else if (select == 16)
{
selectIter = ((1UL << aWidth) + 15) / 16;
if (length && length < selectIter * 16)
{
selectIter = (length + 15) / 16;
}
}
else
{
blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
}
 
unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
if (length && length < blockTotal * 512)
{
blockTotal = (length + 511) / 512;
}
 
if (length)
{
if (length > selectIter * 16)
{
blockIter -= ((1UL << aWidth) + 511) / 512 - blockTotal;
}
else
{
blockIter = 0;
}
}
if (length && !blockIter && length < selectIter * 16)
{
selectIter = (length + 15) / 16;
}
 
cerr << "Creating ROM with " << selectIter * bytes;
cerr << " RAM16X1S and " << blockIter * bytes << " RAMB4_S8\n";
 
printf("-- This file was generated with xrom written by Daniel Wallner\n");
printf("\nlibrary IEEE;");
printf("\nuse IEEE.std_logic_1164.all;");
printf("\nuse IEEE.numeric_std.all;");
printf("\n\nentity %s is", argv[1]);
printf("\n\tport(");
printf("\n\t\tClk\t: in std_logic;");
printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
printf("\n\t);");
printf("\nend %s;", argv[1]);
printf("\n\narchitecture rtl of %s is", argv[1]);
 
if (selectIter)
{
printf("\n\tcomponent RAM16X1S");
printf("\n\t\tport(");
printf("\n\t\t\tO : out std_ulogic;");
printf("\n\t\t\tA0 : in std_ulogic;");
printf("\n\t\t\tA1 : in std_ulogic;");
printf("\n\t\t\tA2 : in std_ulogic;");
printf("\n\t\t\tA3 : in std_ulogic;");
printf("\n\t\t\tD : in std_ulogic;");
printf("\n\t\t\tWCLK : in std_ulogic;");
printf("\n\t\t\tWE : in std_ulogic);");
printf("\n\tend component;\n");
}
if (blockIter)
{
printf("\n\tcomponent RAMB4_S8");
printf("\n\t\tport(");
printf("\n\t\t\tDO : out std_logic_vector(7 downto 0);");
printf("\n\t\t\tADDR : in std_logic_vector(8 downto 0);");
printf("\n\t\t\tCLK : in std_ulogic;");
printf("\n\t\t\tDI : in std_logic_vector(7 downto 0);");
printf("\n\t\t\tEN : in std_ulogic;");
printf("\n\t\t\tRST : in std_ulogic;");
printf("\n\t\t\tWE : in std_ulogic);");
printf("\n\tend component;\n");
}
 
if (selectIter > 0)
{
printf("\n\tsignal A_r: unsigned(A'range);");
}
if (selectIter > 1)
{
printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);
printf("\n\tsignal sRAMOut : sRAMOut_a;");
printf("\n\tsignal siA_r : integer;");
}
if (selectIter && blockIter)
{
printf("\n\tsignal sD : std_logic_vector(D'range);");
}
if (blockIter == 1)
{
printf("\n\tsignal bRAMOut : std_logic_vector(%d downto 0);", bytes * 8 - 1);
}
if (blockIter > 1)
{
printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(%d downto 0);", blockTotal - blockIter, blockTotal - 1, bytes * 8 - 1);
printf("\n\tsignal bRAMOut : bRAMOut_a;");
printf("\n\tsignal biA_r : integer;");
if (!selectIter)
{
printf("\n\tsignal A_r : unsigned(A'left downto 9);");
}
}
if (selectIter && blockIter)
{
printf("\n\tsignal bD : std_logic_vector(D'range);");
}
 
printf("\nbegin");
 
if (selectIter > 0 || blockIter > 1)
{
printf("\n\tprocess (Clk)");
printf("\n\tbegin");
printf("\n\t\tif Clk'event and Clk = '1' then");
if (!selectIter)
{
printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");
}
else
{
printf("\n\t\t\tA_r <= unsigned(A);");
}
printf("\n\t\tend if;");
printf("\n\tend process;");
}
 
if (selectIter == 1)
{
printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
printf("\n\t\tS%s : RAM16X1S\n\t\t\tport map (", argv[1]);
if (blockIter)
{
printf("s");
}
printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");
printf("\n\tend generate;");
}
if (selectIter > 1)
{
printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
printf("\n\t\t\tS%s : RAM16X1S\n\t\t\t\tport map (WE => '0', WCLK => '0', D => '0', O => sRAMOut(I)(J), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));", argv[1]);
printf("\n\t\tend generate;");
if (z == 'z')
{
printf("\n\t\t");
if (blockIter)
{
printf("s");
}
printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");
}
printf("\n\tend generate;");
if (z != 'z')
{
printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");
if (blockIter)
{
printf("s");
}
printf("D <= sRAMOut(0);");
printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);
printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");
if (blockIter)
{
printf("s");
}
printf("D <= sRAMOut(I);\n\t\t\tend if;");
printf("\n\t\tend loop;\n\tend process;");
}
}
 
if (blockIter == 1)
{
printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
printf("\n\t\tB%s : RAMB4_S8", argv[1]);
printf("\n\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);
printf("\n\tend generate;");
printf("\n\n\t");
if (selectIter)
{
printf("b");
}
printf("D <= bRAMOut(D'range);");
}
if (blockIter > 1)
{
printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
printf("\n\t\tend generate;");
if (z == 'z')
{
printf("\n\t\t");
if (selectIter)
{
printf("b");
}
printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");
}
printf("\n\tend generate;");
if (z != 'z')
{
printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");
if (selectIter)
{
printf("b");
}
printf("D <= bRAMOut(%d)(D'range);", blockTotal - blockIter);
printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);
printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");
if (selectIter)
{
printf("b");
}
printf("D <= bRAMOut(I)(D'range);\n\t\t\tend if;");
printf("\n\t\tend loop;\n\tend process;");
}
}
 
if (selectIter && blockIter)
{
printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);
}
 
printf("\nend;\n");
 
return 0;
}
catch (string error)
{
cerr << "Fatal: " << error;
}
catch (const char *error)
{
cerr << "Fatal: " << error;
}
return -1;
}
/ax8/trunk/sw/hex2rom.cpp
0,0 → 1,962
//
// Binary and intel/motorola hex to VHDL ROM converter
//
// Version : 0244
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
// No support for wrapped intel segments
// Requires stl to compile
//
// File history :
//
// 0146 : Initial release
//
// 0150 : Added binary read
//
// 0208 : Changed some errors to warnings
//
// 0215 : Added support for synchronous ROM
//
// 0220 : Changed array ROM format, added support for Xilinx .UCF generation
//
// 0221 : Fixed small .UCF generation for small ROMs
//
// 0244 : Added Leonardo .UCF option
//
 
#include <stdio.h>
#include <string>
#include <vector>
#include <iostream>
 
using namespace std;
 
#if !(defined(max)) && _MSC_VER
// VC fix
#define max __max
#endif
 
class MemBlock
{
public:
unsigned long m_startAddress;
vector<unsigned char> m_bytes;
};
 
class File
{
public:
explicit File(const char *fileName, const char *mode)
{
m_file = fopen(fileName, mode);
if (m_file != NULL)
{
return;
}
string errorStr = "Error opening ";
errorStr += fileName;
errorStr += "\n";
throw errorStr;
}
 
~File()
{
fclose(m_file);
}
 
// Read binary file
void ReadBin(unsigned long limit)
{
m_top = 0;
 
m_chunks.push_back(MemBlock());
m_chunks.back().m_startAddress = 0;
 
cerr << "Reading binary file\n";
 
int tmp = fgetc(m_file);
 
while (!feof(m_file))
{
m_chunks.back().m_bytes.push_back(tmp);
 
if (m_chunks.back().m_bytes.size() > limit + 1)
{
m_chunks.back().m_bytes.pop_back();
m_top = m_chunks.back().m_bytes.size() - 1;
cerr << "Ignoring data above address space!\n";
cerr << " Limit: " << limit << "\n";
return;
}
 
tmp = fgetc(m_file);
}
 
m_top = m_chunks.back().m_bytes.size() - 1;
 
if (!m_chunks.back().m_bytes.size())
{
cerr << "No data!\n";
 
m_chunks.pop_back();
}
}
 
// Read hex file
void ReadHex(unsigned long limit)
{
char szLine[1024];
bool formatDetected = false;
bool intel;
bool endSeen = false;
bool linear = true; // Only used for intel hex
unsigned long addressBase = 0; // Only used for intel hex
unsigned long dataRecords = 0; // Only used for s-record
while (!feof(m_file))
{
if (fgets(szLine, 1024, m_file) == 0)
{
if (ferror(m_file))
{
throw "Error reading input!\n";
}
continue;
}
 
if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD)
{
szLine[strlen(szLine) - 1] = 0;
}
 
if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD)
{
szLine[strlen(szLine) - 1] = 0;
}
 
if (strlen(szLine) == 1023)
{
throw "Hex file lines to long!\n";
}
// Ignore blank lines
if (szLine[0] == '\n')
{
continue;
}
// Detect format and warn if garbage lines are found
if (!formatDetected)
{
if (szLine[0] != ':' && szLine[0] != 'S')
{
cerr << "Ignoring garbage line!\n";
continue;
}
if (szLine[0] == 'S')
{
intel = false;
cerr << "Detected S-Record\n";
}
else
{
intel = true;
cerr << "Detected intel hex file\n";
}
formatDetected = true;
}
else if ((intel && szLine[0] != ':') ||
(!intel && szLine[0] != 'S'))
{
cerr << "Ignoring garbage line!\n";
continue;
}
 
if (endSeen)
{
throw "Hex line after end of file record!\n";
}
 
if (intel)
{
unsigned long dataBytes;
unsigned long startAddress;
unsigned long type;
if (sscanf(&szLine[1], "%2lx%4lx%2lx", &dataBytes, &startAddress, &type) != 3)
{
throw "Hex line beginning corrupt!\n";
}
// Check line length
if (szLine[11 + dataBytes * 2] != '\n' && szLine[11 + dataBytes * 2] != 0)
{
throw "Hex line length incorrect!\n";
}
// Check line checksum
unsigned char checkSum = 0;
unsigned long tmp;
for (unsigned int i = 0; i <= dataBytes + 4; ++i)
{
if (sscanf(&szLine[1 + i * 2], "%2lx", &tmp) != 1)
{
throw "Hex line data corrupt!\n";
}
checkSum += tmp;
}
if (checkSum != 0)
{
throw "Hex line checksum error!\n";
}
 
switch (type)
{
case 0:
// Data record
if (!linear)
{
// Segmented
unsigned long test = startAddress;
test += dataBytes;
if (test > 0xffff)
{
throw "Can't handle wrapped segments!\n";
}
}
if (!m_chunks.size() ||
m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() !=
addressBase + startAddress)
{
m_chunks.push_back(MemBlock());
m_chunks.back().m_startAddress = addressBase + startAddress;
}
{
unsigned char i = 0;
for (i = 0; i < dataBytes; ++i)
{
sscanf(&szLine[9 + i * 2], "%2lx", &tmp);
if (addressBase + startAddress + i > limit)
{
cerr << "Ignoring data above address space!\n";
cerr << "Data address: " << addressBase + startAddress + i;
cerr << " Limit: " << limit << "\n";
if (!m_chunks.back().m_bytes.size())
{
m_chunks.pop_back();
}
continue;
}
m_chunks.back().m_bytes.push_back(tmp);
}
}
break;
 
case 1:
// End-of-file record
if (dataBytes != 0)
{
cerr << "Warning: End of file record not zero length!\n";
}
if (startAddress != 0)
{
cerr << "Warning: End of file record address not zero!\n";
}
endSeen = true;
break;
 
case 2:
// Extended segment address record
if (dataBytes != 2)
{
throw "Length field must be 2 in extended segment address record!\n";
}
if (startAddress != 0)
{
throw "Address field must be zero in extended segment address record!\n";
}
sscanf(&szLine[9], "%4lx", &startAddress);
addressBase = startAddress << 4;
linear = false;
break;
 
case 3:
// Start segment address record
if (dataBytes != 4)
{
cerr << "Warning: Length field must be 4 in start segment address record!\n";
}
if (startAddress != 0)
{
cerr << "Warning: Address field must be zero in start segment address record!\n";
}
if (dataBytes == 4)
{
unsigned long ssa;
char ssaStr[16];
sscanf(&szLine[9], "%8lx", &ssa);
sprintf(ssaStr, "%08X\n", ssa);
cerr << "Segment start address (CS/IP): ";
cerr << ssaStr;
}
break;
 
case 4:
// Extended linear address record
if (dataBytes != 2)
{
throw "Length field must be 2 in extended linear address record!\n";
}
if (startAddress != 0)
{
throw "Address field must be zero in extended linear address record!\n";
}
sscanf(&szLine[9], "%4lx", &startAddress);
addressBase = ((unsigned long)startAddress) << 16;
linear = true;
break;
 
case 5:
// Start linear address record
if (dataBytes != 4)
{
cerr << "Warning: Length field must be 4 in start linear address record!\n";
}
if (startAddress != 0)
{
cerr << "Warning: Address field must be zero in start linear address record!\n";
}
if (dataBytes == 4)
{
unsigned long lsa;
char lsaStr[16];
sscanf(&szLine[9], "%8lx", &lsa);
sprintf(lsaStr, "%08X\n", lsa);
cerr << "Linear start address: ";
cerr << lsaStr;
}
break;
 
default:
cerr << "Waring: Unknown record found!\n";
}
}
else
{
// S-record
unsigned long count;
char type;
if (sscanf(&szLine[1], "%c%2lx", &type, &count) != 2)
{
throw "Hex line beginning corrupt!\n";
}
// Check line length
if (szLine[4 + count * 2] != '\n' && szLine[4 + count * 2] != 0)
{
throw "Hex line length incorrect!\n";
}
// Check line checksum
unsigned char checkSum = 0;
unsigned long tmp;
for (unsigned int i = 0; i < count + 1; ++i)
{
if (sscanf(&szLine[2 + i * 2], "%2lx", &tmp) != 1)
{
throw "Hex line data corrupt!\n";
}
checkSum += tmp;
}
if (checkSum != 255)
{
throw "Hex line checksum error!\n";
}
 
switch (type)
{
case '0':
// Header record
{
char header[256];
unsigned char i = 0;
for (i = 0; i + 3 < count; ++i)
{
sscanf(&szLine[8 + i * 2], "%2lx", &tmp);
header[i] = tmp;
}
header[i] = 0;
if (i > 0)
{
cerr << "Module name: " << header << "\n";
}
}
break;
 
case '1':
case '2':
case '3':
// Data record
{
dataRecords++;
unsigned long startAddress;
if (type == '1')
{
sscanf(&szLine[4], "%4lx", &startAddress);
}
else if (type == '2')
{
sscanf(&szLine[4], "%6lx", &startAddress);
}
else
{
sscanf(&szLine[4], "%8lx", &startAddress);
}
 
if (!m_chunks.size() ||
m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() !=
startAddress)
{
m_chunks.push_back(MemBlock());
m_chunks.back().m_startAddress = startAddress;
}
unsigned char i = 0;
for (i = (type - '1'); i + 3 < count; ++i)
{
sscanf(&szLine[8 + i * 2], "%2lx", &tmp);
if (startAddress + i > limit)
{
cerr << "Ignoring data above address space!\n";
cerr << "Data address: " << startAddress + i;
cerr << " Limit: " << limit << "\n";
if (!m_chunks.back().m_bytes.size())
{
m_chunks.pop_back();
}
continue;
}
m_chunks.back().m_bytes.push_back(tmp);
}
}
break;
 
case '5':
// Count record
{
unsigned long address;
sscanf(&szLine[4], "%4lx", &address);
if (address != dataRecords)
{
throw "Wrong number of data records!\n";
}
}
break;
 
case '7':
case '8':
case '9':
// Start address record
cerr << "Ignoring start address record!\n";
break;
 
default:
cerr << "Unknown record found!\n";
}
}
}
if (intel && !endSeen)
{
cerr << "No end of file record!\n";
}
if (!m_chunks.size())
{
throw "No data in file!\n";
}
vector<MemBlock>::iterator vi;
m_top = 0;
for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++)
{
m_top = max(m_top, vi->m_startAddress + vi->m_bytes.size() - 1);
}
}
 
// Rather inefficient this one, fix sometime
bool GetByte(const unsigned long address, unsigned char &chr)
{
vector<MemBlock>::iterator vi;
 
for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++)
{
if (vi->m_startAddress + vi->m_bytes.size() > address && vi->m_startAddress <= address)
{
break;
}
}
if (vi == m_chunks.end())
{
return false;
}
chr = vi->m_bytes[address - vi->m_startAddress];
return true;
}
 
bool BitString(const unsigned long address, const unsigned char bits, const bool lEndian, string &str)
{
bool ok = false;
long i;
unsigned char chr;
unsigned long data = 0;
unsigned long tmp;
 
if (lEndian)
{
for (i = 0; i < (bits + 7) / 8; ++i)
{
ok |= GetByte(address + i, chr);
tmp = chr;
data |= tmp << (8 * i);
}
}
else
{
for (i = 0; i < (bits + 7) / 8; ++i)
{
ok |= GetByte(address + i, chr);
tmp = chr;
data |= tmp << (8 * ((bits + 7) / 8 - i - 1));
}
}
 
if (!ok)
{
return false;
}
 
unsigned long mask = 1;
 
str = "";
for (i = 0; i < bits; i++)
{
if (data & mask)
{
str.insert(0,"1");
}
else
{
str.insert(0,"0");
}
mask <<= 1;
}
return true;
}
 
FILE *Handle() { return m_file; };
vector<MemBlock> m_chunks;
unsigned long m_top;
private:
FILE *m_file;
};
 
 
int main (int argc, char *argv[])
{
cerr << "Hex to VHDL ROM converter by Daniel Wallner. Version 0244\n";
 
try
{
unsigned long aWidth;
unsigned long dWidth;
char endian;
char O = 0;
 
if (!(argc == 4 || argc == 5))
{
cerr << "\nUsage: hex2rom [-b] <input file> <entity name> <format>\n";
cerr << "\nIf the -b option is specified the file is read as a binary file\n";
cerr << "Hex input files must be intel hex or motorola s-record\n";
cerr << "\nThe format string has the format AEDOS where:\n";
cerr << " A = Address bits\n";
cerr << " E = Endianness, l or b\n";
cerr << " D = Data bits\n";
cerr << " O = ROM type: (one optional character)\n";
cerr << " z for tri-state output\n";
cerr << " a for array ROM\n";
cerr << " s for synchronous ROM\n";
cerr << " u for XST ucf\n";
cerr << " l for Leonardo ucf\n";
cerr << " S = SelectRAM usage in 1/16 parts (only used when O = u)\n";
cerr << "\nExample:\n";
cerr << " hex2rom test.hex Test_ROM 18b16z\n\n";
return -1;
}
 
string inFileName;
string outFileName;
 
unsigned long bytes;
unsigned long select = 0;
 
if (argc == 5)
{
if (strcmp(argv[1], "-b"))
{
throw "Error in arguments!\n";
}
}
 
int result;
 
result = sscanf(argv[argc - 1], "%lu%c%lu%c%lu", &aWidth, &endian, &dWidth, &O, &select);
if (result < 3)
{
throw "Error in output format argument!\n";
}
 
if (aWidth > 32 || (endian != 'l' && endian != 'b') || dWidth > 32 || (result > 3 && O != 'z' && O != 'a' && O != 's' && O != 'u' && O != 'l'))
{
throw "Error in output format argument!\n";
}
inFileName = argv[argc - 3];
outFileName = argv[argc - 2];
 
bytes = (dWidth + 7) / 8;
 
File inFile(inFileName.c_str(), "rb");
 
if (argc == 4)
{
inFile.ReadHex((1UL << aWidth) * bytes - 1);
}
else
{
inFile.ReadBin((1UL << aWidth) * bytes - 1);
}
 
string line;
 
unsigned long words = 1;
unsigned long i = inFile.m_top;
i /= bytes;
 
while (i != 0)
{
i >>= 1;
words <<= 1;
}
 
if (O != 'u' && O != 'l')
{
printf("-- This file was generated with hex2rom written by Daniel Wallner\n");
printf("\nlibrary IEEE;");
printf("\nuse IEEE.std_logic_1164.all;");
printf("\nuse IEEE.numeric_std.all;");
printf("\n\nentity %s is", outFileName.c_str());
printf("\n\tport(");
if (O == 'z')
{
printf("\n\t\tCE_n\t: in std_logic;", dWidth - 1);
printf("\n\t\tOE_n\t: in std_logic;", dWidth - 1);
}
if (O == 's')
{
printf("\n\t\tClk\t: in std_logic;", dWidth - 1);
}
printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
printf("\n\t);");
printf("\nend %s;", outFileName.c_str());
printf("\n\narchitecture rtl of %s is", outFileName.c_str());
if (!O)
{
printf("\nbegin");
printf("\n\tprocess (A)");
printf("\n\tbegin");
printf("\n\t\tcase to_integer(unsigned(A)) is");
}
else if (O == 's')
{
printf("\n\tsignal A_r : std_logic_vector(%d downto 0);", aWidth - 1);
printf("\nbegin");
printf("\n\tprocess (Clk)");
printf("\n\tbegin");
printf("\n\t\tif Clk'event and Clk = '1' then");
printf("\n\t\t\tA_r <= A;");
printf("\n\t\tend if;");
printf("\n\tend process;");
printf("\n\tprocess (A_r)");
printf("\n\tbegin");
printf("\n\t\tcase to_integer(unsigned(A_r)) is");
}
else
{
printf("\n\tsubtype ROM_WORD is std_logic_vector(%d downto 0);", dWidth - 1);
printf("\n\ttype ROM_TABLE is array(0 to %d) of ROM_WORD;", words - 1);
printf("\n\tconstant ROM: ROM_TABLE := ROM_TABLE'(");
}
 
string str;
string strDC;
for (i = 0; i < dWidth; i++)
{
strDC.insert(0, "-");
}
for (i = 0; i < words; i++)
{
if (!inFile.BitString(i * bytes, dWidth, endian == 'l', str))
{
str = strDC;
}
if (!O || O == 's')
{
if (inFile.m_top / bytes >= i)
{
printf("\n\t\twhen %06d => D <= \"%s\";",i, str.c_str());
printf("\t-- 0x%04X", i * bytes);
}
}
else
{
printf("\n\t\t\"%s", str.c_str());
if (i != words - 1)
{
printf("\",");
}
else
{
printf("\");");
}
printf("\t-- 0x%04X", i * bytes);
}
}
 
if (!O || O == 's')
{
printf("\n\t\twhen others => D <= \"%s\";", strDC.c_str());
printf("\n\t\tend case;");
printf("\n\tend process;");
}
else
{
printf("\nbegin");
if (O == 'z')
{
printf("\n\tD <= ROM(to_integer(unsigned(A))) when CE_n = '0' and OE_n = '0' else (others => 'Z');");
}
else
{
printf("\n\tD <= ROM(to_integer(unsigned(A)));");
}
}
printf("\nend;\n");
}
else
{
unsigned long selectIter = 0;
unsigned long blockIter = 0;
 
if (!select)
{
blockIter = ((1UL << aWidth) + 511) / 512;
}
else if (select == 16)
{
selectIter = ((1UL << aWidth) + 15) / 16;
}
else
{
blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
}
 
cerr << "Creating .ucf file with " << selectIter * bytes;
cerr << " LUTs and " << blockIter * bytes << " block RAMs\n";
 
unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
 
printf("# This file was generated with hex2rom written by Daniel Wallner\n");
 
for (i = 0; i < selectIter; i++)
{
unsigned long base = i * 16 * bytes;
unsigned long j;
unsigned char c;
unsigned long pos;
 
// Check that there is any actual data in segment
bool init = false;
for (pos = 0; pos < bytes * 16; pos++)
{
init = inFile.GetByte(base + pos, c);
if (init)
{
break;
}
}
 
if (init)
{
for (j = 0; j < dWidth; j++)
{
unsigned long bitMask = 1;
unsigned long bits = 0;
 
for (pos = 0; pos < 16; pos++)
{
unsigned long addr;
 
if (endian = 'l')
{
addr = base + bytes * pos + j / 8;
}
else
{
addr = base + bytes * pos + bytes - j / 8 - 1;
}
 
c = 0;
inFile.GetByte(addr, c);
if (c & (1 << (j % 8)))
{
bits |= bitMask;
}
bitMask <<= 1;
}
 
if (O == 'u')
{
if (selectIter == 1)
{
printf("\nINST *s%s%d INIT = %04X;", outFileName.c_str(), j, bits);
}
else
{
printf("\nINST *s%s%d%d INIT = %04X;", outFileName.c_str(), i, j, bits);
}
}
else
{
if (selectIter == 1)
{
printf("\nINST *sG1_%d_S%s INIT = %04X;", j, outFileName.c_str(), bits);
}
else
{
printf("\nINST *sG1_%d_sG2_%d_S%s INIT = %04X;", i, j, outFileName.c_str(), bits);
}
}
}
}
}
 
for (i = blockTotal - blockIter; i < blockTotal; i++)
{
unsigned long j;
for (j = 0; j < bytes; j++)
{
unsigned long k;
for (k = 0; k < 16; k++)
{
unsigned long base = i * 512 * bytes + k * 32 * bytes;
unsigned char c;
unsigned long pos;
 
// Check that there is any actual data in segment
bool init = false;
for (pos = 0; pos < 32; pos++)
{
init = inFile.GetByte(base + bytes * pos + j, c);
if (init)
{
break;
}
}
 
if (init)
{
if (O == 'u')
{
if (blockIter == 1)
{
printf("\nINST *b%s%d INIT_%02X = ", outFileName.c_str(), j, k);
}
else
{
printf("\nINST *b%s%d%d INIT_%02X = ", outFileName.c_str(), i, j, k);
}
}
else
{
if (blockIter == 1)
{
printf("\nINST *bG1_%d_B%s INIT_%02X = ", j, outFileName.c_str(), k);
}
else
{
printf("\nINST *bG1_%d_bG2_%d_B%s INIT_%02X = ", i, j, outFileName.c_str(), k);
}
}
for (pos = 0; pos < 32; pos++)
{
unsigned long addr;
 
if (endian = 'l')
{
addr = base + bytes * (31 - pos) + j;
}
else
{
addr = base + bytes * (31 - pos) + bytes - j - 1;
}
 
c = 0;
inFile.GetByte(addr, c);
printf("%02X", c);
}
printf(";");
}
}
}
}
printf("\n");
}
return 0;
}
catch (string error)
{
cerr << "Fatal: " << error;
}
catch (const char *error)
{
cerr << "Fatal: " << error;
}
return -1;
}
/ax8/trunk/sw/echo1200.hex
0,0 → 1,8
:100000000FE80DBF26C000C01895000000000000DA
:1000100018950AE02095089410F4919802C0919ADE
:10002000000013D012D026950A95B1F7089509E083
:100030008099FECF0AD009D008D08894809908947E
:100040000A9511F03795F7CF08951BE01A95F1F74F
:100050000895919A899A2CE0DCDFE9DF232FD9DF1C
:02006000FCCFD3
:00000001FF
/ax8/trunk/sw/sine2313.hex
0,0 → 1,96
:020000020000FC
:1000620069D10AE009B901E010E0002309F441C0B6
:1000720044245524662477243ED046E55EE069ECAC
:1000820070E42CD180F7A3D140E050E060EF71E43E
:10009200D7D040E050E060E272E49BD0802F912FF5
:1000A200A22FB32F88249924082D192D292D290D2B
:1000B200220B322F72D0482F592F6A2F7B2F0ED14D
:1000C20038F400E210E01CD00FEF801A900AECCF57
:1000D2000AE210E015D00AE010E012D00CD04DEC8C
:1000E2005CEC6CEC7DE375D0402E512E622E732EAB
:1000F200C3CFEAE030C1042D152D262D372D0895EA
:0C01020028E02AB95D9BFECF0CB90895DF
:020000000FC02F
:10001C0000EC05BFC0E800E903500DBF73D000230E
:10002C0009F417D0E0E6F0E000E072D1E2E6F0E08F
:10003C0000E640E061D1E0E6F0E000E069D1E2E604
:10004C00F0E000E640E058D1E2E6F0E000E640E007
:06005C0053D101D056C093
:02010E00FFCF21
:0401100001E008956D
:1001140030952095109501951F4F2F4F3F4F08950F
:100124004A952AF03695279517950795F9CF08959E
:100134001124770F179467FD73956068FF270024D7
:0E014400330F079427FD33952068EE270895AA
:100152003323D1F0222332F0EE0F001F111F221F92
:100162003A95F7CFE03838F011F401FF04C00F5F81
:100172001F4F2F4F3F4F3F3F61F0332329F030FB9A
:0801820027F936953029089594
:10018A00332722271127002708953FE7302920E83F
:02019A00F9CF9B
:10019C0070E8072E03220AF4B7DFE02F012F122F8D
:0601AC00232F3EE9D0CF35
:1001B200C7DF432F4F5710F0403208F0E5CF322F00
:1001C200212F102F0E2F4F514195ABDF07FE0895BF
:0201D200A0CFBC
:1001D400AFDF401751076207730778F0332E372FCC
:1001E400732D322E262F632D312E152F532D302EA5
:1001F400042F432D302C012C132C3F3F09F4C8CF7E
:100204007723C9F0371731F0669557954795F795D9
:100214007395F8CF10245AF0EF0F041F151F261FF3
:1002240050F4279517950795E795339590CFEF1BD5
:08023400040B150B260B8BCF08
:06023C00E0E87E27C9CFB7
:1002420078DF012407FA3F3F11F07F3F09F4A1CF85
:10025200332311F0772309F497CF3F577F57370F96
:1002620013F4AAF3F9CF31583F3FB1F34A923A93CC
:1002720033242224112400243327442477272030D6
:100282001207010789F026951795079530F4040E99
:10029200451E361F171E2E1E3F1E440F551F661F7A
:1002A200771FEE1FFF1FEBCF732F399133203AF0E8
:1002B200000C441C771F111C221C331C02C03395F6
:1002C20031F2703819F4402809F073954990232DC2
:0C02D200122D012DE72F002407F83ACF71
:1002DE008894E32FE7272AF4772312F09894089452
:1002EE0008950417150726073707D1F33323C2F7EE
:0602FE00B0F7889408959A
:10030400BF93AF93A02F03C0C89531960D9241506F
:08031400D8F7AF91BF910895E5
:0C031C00002401C001920150E8F7089590
:020328000000D3
:10032A00FA92EA92DA92CA92BA92AA929A928A9223
:10033A007A926A925A924A92BA93AA939A938A930F
:02034A00089514
:10034C00FF84EE84DD84CC84BB84AA849984888465
:10035C007F806E805D804C80BB81AA819981888171
:0E036C00F0E00FB6F894CE0FDF1F0FBE08951D
:10037A00E2DF802F912FA22FB32F442E3F7740E840
:10038A0056E968E17BE4A6DF38F013D0B38300278F
:10039A001127222733270BC011D006DFFADE402FA0
:1003AA00512F622F732F05D0338308D042DFE5E047
:1003BA00D3CFE42D0083118322830895082F192FA8
:0603CA002A2F3B2F0895CD
:0403D000442700C0FE
:1003D400AEDFC85081D0642E44275527662777277F
:1003E4007CDF10F402E001C00027600EBF777DD0EF
:1003F40043E859EF62E27FE322DF6ED081D000E070
:100404001CEF2FE737E469DF30F54C2F6ED0B3DFF4
:1004140079D05ED0062D112764D0DADE08831983E3
:100424002A833B834C2F4C5F842F40E050E060E8EC
:100434007EE305DF482F9FDF4BD00C811D812E8189
:100444003F8140E050E060E870E4F9DE4DD0F4DE36
:10045400AEDE602E09C049D0AADE402E42D051D073
:10046400460C642C03E0602260FE06C000E010E04D
:1004740020E83FE34CD045D002E0601630F000277E
:10048400A016B00611F000E8B02646D040D0D7DE62
:1004940023D04BEF57ED6EE179E3D1DE45E656E22A
:1004A40069E97BEB27D048E554E363EA7DE322D096
:1004B40041EE5DE565E27FEB1DD04BED5FE069EC5D
:1004C4007FE386DE1DD028D0BADEC85FECE040CFE3
:1004D400088119812A813B81802F912FA22FB32F6C
:1004E40008952227332758DE1CD0082F192F2A2FCE
:1004F4003B2F08956DDE482F592F6A2F7B2F9FCEF7
:1005040010C09ADE802E912EA22EB32E0895482D6F
:10051400592D6A2D7B2D0895082D192D2A2D3B2D3B
:0C0524000895402F512F622F732F08956F
:00000001FF
/ax8/trunk/rtl/vhdl/AX8.vhd
0,0 → 1,775
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/ax8/
--
-- Limitations :
-- No power down sleep, only 16 bit addresses, no external RAM
--
-- File history :
--
-- 0146 : First release
-- 0220 : Added support for synchronous ROM
-- 0221 : Changed tristate buses
-- 0221b : Changed tristate buses
-- 0224 : Fixed reset
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.AX_Pack.all;
 
entity AX8 is
generic(
ROMAddressWidth : integer;
RAMAddressWidth : integer;
BigISet : boolean;
TriState : boolean := false
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
ROM_Data : in std_logic_vector(15 downto 0);
Sleep_En : in std_logic;
Int_Trig : in std_logic_vector(15 downto 1);
Int_Acc : out std_logic_vector(15 downto 1);
SREG : out std_logic_vector(7 downto 0);
SP : out std_logic_vector(15 downto 0);
IO_Rd : out std_logic;
IO_Wr : out std_logic;
IO_Addr : out std_logic_vector(5 downto 0);
IO_RData : in std_logic_vector(7 downto 0);
IO_WData : out std_logic_vector(7 downto 0);
WDR : out std_logic
);
end AX8;
 
architecture rtl of AX8 is
 
-- Registers
signal SREG_i : std_logic_vector(7 downto 0);
signal SP_i : unsigned(15 downto 0);
signal NPC : std_logic_vector(15 downto 0);
signal PC : std_logic_vector(15 downto 0);
signal PCH : std_logic_vector(7 downto 0);
signal Dec_SP : std_logic;
signal Inc_SP : std_logic;
signal X : unsigned(15 downto 0);
signal Y : unsigned(15 downto 0);
signal Z : unsigned(15 downto 0);
signal Add : std_logic;
signal Sub : std_logic;
signal AS_Offset : std_logic_vector(5 downto 0);
signal Dec_X : std_logic;
signal Dec_Y : std_logic;
signal Dec_Z : std_logic;
signal Inc_X : std_logic;
signal Inc_Y : std_logic;
signal Inc_Z : std_logic;
 
-- ALU signals
signal Do_Other : std_logic;
signal Pass_Mux : std_logic_vector(7 downto 0);
signal Op_Mux : std_logic_vector(7 downto 0);
signal Status_D : std_logic_vector(6 downto 0);
signal Status_D_R : std_logic_vector(4 downto 0);
signal Status_Wr : std_logic_vector(6 downto 0);
signal Status_D_Wr : std_logic;
 
-- Misc signals
signal Rd_Addr : std_logic_vector(15 downto 0);
signal Rr_Addr : std_logic_vector(15 downto 0);
signal IO_Addr_i : std_logic_vector(5 downto 0);
 
signal Wr_Data : std_logic_vector(7 downto 0);
signal Rd_Data : std_logic_vector(7 downto 0);
signal Rr_Data : std_logic_vector(7 downto 0);
 
signal RAM_Data : std_logic_vector(7 downto 0);
 
signal Offset : std_logic_vector(11 downto 0);
 
signal Q : std_logic_vector(7 downto 0);
 
signal Disp : std_logic_vector(5 downto 0);
 
signal Bit_Pattern : std_logic_vector(7 downto 0);
signal IO_BMData : std_logic_vector(7 downto 0);
signal IO_BTest : std_logic_vector(7 downto 0);
signal Do_SBIC : std_logic;
signal Do_SBIS : std_logic;
 
signal CInt : std_logic_vector(3 downto 0);
signal IPush : std_logic;
signal IPending : std_logic;
 
-- Registered instruction word.
signal Inst : std_logic_vector(15 downto 0);
 
-- Control signals
signal Rst_r : std_logic;
signal IO_IR : std_logic;
signal RAM_IR : std_logic;
signal PMH_IR : std_logic;
signal PML_IR : std_logic;
signal IO_IW : std_logic;
signal RAM_IW : std_logic;
signal Reg_IW : std_logic;
signal Reg_Wr : std_logic;
signal HPC_Rd : std_logic;
signal LPC_Rd : std_logic;
signal Reg_Rd : std_logic;
signal RAM_Rd : std_logic;
signal PMH_Rd : std_logic;
signal PML_Rd : std_logic;
signal Reg_Wr_ID : std_logic;
signal RAM_Wr_ID : std_logic;
signal PassB : std_logic;
signal IO_Rd_i : std_logic;
signal IO_Wr_i : std_logic;
signal Z_Skip : std_logic;
signal IOZ_Skip : std_logic;
signal Pause : std_logic_vector(1 downto 0);
signal DidPause : std_logic_vector(1 downto 0);
signal PCPause : std_logic;
signal IndSkip : std_logic;
signal Inst_Skip : std_logic;
signal PreDecode : std_logic;
signal Imm_Op : std_logic;
signal Push : std_logic;
signal Pop : std_logic;
signal HRet : std_logic;
signal LRet : std_logic;
signal ZJmp : std_logic;
signal RJmp : std_logic;
signal CBranch : std_logic;
signal Sleep : std_logic;
 
begin
 
PreDecode <= '1' when Rst_r = '0' and Inst_Skip = '0' and (Pause = "00" or DidPause = "01") else '0';
 
-- Addressing control:
-- IO and Rd/Rr address are always generated parallel with fetch
-- On indirect addressing the correct address is generated on the next positive clock edge
-- The chip selects are only used with 2+ cycle instructions
Disp <= Inst(13) & Inst(11 downto 10) & Inst(2 downto 0);
Reg_Wr <= '1' when
Inst(15 downto 12) = "0010" or
Inst(15 downto 14) = "01" or
Inst(15 downto 11) = "00001" or
Inst(15 downto 11) = "00011" or
Inst(15 downto 12) = "1110" or
Inst(15 downto 9) = "1111100" or
(Inst(15 downto 9) = "1001010" and Inst(3 downto 1) /= "100") or
Inst(15 downto 11) = "10110" or
Reg_Wr_ID = '1'
else '0';
process (Clk)
begin
if Clk'event and Clk = '1' then
Reg_Wr_ID <= Reg_IW;
RAM_Wr_ID <= RAM_IW;
end if;
end process;
process (ROM_Data, Inst, DidPause, Pause, SP_i, X, Y, Z, Disp, IPush)
begin
Rd_Addr <= (others => '-');
Rr_Addr <= (others => '-');
Rd_Addr(4 downto 0) <= ROM_Data(8 downto 4);
Rr_Addr(4 downto 0) <= ROM_Data(9) & ROM_Data(3 downto 0);
if ROM_Data(15 downto 12) = "0011" or
ROM_Data(15 downto 14) = "01" or
ROM_Data(15 downto 12) = "1110" then
-- Special case for immediate data and four bit address
Rd_Addr(4) <= '1';
end if;
 
Dec_X <= '0';
Dec_Y <= '0';
Dec_Z <= '0';
Inc_X <= '0';
Inc_Y <= '0';
Inc_Z <= '0';
Dec_SP <= '0';
Inc_SP <= '0';
if DidPause = "00" and Pause = "01" then
if BigIset then
if Inst(15 downto 14) = "10" and Inst(12) = '0' then
if Inst(9) = '0' and Inst(3) = '0' then -- LDD Z
Rd_Addr(4 downto 0) <= Inst(8 downto 4);
Rr_Addr <= std_logic_vector(Z + unsigned(Disp));
end if;
if Inst(9) = '0' and Inst(3) = '1' then -- LDD Y
Rd_Addr(4 downto 0) <= Inst(8 downto 4);
Rr_Addr <= std_logic_vector(Y + unsigned(Disp));
end if;
if Inst(9) = '1' and Inst(3) = '0' then -- STD Z
Rr_Addr(4 downto 0) <= Inst(8 downto 4);
Rd_Addr <= std_logic_vector(Z + unsigned(Disp));
end if;
if Inst(9) = '1' and Inst(3) = '1' then -- STD Y
Rr_Addr(4 downto 0) <= Inst(8 downto 4);
Rd_Addr <= std_logic_vector(Y + unsigned(Disp));
end if;
end if;
if Inst(15 downto 9) = "1001000" then
Rd_Addr(4 downto 0) <= Inst(8 downto 4);
if Inst(3 downto 0) = "0000" then
Rr_Addr <= ROM_Data;
end if;
if Inst(3 downto 0) = "0001" then
Rr_Addr <= std_logic_vector(Z);
Inc_Z <= '1';
end if;
if Inst(3 downto 0) = "0010" then
Rr_Addr <= std_logic_vector(Z - 1);
Dec_Z <= '1';
end if;
if Inst(3 downto 0) = "1001" then
Rr_Addr <= std_logic_vector(Y);
Inc_Y <= '1';
end if;
if Inst(3 downto 0) = "1010" then
Rr_Addr <= std_logic_vector(Y - 1);
Dec_Y <= '1';
end if;
if Inst(3 downto 0) = "1100" then
Rr_Addr <= std_logic_vector(X);
end if;
if Inst(3 downto 0) = "1101" then
Rr_Addr <= std_logic_vector(X);
Inc_X <= '1';
end if;
if Inst(3 downto 0) = "1110" then
Rr_Addr <= std_logic_vector(X - 1);
Dec_X <= '1';
end if;
if Inst(3 downto 0) = "1111" then -- POP
Rr_Addr <= std_logic_vector(SP_i + 1);
Inc_SP <= '1';
end if;
end if;
if Inst(15 downto 9) = "1001001" then
Rr_Addr(4 downto 0) <= Inst(8 downto 4);
if Inst(3 downto 0) = "0000" then
Rd_Addr <= ROM_Data;
end if;
if Inst(3 downto 0) = "0001" then
Rd_Addr <= std_logic_vector(Z);
Inc_Z <= '1';
end if;
if Inst(3 downto 0) = "0010" then
Rd_Addr <= std_logic_vector(Z - 1);
Dec_Z <= '1';
end if;
if Inst(3 downto 0) = "1001" then
Rd_Addr <= std_logic_vector(Y);
Inc_Y <= '1';
end if;
if Inst(3 downto 0) = "1010" then
Rd_Addr <= std_logic_vector(Y - 1);
Dec_Y <= '1';
end if;
if Inst(3 downto 0) = "1100" then
Rd_Addr <= std_logic_vector(X);
end if;
if Inst(3 downto 0) = "1101" then
Rd_Addr <= std_logic_vector(X);
Inc_X <= '1';
end if;
if Inst(3 downto 0) = "1110" then
Rd_Addr <= std_logic_vector(X - 1);
Dec_X <= '1';
end if;
if Inst(3 downto 0) = "1111" then -- PUSH
Rd_Addr <= std_logic_vector(SP_i);
Dec_SP <= '1';
end if;
end if;
else
if Inst(15 downto 9) = "1000000" then -- LD Z
Rd_Addr(4 downto 0) <= Inst(8 downto 4);
Rr_Addr <= std_logic_vector(Z);
end if;
if Inst(15 downto 9) = "1000001" then -- ST Z
Rr_Addr(4 downto 0) <= Inst(8 downto 4);
Rd_Addr <= std_logic_vector(Z);
end if;
end if;
end if;
if ((DidPause /= "01" and (Inst = "1001010100001001" or Inst(15 downto 12) = "1101")) or IPush = '1') and BigISet then
-- RCALL, ICALL
Rd_Addr <= std_logic_vector(SP_i);
Dec_SP <= '1';
end if;
if DidPause(0) = DidPause(1) and (Inst = "1001010100001000" or Inst = "1001010100011000") and BigISet then
-- RET, RETI
Rr_Addr <= std_logic_vector(SP_i + 1);
Inc_SP <= '1';
end if;
if DidPause = "00" and Inst = "1001010111001000" and BigISet then
-- LPM
Rd_Addr(4 downto 0) <= (others => '0');
end if;
end process;
process (Inst, DidPause, Rd_Addr, Rr_Addr, Dec_SP, Inc_SP, Z)
begin
IO_IR <= '0';
RAM_IR <= '0';
PMH_IR <= '0';
PML_IR <= '0';
Reg_IW <= '0';
IO_IW <= '0';
RAM_IW <= '0';
if (DidPause = "00" and
((Inst(15 downto 14) = "10" and Inst(12) = '0') or -- LDD/STD
Inst(15 downto 10) = "100100")) or -- LD/ST
(Dec_SP = '1' or Inc_SP = '1') then
if (Dec_SP = '0' and Inc_SP = '0' and Inst(9) = '0') or Inc_SP = '1' then -- LD
if Rr_Addr(15 downto 5) = "00000000000" then
elsif Rr_Addr(15 downto 7) = "000000000" and Rr_Addr(10 downto 9) /= "00" and Rr_Addr(10 downto 9) /= "11" then
IO_IR <= '1';
else
RAM_IR <= '1';
end if;
if not (Inst = "1001010100001000" or Inst = "1001010100011000") then -- not RETx
Reg_IW <= '1';
end if;
else
if Rd_Addr(15 downto 5) = "00000000000" then
Reg_IW <= '1';
elsif Rd_Addr(15 downto 7) = "000000000" and Rd_Addr(10 downto 9) /= "00" and Rd_Addr(10 downto 9) /= "11" then
IO_IW <= '1';
else
RAM_IW <= '1';
end if;
end if;
end if;
if DidPause = "00" and Inst = "1001010111001000" then
-- LPM
Reg_IW <= '1';
PMH_IR <= Z(0);
PML_IR <= not Z(0);
end if;
end process;
 
-- IO access
SP <= std_logic_vector(SP_i);
IO_Addr <= IO_Addr_i;
IO_Rd <= IO_Rd_i;
IO_Wr <= IO_Wr_i;
IO_WData <= IO_BMData when Inst(15 downto 11) = "10011" and Inst(8) = '0' else Rd_Data;
IO_BTest <= Bit_Pattern and IO_RData;
IOZ_Skip <= '1' when ((IO_BTest /= "00000000") and (Do_SBIS = '1')) or
((IO_BTest = "00000000") and (Do_SBIC = '1')) else '0';
process (Reset_n, Clk)
begin
if Reset_n = '0' then
if BigISet then
SP_i <= (others => '0');
end if;
IO_Addr_i <= (others => '0');
IO_BMData <= (others => '0');
IO_Wr_i <= '0';
Do_SBIC <= '0';
Do_SBIS <= '0';
elsif Clk'event and Clk = '1' then
Do_SBIC <= '0';
Do_SBIS <= '0';
if ROM_Data(15 downto 8) = "10011001" and PreDecode = '1' then
Do_SBIC <= '1';
end if;
if ROM_Data(15 downto 8) = "10011011" and PreDecode = '1' then
Do_SBIS <= '1';
end if;
if (Inst(15 downto 11) = "10011" and Inst(8) = '0' and DidPause(0) = '0') or
(ROM_Data(15 downto 11) = "10111" and PreDecode = '1') or IO_IW = '1' then
IO_Wr_i <= '1';
else
IO_Wr_i <= '0';
end if;
IO_BMData <= IO_RData;
IO_BMData(to_integer(unsigned(Inst(2 downto 0)))) <= Inst(9); -- CBI, SBI
if Inst(15 downto 10) /= "100110" or DidPause(0) = '1' then
if ROM_Data(13) = '0' then
IO_Addr_i <= "0" & ROM_Data(7 downto 3);
else
IO_Addr_i <= ROM_Data(10 downto 9) & ROM_Data(3 downto 0);
end if;
end if;
if IO_IR = '1' then
IO_Addr_i <= std_logic_vector(resize(unsigned(Rr_Addr) - 32, 6));
end if;
if IO_IW = '1' then
IO_Addr_i <= std_logic_vector(resize(unsigned(Rd_Addr) - 32, 6));
end if;
if IO_Wr_i = '1' and BigISet then
if IO_Addr_i = "111101" then --$3D ($5D) SPL Stack Pointer Low
SP_i(7 downto 0) <= unsigned(Rd_Data);
end if;
if IO_Addr_i = "111110" then --$3E ($5E) SPH Stack Pointer High
SP_i(15 downto 8) <= unsigned(Rd_Data);
end if;
end if;
if Dec_SP = '1' and BigISet then
SP_i <= SP_i - 1;
end if;
if Inc_SP = '1' and BigISet then
SP_i <= SP_i + 1;
end if;
end if;
end process;
 
-- Instruction register
Inst_Skip <= Z_Skip or RJmp or ZJmp or IOZ_Skip or Sleep or IPending or IPush;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Rst_r <= '1';
Inst <= (others => '0'); -- Force NOP at reset.
DidPause <= "00";
Bit_Pattern <= "00000000";
elsif Clk'event and Clk = '1' then
Rst_r <= '0';
if DidPause = "00" then
DidPause <= Pause;
else
DidPause <= std_logic_vector(unsigned(DidPause) - 1);
end if;
if (Pause /= "00" and DidPause = "00") or DidPause(1) = '1' then
-- Pause: instruction retained
elsif Rst_r = '1' or Inst_Skip = '1' then
-- Skip/flush: NOP insertion
Inst <= (others => '0');
else
Inst <= ROM_Data;
end if;
case ROM_Data(2 downto 0) is
when "000" =>
Bit_Pattern <= "00000001";
when "001" =>
Bit_Pattern <= "00000010";
when "010" =>
Bit_Pattern <= "00000100";
when "011" =>
Bit_Pattern <= "00001000";
when "100" =>
Bit_Pattern <= "00010000";
when "101" =>
Bit_Pattern <= "00100000";
when "110" =>
Bit_Pattern <= "01000000";
when others =>
Bit_Pattern <= "10000000";
end case;
end if;
end process;
 
-- Status register
SREG <= SREG_i;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
SREG_i <= "00000000";
elsif Clk'event and Clk = '1' then
if IO_Wr_i = '1' and IO_Addr_i = "111111" then --$3F ($5F) SREG Status Register
SREG_i <= Rd_Data;
end if;
if Inst(15 downto 8) = "10010100" and Inst(3 downto 0) = "1000" then
SREG_i(to_integer(unsigned(Inst(6 downto 4)))) <= not Inst(7); -- BSET, BCLR
end if;
if Inst = "1001010100011000" then SREG_i(7) <= '1'; end if;
if IPush = '1' then
SREG_i(7) <= '0';
end if;
if Status_Wr(6) = '1' then SREG_i(6) <= Status_D(6); end if;
if Status_Wr(5) = '1' then SREG_i(5) <= Status_D(5); end if;
if Status_Wr(4) = '1' then SREG_i(4) <= Status_D(4); end if;
if Status_Wr(3) = '1' then SREG_i(3) <= Status_D(3); end if;
if Status_Wr(2) = '1' then SREG_i(2) <= Status_D(2); end if;
if Status_Wr(1) = '1' then SREG_i(1) <= Status_D(1); end if;
if Status_Wr(0) = '1' then SREG_i(0) <= Status_D(0); end if;
if Status_D_Wr = '1' and BigISet then SREG_i(4 downto 0) <= Status_D_R; end if;
end if;
end process;
 
-- Registers
process (Clk)
begin
if Clk'event and Clk = '1' then
Add <= '0';
Sub <= '0';
if BigISet then
Status_D_Wr <= '0';
if ROM_Data(15 downto 8) = "10010110" and PreDecode = '1' then
Add <= '1';
end if;
if ROM_Data(15 downto 8) = "10010111" and PreDecode = '1' then
Sub <= '1';
end if;
if Inst(15 downto 9) = "1001011" and DidPause = "00" then
Status_D_Wr <= '1';
end if;
end if;
end if;
end process;
AS_Offset(5 downto 4) <= Inst(7 downto 6);
AS_Offset(3 downto 0) <= Inst(3 downto 0);
pr : AX_Reg
generic map(
BigISet => BigISet)
port map (
Clk => Clk,
Reset_n => Reset_n,
Wr => Reg_Wr,
Rd_Addr => Rd_Addr(4 downto 0),
Rr_Addr => Rr_Addr(4 downto 0),
Data_In => Wr_Data,
Rd_Data => Rd_Data,
Rr_Data => Rr_Data,
Add => Add,
Sub => Sub,
AS_Offset => AS_Offset,
AS_Reg => Inst(5 downto 4),
Dec_X => Dec_X,
Dec_Y => Dec_Y,
Dec_Z => Dec_Z,
Inc_X => Inc_X,
Inc_Y => Inc_Y,
Inc_Z => Inc_Z,
X => X,
Y => Y,
Z => Z,
Status_D => Status_D_R);
 
-- RAM
g1 : if BigISet generate
dr : AX_RAM
generic map(
RAMAddressWidth => RAMAddressWidth)
port map (
Clk => Clk,
Rd_Addr => Rr_Addr(RAMAddressWidth downto 0),
Wr_Addr => Rd_Addr(RAMAddressWidth downto 0),
Wr => RAM_Wr_ID,
Data_In => Wr_Data,
Data_Out => RAM_Data);
end generate;
 
-- Program counter
ROM_Addr <= "0" & std_logic_vector(Z(ROMAddressWidth - 1 downto 1))
when Inst = "1001010111001000" and DidPause = "00"
else NPC(ROMAddressWidth - 1 downto 0);
PCPause <= '1' when Rst_r = '1' or (IndSkip = '0' and ((Pause /= "00" and DidPause = "00") or DidPause(1) = '1')) or Sleep = '1' else '0';
RJmp <= '1' when Inst(15 downto 12) = "1100" or
(Inst(15 downto 12) = "1101" and DidPause = "10") or
(CBranch = '1' and Inst(10) = '0' and ((SREG_i and Bit_Pattern) /= "00000000")) or
(CBranch = '1' and Inst(10) = '1' and ((SREG_i and Bit_Pattern) = "00000000")) else '0';
HRet <= '1' when DidPause = "11" and BigIset and
(Inst = "1001010100001000" or Inst = "1001010100011000") else '0';
LRet <= '1' when DidPause = "10" and BigIset and
(Inst = "1001010100001000" or Inst = "1001010100011000") else '0';
ZJmp <= '1' when (Inst = "1001010000001001" or
(DidPause = "10" and Inst = "1001010100001001")) and BigIset else '0';
Push <= '1' when (Inst(15 downto 12) = "1101" or Inst = "1001010100001001") and DidPause = "00" and not BigIset else '0';
Pop <= '1' when Inst(15 downto 5) = "10010101000" and Inst(3 downto 0) = "1000" and DidPause = "00" and not BigIset else '0';
CBranch <= '1' when Inst(15 downto 11) = "11110" else '0';
-- Used for >=2 cycles instructions that are not skip, jump or branch
Pause <= "01" when (Inst(15 downto 14) = "10" and Inst(12) = '0') or -- LDD/STD
Inst(15 downto 10) = "100100" or -- LD/ST
(Inst(15 downto 11) = "10011" and Inst(8) = '0') or -- CBI/SBI
Inst(15 downto 9) = "1001011" else -- ADIW/SBIW
"10" when Inst(15 downto 12) = "1101" or -- RCALL
Inst = "1001010100001001" or -- ICALL
Inst = "1001010110001000" or -- SLEEP
Inst = "1001010111001000" else -- LPM
"11" when Inst = "1001010100001000" or -- RET
Inst = "1001010100011000" else "00"; -- RETI
IndSkip <= '1' when (Inst(15 downto 10) = "100100" and Inst(3 downto 0) = "0000") else '0';
Offset <= Inst(11 downto 0) when CBranch = '0' else
std_logic_vector(resize(signed(Inst(9 downto 3)),12));
pcnt : AX_PCS
generic map(
HW_Stack => not BigISet)
port map (
Clk => Clk,
Reset_n => Reset_n,
Offs_In => Offset,
Z => Z,
Data_In => Wr_Data,
Pause => PCPause,
Push => Push,
Pop => Pop,
HRet => HRet,
LRet => LRet,
ZJmp => ZJmp,
RJmp => RJmp,
CInt => CInt,
IPending => IPending,
IPush => IPush,
NPC => NPC,
PC => PC);
 
-- ALU
PassB <= '1' when (Pause /= "00" and DidPause /= "01") or IPush = '1' else '0';
gNoTri : if not TriState generate
Pass_Mux <= Inst(11 downto 8) & Inst(3 downto 0) when Imm_Op = '1' else
RAM_Data when RAM_Rd = '1' else
PCH when HPC_Rd = '1' and BigIset else
PC(7 downto 0) when LPC_Rd = '1' and BigIset else
Rr_Data when Reg_Rd = '1' else
ROM_Data(15 downto 8) when PMH_Rd = '1' and BigIset else
ROM_Data(7 downto 0) when PML_Rd = '1' and BigIset else
IO_RData;
end generate;
gTri : if TriState generate
Pass_Mux <= Inst(11 downto 8) & Inst(3 downto 0) when Imm_Op = '1' else "ZZZZZZZZ";
Pass_Mux <= IO_RData when IO_Rd_i = '1' else "ZZZZZZZZ";
Pass_Mux <= RAM_Data when RAM_Rd = '1' else "ZZZZZZZZ";
Pass_Mux <= PCH when HPC_Rd = '1' and BigIset else "ZZZZZZZZ";
Pass_Mux <= PC(7 downto 0) when LPC_Rd = '1' and BigIset else "ZZZZZZZZ";
Pass_Mux <= Rr_Data when Reg_Rd = '1' else "ZZZZZZZZ";
Pass_Mux <= ROM_Data(15 downto 8) when PMH_Rd = '1' and BigIset else "ZZZZZZZZ";
Pass_Mux <= ROM_Data(7 downto 0) when PML_Rd = '1' and BigIset else "ZZZZZZZZ";
end generate;
Wr_Data <= Pass_Mux when Do_Other = '1' else Q;
Op_Mux <= Inst(11 downto 8) & Inst(3 downto 0) when Imm_Op = '1' else Rr_Data;
process (Clk)
begin
if Clk'event and Clk = '1' then
PCH <= PC(15 downto 8);
IO_Rd_i <= '0';
Imm_Op <= '0';
RAM_Rd <= '0';
Reg_Rd <= '0';
HPC_Rd <= '0';
LPC_Rd <= '0';
PMH_Rd <= '0';
PML_Rd <= '0';
if (ROM_Data(15 downto 12) = "0011" or
ROM_Data(15 downto 14) = "01" or
ROM_Data(15 downto 12) = "1110") and
PreDecode = '1' then
Imm_Op <= '1';
elsif RAM_IR = '1' then
RAM_Rd <= '1';
elsif PMH_IR = '1' and BigIset then
PMH_Rd <= '1';
elsif PML_IR = '1' and BigIset then
PML_Rd <= '1';
elsif ((ROM_Data(15 downto 10) = "100110" or ROM_Data(15 downto 11) = "10110") and PreDecode = '1') or IO_IR = '1' then
IO_Rd_i <= '1';
elsif ((DidPause = "10" and (Inst = "1001010100001001" or Inst(15 downto 12) = "1101")) or
(IPush = '1' and IPending = '0')) and BigIset then
HPC_Rd <= '1';
elsif ((DidPause = "00" and (Inst = "1001010100001001" or Inst(15 downto 12) = "1101")) or
(IPush = '1' and IPending = '1')) and BigIset then
LPC_Rd <= '1';
else
Reg_Rd <= '1';
end if;
end if;
end process;
alu : AX_ALU
port map(
Clk => Clk,
ROM_Data => ROM_Data,
A => Rd_Data,
B => Op_Mux,
Q => Q,
SREG => SREG_i,
PassB => PassB,
Skip => Inst_Skip,
Do_Other => Do_Other,
Z_Skip => Z_Skip,
Status_D => Status_D,
Status_Wr => Status_Wr);
 
-- Interrupts and stuff
process (Reset_n, Clk)
begin
if Reset_n = '0' then
WDR <= '1';
Sleep <= '0';
CInt <= "0000";
Int_Acc <= (others => '0');
IPending <= '0';
elsif Clk'event and Clk = '1' then
if Inst = "1001010110101000" then
WDR <= '1';
else
WDR <= '0';
end if;
if Inst = "1001010110001000" and Sleep_En = '1' then
Sleep <= '1';
end if;
if Int_Trig /= "000000000000000" and SREG_i(7) = '1' then
Sleep <= '0';
IPending <= '1';
end if;
Int_Acc <= (others => '0');
if IPending = '1' and IPush = '1' then
IPending <= '0';
if Int_Trig(1) = '1' then CInt <= "0001"; Int_Acc(1) <= '1';
elsif Int_Trig(2) = '1' then CInt <= "0010"; Int_Acc(2) <= '1';
elsif Int_Trig(3) = '1' then CInt <= "0011"; Int_Acc(3) <= '1';
elsif Int_Trig(4) = '1' then CInt <= "0100"; Int_Acc(4) <= '1';
elsif Int_Trig(5) = '1' then CInt <= "0101"; Int_Acc(5) <= '1';
elsif Int_Trig(6) = '1' then CInt <= "0110"; Int_Acc(6) <= '1';
elsif Int_Trig(7) = '1' then CInt <= "0111"; Int_Acc(7) <= '1';
elsif Int_Trig(8) = '1' then CInt <= "1000"; Int_Acc(8) <= '1';
elsif Int_Trig(9) = '1' then CInt <= "1001"; Int_Acc(9) <= '1';
elsif Int_Trig(10) = '1' then CInt <= "1010"; Int_Acc(10) <= '1';
elsif Int_Trig(11) = '1' then CInt <= "1011"; Int_Acc(11) <= '1';
elsif Int_Trig(12) = '1' then CInt <= "1100"; Int_Acc(12) <= '1';
elsif Int_Trig(13) = '1' then CInt <= "1101"; Int_Acc(13) <= '1';
elsif Int_Trig(14) = '1' then CInt <= "1110"; Int_Acc(14) <= '1';
elsif Int_Trig(15) = '1' then CInt <= "1111"; Int_Acc(15) <= '1';
end if;
end if;
if Inst = "1001010100011000" then
CInt <= "0000";
end if;
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/AX_PCS.vhd
0,0 → 1,154
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/ax8/
--
-- Limitations :
-- Four level stack
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AX_PCS is
generic(
HW_Stack : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
Offs_In : in std_logic_vector(11 downto 0);
Z : in unsigned(15 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Pause : in std_logic;
Push : in std_logic;
Pop : in std_logic;
HRet : in std_logic;
LRet : in std_logic;
ZJmp : in std_logic;
RJmp : in std_logic;
CInt : in std_logic_vector(3 downto 0);
IPending : in std_logic;
IPush : out std_logic;
NPC : out std_logic_vector(15 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end AX_PCS;
 
architecture rtl of AX_PCS is
 
signal PC_i : unsigned(15 downto 0);
signal NPC_i : unsigned(15 downto 0);
signal IPush_i : std_logic;
 
type Stack_Image is array (3 downto 0) of unsigned(15 downto 0);
signal Stack : Stack_Image;
 
signal StackPtr : unsigned(1 downto 0);
 
begin
 
NPC <= std_logic_vector(NPC_i);
PC <= std_logic_vector(PC_i);
IPush <= IPush_i;
 
process (PC_i, Pause, IPending, IPush_i, Push, Pop, Stack, Data_In, Offs_In, CInt, HRet, LRet, RJmp, ZJmp, Z)
begin
NPC_i <= PC_i;
if Pause = '0' then
if IPending = '0' then
NPC_i <= PC_i + 1;
end if;
if IPending = '0' and IPush_i = '1' then
NPC_i(15 downto 4) <= "000000000000";
NPC_i(3 downto 0) <= unsigned(CInt);
end if;
end if;
if Pop = '1' and HW_Stack then
NPC_i <= Stack(to_integer(StackPtr - 1));
end if;
if HRet = '1' then
NPC_i(15 downto 8) <= unsigned(Data_In);
end if;
if LRet = '1' then
NPC_i(7 downto 0) <= unsigned(Data_In);
end if;
if ZJmp = '1' then
NPC_i <= Z;
end if;
if RJmp = '1' then
NPC_i <= PC_i + unsigned(resize(signed(Offs_In), 16));
end if;
end process;
 
process (Reset_n, Clk)
begin
if Reset_n = '0' then
PC_i <= (others => '0');
IPush_i <= '0';
if HW_Stack then
Stack <= (others => (others => '0'));
StackPtr <= "00";
end if;
elsif Clk'event and Clk = '1' then
PC_i <= NPC_i;
if Pause = '0' then
IPush_i <= IPending;
if IPending = '0' and IPush_i = '1' then
if HW_Stack then
Stack(to_integer(StackPtr)) <= PC_i;
StackPtr <= StackPtr + 1;
end if;
end if;
end if;
if Push = '1' and HW_Stack then
Stack(to_integer(StackPtr)) <= PC_i;
StackPtr <= StackPtr + 1;
end if;
if Pop = '1' and HW_Stack then
StackPtr <= StackPtr - 1;
end if;
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/A90S1200.vhd
0,0 → 1,320
--
-- 90S1200 compatible microcontroller core
--
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/ax8/
--
-- Limitations :
--
-- File history :
--
-- 0146 : First release
-- 0220 : Changed to synchronous ROM
-- 0220b : Changed reset
-- 0221 : Changed to configurable buses
-- 0224 : Fixed timer interrupt enable
 
--Registers: Comments:
--$3F SREG Status Register Implemented in the AX8 core
--$3B GIMSK General Interrupt Mask register
--$39 TIMSK Timer/Counter Interrupt Mask register
--$38 TIFR Timer/Counter Interrupt Flag register
--$35 MCUCR MCU general Control Register No power down
--$33 TCCR0 Timer/Counter 0 Control Register
--$32 TCNT0 Timer/Counter 0 (8-bit)
--$21 WDTCR Watchdog Timer Control Register Not implemented
--$1E EEAR EEPROM Address Register Not implemented
--$1D EEDR EEPROM Data Register Not implemented
--$1C EECR EEPROM Control Register Not implemented
--$18 PORTB Data Register, Port B No pullup
--$17 DDRB Data Direction Register, Port B
--$16 PINB Input Pins, Port B
--$12 PORTD Data Register, Port D No pullup
--$11 DDRD Data Direction Register, Port D
--$10 PIND Input Pins, Port D
--$08 ACSR Analog Comparator Control and Status Register Not implemented
 
library IEEE;
use IEEE.std_logic_1164.all;
use work.AX_Pack.all;
 
entity A90S1200 is
generic(
SyncReset : boolean := true;
TriState : boolean := false
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
INT0 : in std_logic;
T0 : in std_logic;
Port_B : inout std_logic_vector(7 downto 0);
Port_D : inout std_logic_vector(7 downto 0)
);
end A90S1200;
 
architecture rtl of A90S1200 is
 
constant ROMAddressWidth : integer := 9;
constant RAMAddressWidth : integer := 0;
constant BigISet : boolean := false;
 
component ROM1200
port(
Clk : in std_logic;
A : in std_logic_vector(ROMAddressWidth - 1 downto 0);
D : out std_logic_vector(15 downto 0)
);
end component;
 
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
signal ROM_Data : std_logic_vector(15 downto 0);
signal SREG : std_logic_vector(7 downto 0);
signal IO_Rd : std_logic;
signal IO_Wr : std_logic;
signal IO_Addr : std_logic_vector(5 downto 0);
signal IO_WData : std_logic_vector(7 downto 0);
signal IO_RData : std_logic_vector(7 downto 0);
signal TCCR_Sel : std_logic;
signal TCNT_Sel : std_logic;
signal PORTB_Sel : std_logic;
signal DDRB_Sel : std_logic;
signal PINB_Sel : std_logic;
signal PORTD_Sel : std_logic;
signal DDRD_Sel : std_logic;
signal PIND_Sel : std_logic;
signal Sleep_En : std_logic;
signal ISC0 : std_logic_vector(1 downto 0);
signal Int0_ET : std_logic;
signal Int0_En : std_logic;
signal Int0_r : std_logic_vector(1 downto 0);
signal TC_Trig : std_logic;
signal TOIE0 : std_logic;
signal TOV0 : std_logic;
signal Int_Trig : std_logic_vector(15 downto 1);
signal Int_Acc : std_logic_vector(15 downto 1);
signal TCCR : std_logic_vector(2 downto 0);
signal TCNT : std_logic_vector(7 downto 0);
signal DirB : std_logic_vector(7 downto 0);
signal Port_InB : std_logic_vector(7 downto 0);
signal Port_OutB : std_logic_vector(7 downto 0);
signal DirD : std_logic_vector(7 downto 0);
signal Port_InD : std_logic_vector(7 downto 0);
signal Port_OutD : std_logic_vector(7 downto 0);
 
begin
 
-- Synchronise reset
process (Reset_n, Clk)
variable Reset_v : std_logic;
begin
if Reset_n = '0' then
if SyncReset then
Reset_s_n <= '0';
Reset_v := '0';
end if;
elsif Clk'event and Clk = '1' then
if SyncReset then
Reset_s_n <= Reset_v;
Reset_v := '1';
end if;
end if;
end process;
 
g_reset : if not SyncReset generate
Reset_s_n <= Reset_n;
end generate;
 
-- Registers/Interrupts
process (Reset_s_n, Clk)
begin
if Reset_s_n = '0' then
Sleep_En <= '0';
ISC0 <= "00";
Int0_ET <= '0';
Int0_En <= '0';
Int0_r <= "11";
TOIE0 <= '0';
TOV0 <= '0';
elsif Clk'event and Clk = '1' then
Int0_r(0) <= INT0;
Int0_r(1) <= Int0_r(0);
if IO_Wr = '1' and IO_Addr = "110101" then -- $35 MCUCR
Sleep_En <= IO_WData(5);
ISC0 <= IO_WData(1 downto 0);
end if;
if IO_Wr = '1' and IO_Addr = "111011" then -- $3B GIMSK
Int0_En <= IO_WData(6);
end if;
if IO_Wr = '1' and IO_Addr = "111001" then -- $39 TIMSK
TOIE0 <= IO_WData(1);
end if;
if IO_Wr = '1' and IO_Addr = "111000" then -- $38 TIFR
if IO_WData(1) = '1' then
TOV0 <= '0';
end if;
end if;
if Int_Acc(2) = '1' then
TOV0 <= '0';
end if;
if TC_Trig = '1' then
TOV0 <= '1';
end if;
if Int_Acc(1) = '1' then
Int0_ET <= '0';
end if;
if (ISC0 = "10" and Int0_r = "10") or (ISC0 = "11" and Int0_r = "01") then
Int0_ET <= '1';
end if;
end if;
end process;
 
Int_Trig(1) <= '0' when Int0_En = '0' else not Int0_r(1) when ISC0 = "00" else Int0_ET;
Int_Trig(2) <= '1' when TOIE0 = '1' and TOV0 = '1' else '0';
Int_Trig(15 downto 3) <= (others => '0');
 
rom : ROM1200 port map (
Clk => Clk,
A => ROM_Addr,
D => ROM_Data);
 
ax : AX8
generic map(
ROMAddressWidth => ROMAddressWidth,
RAMAddressWidth => RAMAddressWidth,
BigIset => BigIset)
port map (
Clk => Clk,
Reset_n => Reset_s_n,
ROM_Addr => ROM_Addr,
ROM_Data => ROM_Data,
Sleep_En => Sleep_En,
Int_Trig => Int_Trig,
Int_Acc => Int_Acc,
SREG => SREG,
IO_Rd => IO_Rd,
IO_Wr => IO_Wr,
IO_Addr => IO_Addr,
IO_RData => IO_RData,
IO_WData => IO_WData);
 
TCCR_Sel <= '1' when IO_Addr = "110011" else '0'; -- $33 TCCR0
TCNT_Sel <= '1' when IO_Addr = "110010" else '0'; -- $32 TCNT0
tc : AX_TC8 port map(
Clk => Clk,
Reset_n => Reset_s_n,
T => T0,
TCCR_Sel => TCCR_Sel,
TCNT_Sel => TCNT_Sel,
Wr => IO_Wr,
Data_In => IO_WData,
TCCR => TCCR,
TCNT => TCNT,
Int => TC_Trig);
 
PINB_Sel <= '1' when IO_Addr = "010101" else '0';
DDRB_Sel <= '1' when IO_Addr = "010111" else '0';
PORTB_Sel <= '1' when IO_Addr = "011000" else '0';
PIND_Sel <= '1' when IO_Addr = "010000" else '0';
DDRD_Sel <= '1' when IO_Addr = "010001" else '0';
PORTD_Sel <= '1' when IO_Addr = "010010" else '0';
portb : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTB_Sel,
DDR_Sel => DDRB_Sel,
PIN_Sel => PINB_Sel,
Wr => IO_Wr,
Data_In => IO_WData,
Dir => DirB,
Port_Input => Port_InB,
Port_Output => Port_OutB,
IOPort => Port_B);
portd : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTD_Sel,
DDR_Sel => DDRD_Sel,
PIN_Sel => PIND_Sel,
Wr => IO_Wr,
Data_In => IO_WData,
Dir => DirD,
Port_Input => Port_InD,
Port_Output => Port_OutD,
IOPort => Port_D);
 
gNoTri : if not TriState generate
with IO_Addr select
IO_RData <= SREG when "111111",
"00" & Sleep_En & "000" & ISC0 when "110101",
"0" & Int0_En & "000000" when "111011",
"000000" & TOIE0 & "0" when "111001",
"000000" & TOV0 & "0" when "111000",
"00000" & TCCR when "110011",
TCNT when "110010",
Port_InB when "010101",
DirB when "010111",
Port_OutB when "011000",
Port_InD when "010000",
DirD when "010001",
Port_OutD when "010010",
"--------" when others;
end generate;
gTri : if TriState generate
IO_RData <= SREG when IO_Addr = "111111" else "ZZZZZZZZ";
 
IO_RData <= "00" & Sleep_En & "000" & ISC0 when IO_Addr = "110101" else "ZZZZZZZZ";
IO_RData <= "0" & Int0_En & "000000" when IO_Addr = "111011" else "ZZZZZZZZ";
IO_RData <= "000000" & TOIE0 & "0" when IO_Addr = "111001" else "ZZZZZZZZ";
IO_RData <= "000000" & TOV0 & "0" when IO_Addr = "111000" else "ZZZZZZZZ";
 
IO_RData <= "00000" & TCCR when TCCR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= TCNT when TCNT_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InB when PINB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirB when DDRB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutB when PORTB_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InD when PIND_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirD when DDRD_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutD when PORTD_Sel = '1' else "ZZZZZZZZ";
end generate;
 
end;
/ax8/trunk/rtl/vhdl/A90S2313.vhd
0,0 → 1,505
--
-- 90S2313 compatible microcontroller core
--
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/ax8/
--
-- Limitations :
--
-- File history :
--
-- 0146 : First release
-- 0220 : Changed to synchronous ROM
-- 0220b : Changed reset
-- 0221 : Changed to configurable buses
-- 0224 : Fixed timer interrupt enables
 
--Registers: Comments:
--$3F SREG Status Register Implemented in the AX8 core
--$3D SPL Stack Pointer Low Implemented in the AX8 core
--$3B GIMSK General Interrupt Mask register
--$3A GIFR General Interrupt Flag Register
--$39 TIMSK Timer/Counter Interrupt Mask register
--$38 TIFR Timer/Counter Interrupt Flag register
--$35 MCUCR MCU General Control Register No power down
--$33 TCCR0 Timer/Counter 0 Control Register
--$32 TCNT0 Timer/Counter 0 (8-bit)
--$2F TCCR1A Timer/Counter 1 Control Register A
--$2E TCCR1B Timer/Counter 1 Control Register B
--$2D TCNT1H Timer/Counter 1 High Byte
--$2C TCNT1L Timer/Counter 1 Low Byte
--$2B OCR1AH Output Compare Register 1 High Byte
--$2A OCR1AL Output Compare Register 1 Low Byte
--$25 ICR1H T/C 1 Input Capture Register High Byte
--$24 ICR1L T/C 1 Input Capture Register Low Byte
--$21 WDTCR Watchdog Timer Control Register Not implemented
--$1E EEAR EEPROM Address Register Not implemented
--$1D EEDR EEPROM Data Register Not implemented
--$1C EECR EEPROM Control Register Not implemented
--$18 PORTB Data Register, Port B No pullup
--$17 DDRB Data Direction Register, Port B
--$16 PINB Input Pins, Port B
--$12 PORTD Data Register, Port D No pullup
--$11 DDRD Data Direction Register, Port D
--$10 PIND Input Pins, Port D
--$0C UDR UART I/O Data Register
--$0B USR UART Status Register
--$0A UCR UART Control Register
--$09 UBRR UART Baud Rate Register
--$08 ACSR Analog Comparator Control and Status Register Not implemented
 
library IEEE;
use IEEE.std_logic_1164.all;
use work.AX_Pack.all;
 
entity A90S2313 is
generic(
SyncReset : boolean := true;
TriState : boolean := false
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
INT0 : in std_logic;
INT1 : in std_logic;
T0 : in std_logic;
T1 : in std_logic;
ICP : in std_logic;
RXD : in std_logic;
TXD : out std_logic;
OC : out std_logic;
Port_B : inout std_logic_vector(7 downto 0);
Port_D : inout std_logic_vector(7 downto 0)
);
end A90S2313;
 
architecture rtl of A90S2313 is
 
constant ROMAddressWidth : integer := 10;
constant RAMAddressWidth : integer := 7;
constant BigISet : boolean := true;
 
component ROM2313
port(
Clk : in std_logic;
A : in std_logic_vector(ROMAddressWidth - 1 downto 0);
D : out std_logic_vector(15 downto 0)
);
end component;
 
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
signal ROM_Data : std_logic_vector(15 downto 0);
signal SREG : std_logic_vector(7 downto 0);
signal SP : std_logic_vector(15 downto 0);
signal IO_Rd : std_logic;
signal IO_Wr : std_logic;
signal IO_Addr : std_logic_vector(5 downto 0);
signal IO_WData : std_logic_vector(7 downto 0);
signal IO_RData : std_logic_vector(7 downto 0);
signal TCCR0_Sel : std_logic;
signal TCNT0_Sel : std_logic;
signal TCCR1_Sel : std_logic;
signal TCNT1_Sel : std_logic;
signal OCR1_Sel : std_logic;
signal ICR1_Sel : std_logic;
signal UDR_Sel : std_logic;
signal USR_Sel : std_logic;
signal UCR_Sel : std_logic;
signal UBRR_Sel : std_logic;
signal PORTB_Sel : std_logic;
signal DDRB_Sel : std_logic;
signal PINB_Sel : std_logic;
signal PORTD_Sel : std_logic;
signal DDRD_Sel : std_logic;
signal PIND_Sel : std_logic;
signal Sleep_En : std_logic;
signal ISC0 : std_logic_vector(1 downto 0);
signal ISC1 : std_logic_vector(1 downto 0);
signal Int_ET : std_logic_vector(1 downto 0);
signal Int_En : std_logic_vector(1 downto 0);
signal Int0_r : std_logic_vector(1 downto 0);
signal Int1_r : std_logic_vector(1 downto 0);
signal TC_Trig : std_logic;
signal TO_Trig : std_logic;
signal OC_Trig : std_logic;
signal IC_Trig : std_logic;
signal TOIE0 : std_logic;
signal TICIE1 : std_logic;
signal OCIE1 : std_logic;
signal TOIE1 : std_logic;
signal TOV0 : std_logic;
signal ICF1 : std_logic;
signal OCF1 : std_logic;
signal TOV1 : std_logic;
signal Int_Trig : std_logic_vector(15 downto 1);
signal Int_Acc : std_logic_vector(15 downto 1);
signal TCCR0 : std_logic_vector(2 downto 0);
signal TCNT0 : std_logic_vector(7 downto 0);
signal COM : std_logic_vector(1 downto 0);
signal PWM : std_logic_vector(1 downto 0);
signal CRBH : std_logic_vector(1 downto 0);
signal CRBL : std_logic_vector(3 downto 0);
signal TCNT1 : std_logic_vector(15 downto 0);
signal IC : std_logic_vector(15 downto 0);
signal OCR : std_logic_vector(15 downto 0);
signal Tmp : std_logic_vector(15 downto 0);
signal UDR : std_logic_vector(7 downto 0);
signal USR : std_logic_vector(7 downto 3);
signal UCR : std_logic_vector(7 downto 0);
signal UBRR : std_logic_vector(7 downto 0);
signal DirB : std_logic_vector(7 downto 0);
signal Port_InB : std_logic_vector(7 downto 0);
signal Port_OutB : std_logic_vector(7 downto 0);
signal DirD : std_logic_vector(7 downto 0);
signal Port_InD : std_logic_vector(7 downto 0);
signal Port_OutD : std_logic_vector(7 downto 0);
 
begin
 
-- Synchronise reset
process (Reset_n, Clk)
variable Reset_v : std_logic;
begin
if Reset_n = '0' then
if SyncReset then
Reset_s_n <= '0';
Reset_v := '0';
end if;
elsif Clk'event and Clk = '1' then
if SyncReset then
Reset_s_n <= Reset_v;
Reset_v := '1';
end if;
end if;
end process;
 
g_reset : if not SyncReset generate
Reset_s_n <= Reset_n;
end generate;
 
-- Registers/Interrupts
process (Reset_s_n, Clk)
begin
if Reset_s_n = '0' then
Sleep_En <= '0';
ISC0 <= "00";
ISC1 <= "00";
Int_ET <= "00";
Int_En <= "00";
Int0_r <= "11";
Int1_r <= "11";
TOIE0 <= '0';
TICIE1 <= '0';
OCIE1 <= '0';
TOIE1 <= '0';
TOV0 <= '0';
ICF1 <= '0';
OCF1 <= '0';
TOV1 <= '0';
elsif Clk'event and Clk = '1' then
Int0_r(0) <= INT0;
Int0_r(1) <= Int0_r(0);
Int1_r(0) <= INT1;
Int1_r(1) <= Int1_r(0);
if IO_Wr = '1' and IO_Addr = "110101" then -- $35 MCUCR
Sleep_En <= IO_WData(5);
ISC0 <= IO_WData(1 downto 0);
ISC1 <= IO_WData(3 downto 2);
end if;
if IO_Wr = '1' and IO_Addr = "111011" then -- $3B GIMSK
Int_En <= IO_WData(7 downto 6);
end if;
if IO_Wr = '1' and IO_Addr = "111001" then -- $39 TIMSK
TOIE0 <= IO_WData(1);
TICIE1 <= IO_WData(3);
OCIE1 <= IO_WData(6);
TOIE1 <= IO_WData(7);
end if;
if IO_Wr = '1' and IO_Addr = "111000" then -- $38 TIFR
if IO_WData(1) = '1' then
TOV0 <= '0';
end if;
if IO_WData(3) = '1' then
ICF1 <= '0';
end if;
if IO_WData(6) = '1' then
OCF1 <= '0';
end if;
if IO_WData(7) = '1' then
TOV1 <= '0';
end if;
end if;
if Int_Acc(3) = '1' then
ICF1 <= '0';
end if;
if Int_Acc(4) = '1' then
OCF1 <= '0';
end if;
if Int_Acc(5) = '1' then
TOV1 <= '0';
end if;
if Int_Acc(6) = '1' then
TOV0 <= '0';
end if;
if TC_Trig = '1' then
TOV0 <= '1';
end if;
if IC_Trig = '1' then
ICF1 <= '1';
end if;
if OC_Trig = '1' then
OCF1 <= '1';
end if;
if TO_Trig = '1' then
TOV1 <= '1';
end if;
if Int_Acc(1) = '1' then
Int_ET(0) <= '0';
end if;
if (ISC0 = "10" and Int0_r = "10") or (ISC0 = "11" and Int0_r = "01") then
Int_ET(0) <= '1';
end if;
if Int_Acc(2) = '1' then
Int_ET(1) <= '0';
end if;
if (ISC1 = "10" and Int1_r = "10") or (ISC1 = "11" and Int1_r = "01") then
Int_ET(1) <= '1';
end if;
end if;
end process;
 
Int_Trig(1) <= '0' when Int_En(0) = '0' else not Int0_r(1) when ISC0 = "00" else Int_ET(0);
Int_Trig(2) <= '0' when Int_En(1) = '0' else not Int1_r(1) when ISC1 = "00" else Int_ET(1);
Int_Trig(3) <= '1' when TICIE1 = '1' and ICF1 = '1' else '0';
Int_Trig(4) <= '1' when OCIE1 = '1' and OCF1 = '1' else '0';
Int_Trig(5) <= '1' when TOIE1 = '1' and TOV1 = '1' else '0';
Int_Trig(6) <= '1' when TOIE0 = '1' and TOV0 = '1' else '0';
Int_Trig(15 downto 10) <= (others => '0');
 
rom : ROM2313 port map(
Clk => Clk,
A => ROM_Addr,
D => ROM_Data);
 
ax : AX8
generic map(
ROMAddressWidth => ROMAddressWidth,
RAMAddressWidth => RAMAddressWidth,
BigIset => BigIset)
port map(
Clk => Clk,
Reset_n => Reset_s_n,
ROM_Addr => ROM_Addr,
ROM_Data => ROM_Data,
Sleep_En => Sleep_En,
Int_Trig => Int_Trig,
Int_Acc => Int_Acc,
SREG => SREG,
SP => SP,
IO_Rd => IO_Rd,
IO_Wr => IO_Wr,
IO_Addr => IO_Addr,
IO_RData => IO_RData,
IO_WData => IO_WData);
 
TCCR0_Sel <= '1' when IO_Addr = "110011" else '0'; -- $33 TCCR0
TCNT0_Sel <= '1' when IO_Addr = "110010" else '0'; -- $32 TCNT0
tc0 : AX_TC8 port map(
Clk => Clk,
Reset_n => Reset_s_n,
T => T0,
TCCR_Sel => TCCR0_Sel,
TCNT_Sel => TCNT0_Sel,
Wr => IO_Wr,
Data_In => IO_WData,
TCCR => TCCR0,
TCNT => TCNT0,
Int => TC_Trig);
 
TCCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10111" else '0'; -- $2E TCCR1
TCNT1_Sel <= '1' when IO_Addr(5 downto 1) = "10110" else '0'; -- $2C TCNT1
OCR1_Sel <= '1' when IO_Addr(5 downto 1) = "10101" else '0'; -- $2A OCR1
ICR1_Sel <= '1' when IO_Addr(5 downto 1) = "10100" else '0'; -- $24 ICR1
tc1 : AX_TC16 port map(
Clk => Clk,
Reset_n => Reset_s_n,
T => T1,
ICP => ICP,
TCCR_Sel => TCCR1_Sel,
TCNT_Sel => TCNT1_Sel,
OCR_Sel => OCR1_Sel,
ICR_Sel => ICR1_Sel,
A0 => IO_Addr(0),
Rd => IO_Rd,
Wr => IO_Wr,
Data_In => IO_WData,
COM => COM,
PWM => PWM,
CRBH => CRBH,
CRBL => CRBL,
TCNT => TCNT1,
IC => IC,
OCR => OCR,
Tmp => Tmp,
OC => OC,
Int_TO => TO_Trig,
Int_OC => OC_Trig,
Int_IC => IC_Trig);
 
UDR_Sel <= '1' when IO_Addr = "001100" else '0';
USR_Sel <= '1' when IO_Addr = "001011" else '0';
UCR_Sel <= '1' when IO_Addr = "001010" else '0';
UBRR_Sel <= '1' when IO_Addr = "001001" else '0';
uart : AX_UART port map(
Clk => Clk,
Reset_n => Reset_s_n,
UDR_Sel => UDR_Sel,
USR_Sel => USR_Sel,
UCR_Sel => UCR_Sel,
UBRR_Sel => UBRR_Sel,
Rd => IO_Rd,
Wr => IO_Wr,
TXC_Clr => Int_Acc(9),
Data_In => IO_WData,
UDR => UDR,
USR => USR,
UCR => UCR,
UBRR => UBRR,
RXD => RXD,
TXD => TXD,
Int_RX => Int_Trig(7),
Int_TR => Int_Trig(8),
Int_TC => Int_Trig(9));
 
PINB_Sel <= '1' when IO_Addr = "010101" else '0';
DDRB_Sel <= '1' when IO_Addr = "010111" else '0';
PORTB_Sel <= '1' when IO_Addr = "011000" else '0';
PIND_Sel <= '1' when IO_Addr = "010000" else '0';
DDRD_Sel <= '1' when IO_Addr = "010001" else '0';
PORTD_Sel <= '1' when IO_Addr = "010010" else '0';
portb : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTB_Sel,
DDR_Sel => DDRB_Sel,
PIN_Sel => PINB_Sel,
Wr => IO_Wr,
Data_In => IO_WData,
Dir => DirB,
Port_Input => Port_InB,
Port_Output => Port_OutB,
IOPort => Port_B);
portd : AX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
PORT_Sel => PORTD_Sel,
DDR_Sel => DDRD_Sel,
PIN_Sel => PIND_Sel,
Wr => IO_Wr,
Data_In => IO_WData,
Dir => DirD,
Port_Input => Port_InD,
Port_Output => Port_OutD,
IOPort => Port_D);
 
gNoTri : if not TriState generate
with IO_Addr select
IO_RData <= SREG when "111111",
SP(7 downto 0) when "111101",
SP(15 downto 8) when "111110",
"00" & Sleep_En & "0" & ISC1 & ISC0 when "110101",
Int_En & "000000" when "111011",
TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when "111001",
TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when "111000",
UDR when "001100",
USR & "000" when "001011",
UCR(7 downto 1) & "0" when "001010",
UBRR when "001001",
"00000" & TCCR0 when "110011",
TCNT0 when "110010",
COM & "0000" & PWM when "101111",
CRBH & "00" & CRBL when "101110",
TCNT1(7 downto 0) when "101100",
OCR(7 downto 0) when "101010",
IC(7 downto 0) when "101000",
Tmp(15 downto 8) when "101101" | "101001" | "101011",
Port_InB when "010101",
DirB when "010111",
Port_OutB when "011000",
Port_InD when "010000",
DirD when "010001",
Port_OutD when "010010",
"--------" when others;
end generate;
gTri : if TriState generate
IO_RData <= SREG when IO_Addr = "111111" else "ZZZZZZZZ";
IO_RData <= SP(7 downto 0) when IO_Addr = "111101" and BigIset else "ZZZZZZZZ";
IO_RData <= SP(15 downto 8) when IO_Addr = "111110" and BigIset else "ZZZZZZZZ";
 
IO_RData <= "00" & Sleep_En & "0" & ISC1 & ISC0 when IO_Addr = "110101" else "ZZZZZZZZ";
IO_RData <= Int_En & "000000" when IO_Rd = '1' and IO_Addr = "111011" else "ZZZZZZZZ";
IO_RData <= TOIE1 & OCIE1 & "00" & TICIE1 & "0" & TOIE0 & "0" when IO_Addr = "111001" else "ZZZZZZZZ";
IO_RData <= TOV1 & OCF1 & "00" & ICF1 & "0" & TOV0 & "0" when IO_Addr = "111000" else "ZZZZZZZZ";
 
IO_RData <= UDR when UDR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= USR & "000" when USR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= UCR(7 downto 1) & "0" when UCR_Sel = '1' else "ZZZZZZZZ";
IO_RData <= UBRR when UBRR_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= "00000" & TCCR0 when TCCR0_Sel = '1' else "ZZZZZZZZ";
IO_RData <= TCNT0 when TCNT0_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= COM & "0000" & PWM when TCCR1_Sel = '1' and IO_Addr(0) = '1' else "ZZZZZZZZ";
IO_RData <= CRBH & "00" & CRBL when TCCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= TCNT1(7 downto 0) when TCNT1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= OCR(7 downto 0) when OCR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= IC(7 downto 0) when ICR1_Sel = '1' and IO_Addr(0) = '0' else "ZZZZZZZZ";
IO_RData <= Tmp(15 downto 8) when (TCNT1_Sel = '1' or ICR1_Sel = '1' or OCR1_Sel = '1') and IO_Addr(0) = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InB when PINB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirB when DDRB_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutB when PORTB_Sel = '1' else "ZZZZZZZZ";
 
IO_RData <= Port_InD when PIND_Sel = '1' else "ZZZZZZZZ";
IO_RData <= DirD when DDRD_Sel = '1' else "ZZZZZZZZ";
IO_RData <= Port_OutD when PORTD_Sel = '1' else "ZZZZZZZZ";
end generate;
 
end;
/ax8/trunk/rtl/vhdl/AX_UART.vhd
0,0 → 1,290
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AX_UART is
port(
Clk : in std_logic;
Reset_n : in std_logic;
UDR_Sel : in std_logic;
USR_Sel : in std_logic;
UCR_Sel : in std_logic;
UBRR_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
TXC_Clr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
UDR : out std_logic_vector(7 downto 0);
USR : out std_logic_vector(7 downto 3);
UCR : out std_logic_vector(7 downto 0);
UBRR : out std_logic_vector(7 downto 0);
RXD : in std_logic;
TXD : out std_logic;
Int_RX : out std_logic;
Int_TR : out std_logic;
Int_TC : out std_logic
);
end AX_UART;
 
architecture rtl of AX_UART is
 
signal UDR_i : std_logic_vector(7 downto 0); -- UART I/O Data Register
signal USR_i : std_logic_vector(7 downto 3); -- UART Status Register
signal UCR_i : std_logic_vector(7 downto 0); -- UART Control Register
signal UBRR_i : std_logic_vector(7 downto 0); -- UART Baud Rate Register
 
signal Baud16 : std_logic;
 
signal Bit_Phase : unsigned(3 downto 0);
signal RX_Filtered : std_logic;
signal RX_ShiftReg : std_logic_vector(8 downto 0);
signal RX_Bit_Cnt : integer range 0 to 11;
signal Overflow_t : std_logic;
 
signal TX_Tick : std_logic;
signal TX_Data : std_logic_vector(7 downto 0);
signal TX_ShiftReg : std_logic_vector(8 downto 0);
signal TX_Bit_Cnt : integer range 0 to 11;
 
begin
 
-- Registers
UDR <= UDR_i;
USR <= USR_i;
UCR <= UCR_i;
UBRR <= UBRR_i;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
UCR_i(7 downto 2) <= "000000";
UCR_i(0) <= '0';
UBRR_i <= "00000000";
elsif Clk'event and Clk = '1' then
if UCR_Sel = '1' and Wr = '1' then
UCR_i(7 downto 2) <= Data_In(7 downto 2);
UCR_i(0) <= Data_In(0);
end if;
if UBRR_Sel = '1' and Wr = '1' then
UBRR_i <= Data_In;
end if;
end if;
end process;
 
-- Baud x 16 clock generator
process (Clk, Reset_n)
variable Baud_Cnt : unsigned(7 downto 0);
begin
if Reset_n = '0' then
Baud_Cnt := "00000000";
Baud16 <= '0';
elsif Clk'event and Clk='1' then
if Baud_Cnt = "00000000" then
Baud_Cnt := unsigned(UBRR_i);
Baud16 <= '1';
else
Baud_Cnt := Baud_Cnt - 1;
Baud16 <= '0';
end if;
end if;
end process;
 
-- Input filter
process (Clk, Reset_n)
variable Samples : std_logic_vector(1 downto 0);
begin
if Reset_n = '0' then
Samples := "11";
RX_Filtered <= '1';
elsif Clk'event and Clk = '1' then
if Baud16 = '1' then
Samples(1) := Samples(0);
Samples(0) := RXD;
end if;
if Samples = "00" then
RX_Filtered <= '0';
end if;
if Samples = "11" then
RX_Filtered <= '1';
end if;
end if;
end process;
 
-- Receive state machine
Int_RX <= USR_i(7) and UCR_i(7);
process (Clk, Reset_n)
begin
if Reset_n = '0' then
USR_i(7) <= '0';
USR_i(4) <= '0';
USR_i(3) <= '0';
UCR_i(1) <= '1';
UDR_i <= "00000000";
Overflow_t <= '0';
Bit_Phase <= "0000";
RX_ShiftReg(8 downto 0) <= "000000000";
RX_Bit_Cnt <= 0;
elsif Clk'event and Clk = '1' then
if UDR_Sel = '1' and Rd = '1' then
USR_i(7) <= '0';
USR_i(3) <= Overflow_t;
end if;
if Baud16 = '1' then
if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
Bit_Phase <= "0000";
else
Bit_Phase <= Bit_Phase + 1;
end if;
if RX_Bit_Cnt = 0 then
if Bit_Phase = "0111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
end if;
elsif Bit_Phase = "1111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
if (UCR_i(2) = '0' and RX_Bit_Cnt = 9) or
(UCR_i(2) = '1' and RX_Bit_Cnt = 10) then -- Stop bit
RX_Bit_Cnt <= 0;
if UCR_i(4) = '1' then
USR_i(7) <= '1'; -- UART Receive complete
USR_i(4) <= not RX_Filtered; -- Framing error
Overflow_t <= USR_i(7);
if USR_i(7) = '0' or (UDR_Sel = '1' and Rd = '1') then
Overflow_t <= '0';
USR_i(3) <= '0';
UDR_i <= RX_ShiftReg(7 downto 0);
UCR_i(1) <= RX_ShiftReg(8);
end if;
end if;
else
RX_ShiftReg(7 downto 0) <= RX_ShiftReg(8 downto 1);
if UCR_i(2) = '1' then -- CHR9
RX_ShiftReg(8) <= RX_Filtered;
else
RX_ShiftReg(7) <= RX_Filtered;
end if;
end if;
end if;
end if;
end if;
end process;
 
-- Transmit bit tick
process (Clk, Reset_n)
variable TX_Cnt : unsigned(3 downto 0);
begin
if Reset_n = '0' then
TX_Cnt := "0000";
TX_Tick <= '0';
elsif Clk'event and Clk = '1' then
TX_Tick <= '0';
if Baud16 = '1' then
if TX_Cnt = "1111" then
TX_Tick <= '1';
end if;
TX_Cnt := TX_Cnt + 1;
end if;
end if;
end process;
 
-- Transmit state machine
Int_TR <= USR_i(5) and UCR_i(5);
Int_TC <= USR_i(6) and UCR_i(6);
process (Clk, Reset_n)
begin
if Reset_n = '0' then
USR_i(6) <= '0';
USR_i(5) <= '1';
TX_Bit_Cnt <= 0;
TX_ShiftReg <= (others => '0');
TX_Data <= (others => '0');
TXD <= '1';
elsif Clk'event and Clk = '1' then
if TXC_Clr = '1' or (USR_Sel = '1' and Wr = '1' and Data_In(6) = '1') then
USR_i(6) <= '0';
end if;
if UDR_Sel = '1' and Wr = '1' and UCR_i(3) = '1' then
USR_i(5) <= '0';
TX_Data <= Data_In;
end if;
if TX_Tick = '1' then
case TX_Bit_Cnt is
when 0 =>
if USR_i(5) = '0' then
TX_Bit_Cnt <= 1;
end if;
TXD <= '1';
when 1 => -- Start bit
TX_ShiftReg(7 downto 0) <= TX_Data;
TX_ShiftReg(8) <= UCR_i(0);
USR_i(5) <= '1';
TXD <= '0';
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
when others =>
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
if UCR_i(2) = '1' then -- CHR9
if TX_Bit_Cnt = 10 then
TX_Bit_Cnt <= 0;
USR_i(6) <= '1';
end if;
else
if TX_Bit_Cnt = 9 then
TX_Bit_Cnt <= 0;
USR_i(6) <= '1';
end if;
end if;
TXD <= TX_ShiftReg(0);
TX_ShiftReg(7 downto 0) <= TX_ShiftReg(8 downto 1);
end case;
end if;
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/AX_Reg.vhd
0,0 → 1,285
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221b
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0221 : Moved register bank to separate file
-- 0221 : Changed buses
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.AX_Pack.all;
 
entity AX_Reg is
generic(
BigISet : boolean;
TriState : boolean := false
);
port (
Clk : in std_logic;
Reset_n : in std_logic;
Wr : in std_logic;
Rd_Addr : in std_logic_vector(4 downto 0);
Rr_Addr : in std_logic_vector(4 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Rd_Data : out std_logic_vector(7 downto 0);
Rr_Data : out std_logic_vector(7 downto 0);
Add : in std_logic;
Sub : in std_logic;
AS_Offset : in std_logic_vector(5 downto 0);
AS_Reg : in std_logic_vector(1 downto 0);
Dec_X : in std_logic;
Dec_Y : in std_logic;
Dec_Z : in std_logic;
Inc_X : in std_logic;
Inc_Y : in std_logic;
Inc_Z : in std_logic;
X : out unsigned(15 downto 0);
Y : out unsigned(15 downto 0);
Z : out unsigned(15 downto 0);
Status_D : out std_logic_vector(4 downto 0) -- S,V,N,Z,C
);
end AX_Reg;
 
architecture rtl of AX_Reg is
 
signal Rd_Addr_r : std_logic_vector(4 downto 0);
signal Rr_Addr_r : std_logic_vector(4 downto 0);
 
signal Op1 : std_logic_vector(15 downto 0);
signal Op2 : std_logic_vector(15 downto 0);
signal ASR : std_logic_vector(15 downto 0);
signal AS_A : std_logic;
signal AS_S : std_logic;
signal Carry_v : std_logic;
signal Carry15_v : std_logic;
signal W_i : unsigned(15 downto 0);
signal X_i : unsigned(15 downto 0);
signal Y_i : unsigned(15 downto 0);
signal Z_i : unsigned(15 downto 0);
 
signal Reg_D_i : std_logic_vector(7 downto 0);
signal Reg_R_i : std_logic_vector(7 downto 0);
 
begin
 
X <= X_i;
Y <= Y_i;
Z <= Z_i;
 
gBig : if BigISet generate
Op2(15 downto 6) <= "0000000000";
AddSub(Op1(14 downto 0), Op2(14 downto 0), AS_S, AS_S, ASR(14 downto 0), Carry15_v);
AddSub(Op1(15 downto 15), Op2(15 downto 15), AS_S, Carry15_v, ASR(15 downto 15), Carry_v);
Status_D(0) <= Carry_v xor AS_S; -- C
Status_D(1) <= '1' when ASR = "0000000000000000" else '0'; -- Z
Status_D(2) <= ASR(15); -- N
Status_D(3) <= Carry_v xor Carry15_v; -- V
Status_D(4) <= ASR(15) xor Carry_v xor Carry15_v; -- S
end generate;
 
gNoTri : if not TriState and BigISet generate
with Rd_Addr_r select
Rd_Data <= std_logic_vector(W_i(7 downto 0)) when "11000",
std_logic_vector(W_i(15 downto 8)) when "11001",
std_logic_vector(X_i(7 downto 0)) when "11010",
std_logic_vector(X_i(15 downto 8)) when "11011",
std_logic_vector(Y_i(7 downto 0)) when "11100",
std_logic_vector(Y_i(15 downto 8)) when "11101",
std_logic_vector(Z_i(7 downto 0)) when "11110",
std_logic_vector(Z_i(15 downto 8)) when "11111",
Reg_D_i when others;
with Rr_Addr_r select
Rr_Data <= std_logic_vector(W_i(7 downto 0)) when "11000",
std_logic_vector(W_i(15 downto 8)) when "11001",
std_logic_vector(X_i(7 downto 0)) when "11010",
std_logic_vector(X_i(15 downto 8)) when "11011",
std_logic_vector(Y_i(7 downto 0)) when "11100",
std_logic_vector(Y_i(15 downto 8)) when "11101",
std_logic_vector(Z_i(7 downto 0)) when "11110",
std_logic_vector(Z_i(15 downto 8)) when "11111",
Reg_R_i when others;
end generate;
 
gTri : if TriState and BigISet generate
Rd_Data <= std_logic_vector(W_i(7 downto 0)) when Rd_Addr_r = "11000" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(W_i(15 downto 8)) when Rd_Addr_r = "11001" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(X_i(7 downto 0)) when Rd_Addr_r = "11010" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(X_i(15 downto 8)) when Rd_Addr_r = "11011" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Y_i(7 downto 0)) when Rd_Addr_r = "11100" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Y_i(15 downto 8)) when Rd_Addr_r = "11101" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Z_i(7 downto 0)) when Rd_Addr_r = "11110" else "ZZZZZZZZ";
Rd_Data <= std_logic_vector(Z_i(15 downto 8)) when Rd_Addr_r = "11111" else "ZZZZZZZZ";
Rd_Data <= Reg_D_i when (Rd_Addr_r(4 downto 3) /= "11") else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(W_i(7 downto 0)) when Rr_Addr_r = "11000" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(W_i(15 downto 8)) when Rr_Addr_r = "11001" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(X_i(7 downto 0)) when Rr_Addr_r = "11010" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(X_i(15 downto 8)) when Rr_Addr_r = "11011" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Y_i(7 downto 0)) when Rr_Addr_r = "11100" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Y_i(15 downto 8)) when Rr_Addr_r = "11101" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Z_i(7 downto 0)) when Rr_Addr_r = "11110" else "ZZZZZZZZ";
Rr_Data <= std_logic_vector(Z_i(15 downto 8)) when Rr_Addr_r = "11111" else "ZZZZZZZZ";
Rr_Data <= Reg_R_i when (Rr_Addr_r(4 downto 3) /= "11") else "ZZZZZZZZ";
end generate;
 
gSmall : if not BigISet generate
Rd_Data <= Reg_D_i;
Rr_Data <= Reg_R_i;
end generate;
 
dpramd : AX_DPRAM
port map(
Clk => Clk,
Rst_n => Reset_n,
Wr => Wr,
Rd_Addr => Rd_Addr,
Wr_Addr => Rd_Addr_r,
Data_In => Data_In,
Data_Out => Reg_D_i);
 
dpramr : AX_DPRAM
port map(
Clk => Clk,
Rst_n => Reset_n,
Wr => Wr,
Rd_Addr => Rr_Addr,
Wr_Addr => Rd_Addr_r,
Data_In => Data_In,
Data_Out => Reg_R_i);
 
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Rd_Addr_r <= (others => '0');
Rr_Addr_r <= (others => '0');
if BigISet then
W_i <= (others => '0');
X_i <= (others => '0');
Y_i <= (others => '0');
AS_S <= '0';
AS_A <= '0';
Op1 <= (others => '0');
Op2(5 downto 0) <= (others => '0');
end if;
Z_i <= (others => '0');
elsif Clk'event and Clk = '1' then
Rd_Addr_r <= Rd_Addr;
Rr_Addr_r <= Rr_Addr;
if Wr = '1' then
if BigISet then
if Rd_Addr_r = "11000" then
W_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11001" then
W_i(15 downto 8) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11010" then
X_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11011" then
X_i(15 downto 8) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11100" then
Y_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11101" then
Y_i(15 downto 8) <= unsigned(Data_In);
end if;
end if;
if Rd_Addr_r = "11110" then
Z_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11111" then
Z_i(15 downto 8) <= unsigned(Data_In);
end if;
end if;
if BigIset then
AS_A <= Add;
AS_S <= Sub;
case AS_Reg is
when "00" =>
Op1 <= std_logic_vector(W_i);
when "01" =>
Op1 <= std_logic_vector(X_i);
when "10" =>
Op1 <= std_logic_vector(Y_i);
when others =>
Op1 <= std_logic_vector(Z_i);
end case;
Op2(5 downto 0) <= AS_Offset;
if AS_A = '1' or AS_S = '1' then
case AS_Reg is
when "00" =>
W_i <= unsigned(ASR);
when "01" =>
X_i <= unsigned(ASR);
when "10" =>
Y_i <= unsigned(ASR);
when others =>
Z_i <= unsigned(ASR);
end case;
end if;
if Dec_X = '1' then
X_i <= X_i - 1;
end if;
if Dec_Y = '1' then
Y_i <= Y_i - 1;
end if;
if Dec_Z = '1' then
Z_i <= Z_i - 1;
end if;
if Inc_X = '1' then
X_i <= X_i + 1;
end if;
if Inc_Y = '1' then
Y_i <= Y_i + 1;
end if;
if Inc_Z = '1' then
Z_i <= Z_i + 1;
end if;
end if;
end if;
end process;
end;
/ax8/trunk/rtl/vhdl/AX_TC16.vhd
0,0 → 1,354
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- No OC disconnect (separate output pins)
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AX_TC16 is
port(
Clk : in std_logic;
Reset_n : in std_logic;
T : in std_logic;
ICP : in std_logic;
TCCR_Sel : in std_logic;
TCNT_Sel : in std_logic;
OCR_Sel : in std_logic;
ICR_Sel : in std_logic;
A0 : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
COM : out std_logic_vector(1 downto 0);
PWM : out std_logic_vector(1 downto 0);
CRBH : out std_logic_vector(1 downto 0);
CRBL : out std_logic_vector(3 downto 0);
TCNT : out std_logic_vector(15 downto 0);
IC : out std_logic_vector(15 downto 0);
OCR : out std_logic_vector(15 downto 0);
Tmp : out std_logic_vector(15 downto 0);
OC : out std_logic;
Int_TO : out std_logic;
Int_OC : out std_logic;
Int_IC : out std_logic
);
end AX_TC16;
 
architecture rtl of AX_TC16 is
 
signal COM_i : std_logic_vector(1 downto 0);
signal PWM_i : std_logic_vector(1 downto 0);
signal CRBH_i : std_logic_vector(1 downto 0); -- ICNC, ICES
signal CRBL_i : std_logic_vector(3 downto 0); -- CTC, CS
signal TCNT_i : std_logic_vector(15 downto 0);
signal IC_i : std_logic_vector(15 downto 0);
signal OCR_i : std_logic_vector(15 downto 0);
signal Tmp_i : std_logic_vector(15 downto 0);
 
signal OC_i : std_logic;
signal IC_Trig : std_logic;
signal Tick : std_logic;
signal PWM_Dn : std_logic;
signal PWM_Load : std_logic;
 
begin
 
COM <= COM_i;
PWM <= PWM_i;
CRBH <= CRBH_i;
CRBL <= CRBL_i;
TCNT <= TCNT_i;
IC <= IC_i;
OCR(7 downto 0) <= OCR_i(7 downto 0) when PWM_Load = '0' else Tmp_i(7 downto 0);
OCR(15 downto 8) <= OCR_i(15 downto 8);
Tmp <= Tmp_i;
OC <= OC_i;
Int_IC <= IC_Trig;
 
-- Registers and counter
process (Reset_n, Clk)
variable PWM_T : std_logic;
variable PWM_B : std_logic;
begin
if Reset_n = '0' then
COM_i <= "00";
PWM_i <= "00";
CRBH_i <= "00";
CRBL_i <= "0000";
TCNT_i <= (others => '0');
OCR_i <= (others => '0');
IC_i <= (others => '0');
Tmp_i <= (others => '0');
OC_i <= '0';
Int_TO <= '0';
Int_OC <= '0';
PWM_Dn <= '0';
PWM_Load <= '0';
elsif Clk'event and Clk = '1' then
Int_TO <= '0';
Int_OC <= '0';
if Tick = '1' then
TCNT_i <= std_logic_vector(unsigned(TCNT_i) + 1);
if TCNT_i = "1111111111111111" then
Int_TO <= '1';
end if;
if TCNT_i = OCR_i then
if PWM_i = "00" then
Int_OC <= '1';
if CRBL_i(3) = '1' then
TCNT_i <= (others => '0');
end if;
if COM_i = "01" then
OC_i <= not OC_i;
end if;
if COM_i = "10" then
OC_i <= '0';
end if;
if COM_i = "11" then
OC_i <= '1';
end if;
end if;
end if;
if PWM_i /= "00" then
PWM_T := '0';
PWM_B := '0';
if PWM_Dn = '0' then
TCNT_i <= std_logic_vector(unsigned(TCNT_i) + 1);
else
TCNT_i <= std_logic_vector(unsigned(TCNT_i) - 1);
end if;
if PWM_i = "01" and TCNT_i(7 downto 0) = OCR_i(7 downto 0) then
OC_i <= COM_i(0) xor PWM_Dn;
end if;
if PWM_i = "10" and TCNT_i(8 downto 0) = OCR_i(8 downto 0) then
OC_i <= COM_i(0) xor PWM_Dn;
end if;
if PWM_i = "11" and TCNT_i(9 downto 0) = OCR_i(9 downto 0) then
OC_i <= COM_i(0) xor PWM_Dn;
end if;
if PWM_i = "01" then
if TCNT_i(7 downto 0) = "11111110" and PWM_Dn = '0' then
PWM_T := '1';
end if;
if TCNT_i(7 downto 0) = "00000001" and PWM_Dn = '1' then
PWM_B := '1';
end if;
end if;
if PWM_i = "10" then
if TCNT_i(8 downto 0) = "111111110" and PWM_Dn = '0' then
PWM_T := '1';
end if;
if TCNT_i(8 downto 0) = "000000001" and PWM_Dn = '1' then
PWM_B := '1';
end if;
end if;
if PWM_i = "11" then
if TCNT_i(9 downto 0) = "1111111110" and PWM_Dn = '0' then
PWM_T := '1';
end if;
if TCNT_i(9 downto 0) = "0000000001" and PWM_Dn = '1' then
PWM_B := '1';
end if;
end if;
if PWM_T = '1' then
if PWM_Load = '1' and COM_i(0) = '0' then
OCR_i <= Tmp_i;
PWM_Load <= '0';
end if;
PWM_Dn <= '1';
end if;
if PWM_B = '1' then
if PWM_Load = '1' and COM_i(0) = '1' then
OCR_i <= Tmp_i;
PWM_Load <= '0';
end if;
PWM_Dn <= '0';
Int_TO <= '1';
end if;
end if;
end if;
if IC_Trig = '1' then
TCNT_i <= IC_i;
end if;
-- Register read with temp
if Rd = '1' and TCNT_Sel = '1' and A0 = '0' then
Tmp_i(15 downto 8) <= TCNT_i(15 downto 8);
end if;
if Rd = '1' and OCR_Sel = '1' and A0 = '0' then
Tmp_i(15 downto 8) <= OCR_i(15 downto 8);
end if;
if Rd = '1' and ICR_Sel = '1' and A0 = '0' then
Tmp_i(15 downto 8) <= IC_i(15 downto 8);
end if;
-- Register write
if TCNT_Sel = '1' and Wr = '1' then
if A0 = '1' then
Tmp_i(15 downto 8) <= Data_In;
else
TCNT_i(7 downto 0) <= Data_In;
TCNT_i(15 downto 8) <= Tmp_i(15 downto 8);
end if;
Int_TO <= '0';
end if;
if OCR_Sel = '1' and Wr = '1' then
if A0 = '1' then
Tmp_i(15 downto 8) <= Data_In;
else
Tmp_i(7 downto 0) <= Data_In;
if PWM_i = "00" then
OCR_i(7 downto 0) <= Data_In;
OCR_i(15 downto 8) <= Tmp_i(15 downto 8);
else
PWM_Load <= '1';
end if;
end if;
end if;
if ICR_Sel = '1' and Wr = '1' then
if A0 = '1' then
Tmp_i(15 downto 8) <= Data_In;
else
IC_i(7 downto 0) <= Data_In;
IC_i(15 downto 8) <= Tmp_i(15 downto 8);
end if;
end if;
if TCCR_Sel = '1' and Wr = '1' and A0 = '1' then
COM_i <= Data_In(7 downto 6);
PWM_i <= Data_In(1 downto 0);
end if;
if TCCR_Sel = '1' and Wr = '1' and A0 = '0' then
CRBH_i <= Data_In(7 downto 6);
CRBL_i <= Data_In(3 downto 0);
end if;
end if;
end process;
 
-- Input capture filter
process (Clk)
variable Samples : std_logic_vector(4 downto 0);
begin
if Clk'event and Clk = '1' then
IC_Trig <= '0';
if CRBH_i(1) = '1' then
if Samples = "10000" and CRBH_i(0) = '0' then
IC_Trig <= '1';
end if;
if Samples = "01111" and CRBH_i(0) = '1' then
IC_Trig <= '1';
end if;
else
if Samples(1 downto 0) = "10" and CRBH_i(0) = '0' then
IC_Trig <= '1';
end if;
if Samples(1 downto 0) = "01" and CRBH_i(0) = '1' then
IC_Trig <= '1';
end if;
end if;
Samples(3 downto 1) := Samples(2 downto 0);
Samples(0) := ICP;
end if;
end process;
 
-- Tick generator
process (Clk, Reset_n)
variable Prescaler : unsigned(9 downto 0);
variable T_r : std_logic_vector(1 downto 0);
begin
if Reset_n = '0' then
Prescaler := (others => '0');
Tick <= '0';
T_r := "00";
elsif Clk'event and Clk='1' then
Tick <= '0';
case CRBL_i(2 downto 0) is
when "000" =>
when "001" =>
Tick <= '1';
when "010" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(2);
when "011" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(5);
when "100" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(7);
when "101" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(9);
when "110" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := T;
when others =>
if T_r(1) = '0' and T_r(0) = '1' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := T;
end case;
Prescaler := Prescaler + 1;
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/AX_Pack.vhd
0,0 → 1,298
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221b
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
package AX_Pack is
 
component AX_ALU
port(
Clk : in std_logic;
ROM_Data : in std_logic_vector(15 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
SREG : in std_logic_vector(7 downto 0);
PassB : in std_logic;
Skip : in std_logic;
Do_Other : out std_logic;
Z_Skip : out std_logic;
Status_D : out std_logic_vector(6 downto 0);
Status_Wr : out std_logic_vector(6 downto 0) -- T,H,S,V,N,Z,C
);
end component;
 
component AX_PCS
generic(
HW_Stack : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
Offs_In : in std_logic_vector(11 downto 0);
Z : in unsigned(15 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Pause : in std_logic;
Push : in std_logic;
Pop : in std_logic;
HRet : in std_logic;
LRet : in std_logic;
ZJmp : in std_logic;
RJmp : in std_logic;
CInt : in std_logic_vector(3 downto 0);
IPending : in std_logic;
IPush : out std_logic;
NPC : out std_logic_vector(15 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end component;
 
component AX_DPRAM
port(
Clk : in std_logic;
Rst_n : in std_logic;
Wr : in std_logic;
Rd_Addr : in std_logic_vector(4 downto 0);
Wr_Addr : in std_logic_vector(4 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
);
end component;
 
component AX_Reg
generic(
BigISet : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
Wr : in std_logic;
Rd_Addr : in std_logic_vector(4 downto 0);
Rr_Addr : in std_logic_vector(4 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Rd_Data : out std_logic_vector(7 downto 0);
Rr_Data : out std_logic_vector(7 downto 0);
Add : in std_logic;
Sub : in std_logic;
AS_Offset : in std_logic_vector(5 downto 0);
AS_Reg : in std_logic_vector(1 downto 0);
Dec_X : in std_logic;
Dec_Y : in std_logic;
Dec_Z : in std_logic;
Inc_X : in std_logic;
Inc_Y : in std_logic;
Inc_Z : in std_logic;
X : out unsigned(15 downto 0);
Y : out unsigned(15 downto 0);
Z : out unsigned(15 downto 0);
Status_D : out std_logic_vector(4 downto 0) -- S,V,N,Z,C
);
end component;
 
component AX_RAM
generic(
RAMAddressWidth : integer
);
port(
Clk : in std_logic;
Rd_Addr : in std_logic_vector(RAMAddressWidth downto 0);
Wr_Addr : in std_logic_vector(RAMAddressWidth downto 0);
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
);
end component;
 
component AX8
generic(
ROMAddressWidth : integer;
RAMAddressWidth : integer;
BigISet : boolean
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
ROM_Data : in std_logic_vector(15 downto 0);
Sleep_En : in std_logic;
Int_Trig : in std_logic_vector(15 downto 1);
Int_Acc : out std_logic_vector(15 downto 1);
SREG : out std_logic_vector(7 downto 0);
SP : out std_logic_vector(15 downto 0);
IO_Rd : out std_logic;
IO_Wr : out std_logic;
IO_Addr : out std_logic_vector(5 downto 0);
IO_RData : in std_logic_vector(7 downto 0);
IO_WData : out std_logic_vector(7 downto 0);
WDR : out std_logic
);
end component;
 
component AX_Port
port(
Clk : in std_logic;
Reset_n : in std_logic;
PORT_Sel : in std_logic;
DDR_Sel : in std_logic;
PIN_Sel : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Dir : out std_logic_vector(7 downto 0);
Port_Input : out std_logic_vector(7 downto 0);
Port_Output : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end component;
 
component AX_UART
port(
Clk : in std_logic;
Reset_n : in std_logic;
UDR_Sel : in std_logic;
USR_Sel : in std_logic;
UCR_Sel : in std_logic;
UBRR_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
TXC_Clr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
UDR : out std_logic_vector(7 downto 0);
USR : out std_logic_vector(7 downto 3);
UCR : out std_logic_vector(7 downto 0);
UBRR : out std_logic_vector(7 downto 0);
RXD : in std_logic;
TXD : out std_logic;
Int_RX : out std_logic;
Int_TR : out std_logic;
Int_TC : out std_logic
);
end component;
 
component AX_TC8
port(
Clk : in std_logic;
Reset_n : in std_logic;
T : in std_logic;
TCCR_Sel : in std_logic;
TCNT_Sel : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
TCCR : out std_logic_vector(2 downto 0);
TCNT : out std_logic_vector(7 downto 0);
Int : out std_logic
);
end component;
 
component AX_TC16
port(
Clk : in std_logic;
Reset_n : in std_logic;
T : in std_logic;
ICP : in std_logic;
TCCR_Sel : in std_logic;
TCNT_Sel : in std_logic;
OCR_Sel : in std_logic;
ICR_Sel : in std_logic;
A0 : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
COM : out std_logic_vector(1 downto 0);
PWM : out std_logic_vector(1 downto 0);
CRBH : out std_logic_vector(1 downto 0);
CRBL : out std_logic_vector(3 downto 0);
TCNT : out std_logic_vector(15 downto 0);
IC : out std_logic_vector(15 downto 0);
OCR : out std_logic_vector(15 downto 0);
Tmp : out std_logic_vector(15 downto 0);
OC : out std_logic;
Int_TO : out std_logic;
Int_OC : out std_logic;
Int_IC : out std_logic
);
end component;
 
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic);
 
end AX_Pack;
 
package body AX_Pack is
 
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length downto 0);
variable Full_Carry : unsigned(A'length downto 0);
variable Res_i : unsigned(A'length downto 0);
begin
if Sub = '1' then
B_i := "0" & unsigned(not B);
else
B_i := "0" & unsigned(B);
end if;
if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
Full_Carry := (others => '0');
Full_Carry(0) := '1';
else
Full_Carry := (others => '0');
end if;
Res_i := unsigned("0" & A) + B_i + Full_Carry;
Carry <= Res_i(A'length);
Res <= std_logic_vector(Res_i(A'length - 1 downto 0));
end;
 
end;
/ax8/trunk/rtl/vhdl/AX_TC8.vhd
0,0 → 1,162
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AX_TC8 is
port(
Clk : in std_logic;
Reset_n : in std_logic;
T : in std_logic;
TCCR_Sel : in std_logic;
TCNT_Sel : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
TCCR : out std_logic_vector(2 downto 0);
TCNT : out std_logic_vector(7 downto 0);
Int : out std_logic
);
end AX_TC8;
 
architecture rtl of AX_TC8 is
 
signal TCCR_i : std_logic_vector(2 downto 0); -- Control Register
signal TCNT_i : std_logic_vector(7 downto 0); -- Timer/Counter
 
signal Tick : std_logic;
 
begin
 
TCCR <= TCCR_i;
TCNT <= TCNT_i;
 
-- Registers and counter
process (Reset_n, Clk)
begin
if Reset_n = '0' then
TCCR_i<= "000";
TCNT_i <= "00000000";
Int <= '0';
elsif Clk'event and Clk = '1' then
if TCCR_Sel = '1' and Wr = '1' then
TCCR_i <= Data_In(2 downto 0);
end if;
Int <= '0';
if Tick = '1' then
TCNT_i <= std_logic_vector(unsigned(TCNT_i) + 1);
if TCNT_i = "11111111" then
Int <= '1';
end if;
end if;
if TCNT_Sel = '1' and Wr = '1' then
TCNT_i <= Data_In;
Int <= '0';
end if;
end if;
end process;
 
-- Tick generator
process (Clk, Reset_n)
variable Prescaler : unsigned(9 downto 0);
variable T_r : std_logic_vector(1 downto 0);
begin
if Reset_n = '0' then
Prescaler := (others => '0');
Tick <= '0';
T_r := "00";
elsif Clk'event and Clk='1' then
Tick <= '0';
case TCCR_i is
when "000" =>
when "001" =>
Tick <= '1';
when "010" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(2);
when "011" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(5);
when "100" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(7);
when "101" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := Prescaler(9);
when "110" =>
if T_r(1) = '1' and T_r(0) = '0' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := T;
when others =>
if T_r(1) = '0' and T_r(0) = '1' then
Tick <= '1';
end if;
T_r(1) := T_r(0);
T_r(0) := T;
end case;
Prescaler := Prescaler + 1;
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/AX_Port.vhd
0,0 → 1,111
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
-- No pull-up
--
-- File history :
--
-- 0146 : First release
-- 0221 : Removed tristate
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity AX_Port is
port(
Clk : in std_logic;
Reset_n : in std_logic;
PORT_Sel : in std_logic;
DDR_Sel : in std_logic;
PIN_Sel : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Dir : out std_logic_vector(7 downto 0);
Port_Input : out std_logic_vector(7 downto 0);
Port_Output : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end AX_Port;
 
architecture rtl of AX_Port is
 
signal Dir_i : std_logic_vector(7 downto 0);
signal Port_Output_i : std_logic_vector(7 downto 0);
 
begin
 
Dir <= Dir_i;
Port_Output <= Port_Output_i;
 
IOPort(0) <= Port_Output_i(0) when Dir_i(0) = '1' else 'Z';
IOPort(1) <= Port_Output_i(1) when Dir_i(1) = '1' else 'Z';
IOPort(2) <= Port_Output_i(2) when Dir_i(2) = '1' else 'Z';
IOPort(3) <= Port_Output_i(3) when Dir_i(3) = '1' else 'Z';
IOPort(4) <= Port_Output_i(4) when Dir_i(4) = '1' else 'Z';
IOPort(5) <= Port_Output_i(5) when Dir_i(5) = '1' else 'Z';
IOPort(6) <= Port_Output_i(6) when Dir_i(6) = '1' else 'Z';
IOPort(7) <= Port_Output_i(7) when Dir_i(7) = '1' else 'Z';
 
process (Clk)
begin
if Clk'event and Clk = '1' then
Port_Input <= IOPort;
end if;
end process;
 
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Dir_i <= "00000000";
Port_Output_i <= "00000000";
elsif Clk'event and Clk = '1' then
if DDR_Sel = '1' and Wr = '1' then
Dir_i <= Data_In;
end if;
if PORT_Sel = '1' and Wr = '1' then
Port_Output_i <= Data_In;
end if;
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/AX_ALU.vhd
0,0 → 1,333
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.AX_Pack.all;
 
entity AX_ALU is
generic(
TriState : boolean := false
);
port(
Clk : in std_logic;
ROM_Data : in std_logic_vector(15 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
SREG : in std_logic_vector(7 downto 0);
PassB : in std_logic;
Skip : in std_logic;
Do_Other : out std_logic;
Z_Skip : out std_logic;
Status_D : out std_logic_vector(6 downto 0);
Status_Wr : out std_logic_vector(6 downto 0) -- T,H,S,V,N,Z,C
);
end AX_ALU;
 
architecture rtl of AX_ALU is
 
signal Do_NEG : std_logic;
signal Do_ADD : std_logic;
signal Do_SUB : std_logic;
signal Do_DEC : std_logic;
signal Do_INC : std_logic;
signal Do_AND : std_logic;
signal Do_OR : std_logic;
signal Do_XOR : std_logic;
signal Do_COM : std_logic;
signal Do_SWAP : std_logic;
signal Do_BLD : std_logic;
signal Do_BST : std_logic;
signal Do_ROR : std_logic;
signal Do_ASR : std_logic;
signal Do_LSR : std_logic;
signal Do_PASSB : std_logic;
signal Do_SBRC : std_logic;
signal Do_SBRS : std_logic;
signal Use_Carry : std_logic;
 
signal Bit_Pattern : std_logic_vector(7 downto 0);
signal Bit_Test : std_logic_vector(7 downto 0);
 
signal Q_i : std_logic_vector(7 downto 0);
signal Q_L : std_logic_vector(7 downto 0);
signal Q_C : std_logic_vector(7 downto 0);
signal Q_S : std_logic_vector(7 downto 0);
signal Q_R : std_logic_vector(7 downto 0);
signal Q_B : std_logic_vector(7 downto 0);
 
-- AddSub intermediate signals
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal Overflow_t : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal AAS : std_logic_vector(7 downto 0);
signal BAS : std_logic_vector(7 downto 0);
 
begin
 
Q <= Q_i;
 
Do_Other <= Do_PASSB;
 
gNoTri : if not TriState generate
Q_i <= Q_v when Do_ADD = '1' or Do_SUB = '1' else
Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
Q_C when Do_COM = '1' else
Q_S when Do_SWAP = '1' else
Q_R when Do_ASR = '1' or Do_LSR = '1' or Do_ROR = '1' else
Q_B;
end generate;
 
gTri : if TriState generate
Q_i <= Q_v when Do_ADD = '1' or Do_SUB = '1' else "ZZZZZZZZ";
Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
Q_i <= Q_R when Do_ASR = '1' or Do_LSR = '1' or Do_ROR = '1' else "ZZZZZZZZ";
Q_i <= Q_B when Do_BLD = '1' else "ZZZZZZZZ";
end generate;
 
process (Clk)
begin
if Clk'event and Clk = '1' then
Do_SUB <= '0';
Do_ADD <= '0';
Use_Carry <= '0';
Do_AND <= '0';
Do_XOR <= '0';
Do_OR <= '0';
Do_SWAP <= '0';
Do_ASR <= '0';
Do_LSR <= '0';
Do_ROR <= '0';
Do_INC <= '0';
Do_DEC <= '0';
Do_COM <= '0';
Do_NEG <= '0';
Do_BLD <= '0';
Do_BST <= '0';
Do_PASSB <= '0';
Do_SBRC <= '0';
Do_SBRS <= '0';
if PassB = '0' then
if Skip = '0' then
if ROM_Data(15 downto 10) = "000101" or ROM_Data(15 downto 12) = "0011" or
ROM_Data(15 downto 10) = "000110" or ROM_Data(15 downto 12) = "0101" or
ROM_Data(15 downto 12) = "0100" or ROM_Data(15 downto 10) = "000001" or
ROM_Data(15 downto 10) = "000010" or
(ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0001") or
(ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "1010") then
-- CP, CPI, SUB, SUBI, SBCI, CPC, SBC, NEG, DEC
Do_SUB <= '1';
end if;
if ROM_Data(15 downto 10) = "000011" or ROM_Data(15 downto 10) = "000111" or
(ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0011") then
-- ADD, ADC, INC
Do_ADD <= '1';
end if;
if ROM_Data(15 downto 12) = "0100" or ROM_Data(15 downto 10) = "000001" or
ROM_Data(15 downto 10) = "000010" or ROM_Data(15 downto 10) = "000111" then
-- SBCI, CPC, SBC, ADC
Use_Carry <= '1';
end if;
if ROM_Data(15 downto 10) = "001000" or ROM_Data(15 downto 12) = "0111" then
-- AND, ANDI
Do_AND <= '1';
end if;
if ROM_Data(15 downto 10) = "001001" then
-- EOR
Do_XOR <= '1';
end if;
if ROM_Data(15 downto 10) = "001010" or ROM_Data(15 downto 12) = "0110" then
-- OR, ORI
Do_OR <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0010" then
-- SWAP
Do_SWAP <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0101" then
-- ASR
Do_ASR <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0110" then
-- LSR
Do_LSR <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0111" then
-- ROR
Do_ROR <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0011" then
-- INC
Do_INC <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "1010" then
-- DEC
Do_DEC <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0000" then
-- COM
Do_COM <= '1';
end if;
if ROM_Data(15 downto 9) = "1001010" and ROM_Data(3 downto 0) = "0001" then
-- NEG
Do_NEG <= '1';
end if;
if ROM_Data(15 downto 9) = "1111100" then
-- BLD
Do_BLD <= '1';
end if;
if ROM_Data(15 downto 9) = "1111101" then
-- BST
Do_BST <= '1';
end if;
if ROM_Data(15 downto 10) = "001011" or
ROM_Data(15 downto 12) = "1011" or
ROM_Data(15 downto 12) = "1110" then
-- MOV, DidPause, IN, OUT, LDI
Do_PASSB <= '1';
end if;
if ROM_Data(15 downto 9) = "1111110" then
-- SBRC
Do_SBRC <= '1';
else
Do_SBRC <= '0';
end if;
if ROM_Data(15 downto 9) = "1111111" then
-- SBRS
Do_SBRS <= '1';
else
Do_SBRS <= '0';
end if;
end if;
else
Do_PASSB <= '1';
end if;
 
case ROM_Data(2 downto 0) is
when "000" =>
Bit_Pattern <= "00000001";
when "001" =>
Bit_Pattern <= "00000010";
when "010" =>
Bit_Pattern <= "00000100";
when "011" =>
Bit_Pattern <= "00001000";
when "100" =>
Bit_Pattern <= "00010000";
when "101" =>
Bit_Pattern <= "00100000";
when "110" =>
Bit_Pattern <= "01000000";
when others =>
Bit_Pattern <= "10000000";
end case;
end if;
end process;
 
Bit_Test <= Bit_Pattern and A;
 
Z_Skip <= '1' when ((Bit_Test /= "00000000") and (Do_SBRS = '1')) or
((Bit_Test = "00000000") and (Do_SBRC = '1')) else '0';
 
AAS <= "00000000" when Do_NEG = '1' else A;
BAS <= A when Do_NEG = '1' else "00000001" when Do_DEC = '1' or Do_INC = '1' else B;
AddSub(AAS(3 downto 0), BAS(3 downto 0), Do_SUB, Do_SUB xor (Use_Carry and SREG(0)), Q_v(3 downto 0), HalfCarry_v);
AddSub(AAS(6 downto 4), BAS(6 downto 4), Do_SUB, HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(AAS(7 downto 7), BAS(7 downto 7), Do_SUB, Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
Status_D(5) <= HalfCarry_v xor Do_SUB; -- H
 
Q_L <= (A and B) when Do_AND = '1' else
(A or B) when Do_OR = '1' else
(A xor B);
 
Q_C <= (not A);
 
Q_S <= A(3 downto 0) & A(7 downto 4);
 
Q_R(6 downto 0) <= A(7 downto 1);
Q_R(7) <= (A(7) and Do_ASR) or (SREG(0) and Do_ROR);
 
Q_B <= ((not Bit_Pattern) and A) when SREG(6) = '0' else
(Bit_Pattern or A);
 
Status_D(6) <= '1' when (Bit_Pattern and A) /= "00000000" else '0';
 
Overflow_t <= Overflow_v when Do_SUB = '1' or Do_ADD = '1' else
Q_i(7) xor A(0) when (Do_ASR or Do_LSR or Do_ROR) = '1' else '0'; -- V
Status_D(3) <= Overflow_t;
Status_D(2) <= Q_i(7); -- N
Status_D(4) <= Overflow_t xor Q_i(7); -- SREG(3) xor SREG(2); -- S
Status_D(1) <= '1' when Q_i(7 downto 0) = "00000000" and (Do_SUB = '0' or Use_Carry = '0') else
SREG(1) when Q_i(7 downto 0) = "00000000" and Do_SUB = '1' and Use_Carry = '1' else '0'; -- Z
Status_D(0) <= ((Carry_v xor Do_SUB) and (Do_ADD or Do_SUB)) or
(A(0) and (Do_ASR or Do_LSR or Do_ROR)) or Do_COM;
 
process (Do_SUB, Do_ADD, Do_COM, Do_ASR, Do_LSR, Do_ROR, Do_AND, Do_XOR, Do_OR, Do_INC, Do_DEC, Do_BST)
begin
Status_Wr <= "0000000";
if (Do_COM or Do_ASR or Do_LSR or Do_ROR) = '1' then
Status_Wr <= "0011111"; -- Z,C,N,V ,S
end if;
if (Do_AND or Do_XOR or Do_OR or Do_INC or Do_DEC) = '1' then
Status_Wr <= "0011110"; -- Z,N,V ,S
elsif (Do_SUB or Do_ADD) = '1' then
Status_Wr <= "0111111"; -- Z,C,N,V,H ,S
end if;
if Do_BST = '1' then
Status_Wr <= "1000000"; -- T
end if;
end process;
 
end;
/ax8/trunk/rtl/vhdl/AX_DPRAM.vhd
0,0 → 1,96
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AX_DPRAM is
port(
Clk : in std_logic;
Rst_n : in std_logic;
Wr : in std_logic;
Rd_Addr : in std_logic_vector(4 downto 0);
Wr_Addr : in std_logic_vector(4 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
);
end AX_DPRAM;
 
architecture rtl of AX_DPRAM is
 
type Reg_Image is array (31 downto 0) of std_logic_vector(7 downto 0);
signal Reg : Reg_Image;
signal Rd_Addr_r : std_logic_vector(4 downto 0);
 
begin
 
process (Rst_n, Clk)
begin
-- pragma translate_off
if Rst_n = '0' then
Reg <= (others => "00000000");
else
-- pragma translate_on
if Clk'event and Clk = '1' then
if Wr = '1' then
Reg(to_integer(unsigned(Wr_Addr))) <= Data_In;
end if;
Rd_Addr_r <= Rd_Addr;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
end process;
 
Data_Out <= Reg(to_integer(unsigned(Rd_Addr_r)))
-- pragma translate_off
when not is_x(Rd_Addr_r) else "--------"
-- pragma translate_on
;
 
end;
/ax8/trunk/rtl/vhdl/AX_RAM.vhd
0,0 → 1,95
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0220
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0146 : First release
-- 0220 : Added support for XST
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AX_RAM is
generic(
RAMAddressWidth : integer := 8
);
port (
Clk : in std_logic;
Rd_Addr : in std_logic_vector(RAMAddressWidth downto 0);
Wr_Addr : in std_logic_vector(RAMAddressWidth downto 0);
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
);
end AX_RAM;
 
architecture rtl of AX_RAM is
 
type RAM_Image is array (2**RAMAddressWidth + 95 downto 0) of std_logic_vector(7 downto 0);
signal DRAM : RAM_Image;
signal Wr_Addr_r : std_logic_vector(RAMAddressWidth downto 0);
signal Rd_Addr_r : std_logic_vector(RAMAddressWidth downto 0);
signal Data_Out_i : std_logic_vector(7 downto 0);
 
begin
 
process (Clk)
begin
if Clk'event and Clk = '1' then
if Wr = '1' then
DRAM(to_integer(unsigned(Wr_Addr_r))) <= Data_In;
end if;
Wr_Addr_r <= Wr_Addr;
Rd_Addr_r <= Rd_Addr;
end if;
end process;
 
Data_Out <= DRAM(to_integer(unsigned(Rd_Addr_r)))
-- pragma translate_off
when not is_x(Rd_Addr_r) else "--------"
-- pragma translate_on
;
 
end;
/ax8/trunk/rtl/vhdl/AX_Reg2.vhd
0,0 → 1,279
--
-- AT90Sxxxx compatible microcontroller core
--
-- Version : 0146
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.AX_Pack.all;
 
entity AX_Reg is
generic(
BigISet : boolean
);
port (
Clk : in std_logic;
Reset_n : in std_logic;
Wr : in std_logic;
Rd_Addr : in std_logic_vector(4 downto 0);
Rr_Addr : in std_logic_vector(4 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Rd_Data : out std_logic_vector(7 downto 0);
Rr_Data : out std_logic_vector(7 downto 0);
Add : in std_logic;
Sub : in std_logic;
AS_Offset : in std_logic_vector(5 downto 0);
AS_Reg : in std_logic_vector(1 downto 0);
Dec_X : in std_logic;
Dec_Y : in std_logic;
Dec_Z : in std_logic;
Inc_X : in std_logic;
Inc_Y : in std_logic;
Inc_Z : in std_logic;
X : out unsigned(15 downto 0);
Y : out unsigned(15 downto 0);
Z : out unsigned(15 downto 0);
Status_D : out std_logic_vector(4 downto 0) -- S,V,N,Z,C
);
end AX_Reg;
 
architecture rtl of AX_Reg is
 
type Reg_Image is array (31 downto 0) of std_logic_vector(7 downto 0);
signal RegD : Reg_Image;
signal RegR : Reg_Image;
signal Rd_Addr_r : std_logic_vector(4 downto 0);
 
signal Op1 : std_logic_vector(15 downto 0);
signal Op2 : std_logic_vector(15 downto 0);
signal ASR : std_logic_vector(15 downto 0);
signal AS_A : std_logic;
signal AS_S : std_logic;
signal Carry_v : std_logic;
signal Carry15_v : std_logic;
signal W_i : unsigned(15 downto 0);
signal X_i : unsigned(15 downto 0);
signal Y_i : unsigned(15 downto 0);
signal Z_i : unsigned(15 downto 0);
 
begin
 
X <= X_i;
Y <= Y_i;
Z <= Z_i;
 
g1 : if BigISet generate
Op2(15 downto 6) <= "0000000000";
AddSub(Op1(14 downto 0), Op2(14 downto 0), AS_S, AS_S, ASR(14 downto 0), Carry15_v);
AddSub(Op1(15 downto 15), Op2(15 downto 15), AS_S, Carry15_v, ASR(15 downto 15), Carry_v);
Status_D(0) <= Carry_v xor AS_S; -- C
Status_D(1) <= '1' when ASR = "0000000000000000" else '0'; -- Z
Status_D(2) <= ASR(15); -- N
Status_D(3) <= Carry_v xor Carry15_v; -- V
Status_D(4) <= ASR(15) xor Carry_v xor Carry15_v; -- S
end generate;
 
process (Reset_n, Clk)
begin
-- pragma translate_off
if Reset_n = '0' then
RegD <= (others => "00000000");
RegR <= (others => "00000000");
if BigISet then
W_i <= (others => '0');
X_i <= (others => '0');
Y_i <= (others => '0');
AS_A <= '0';
AS_S <= '0';
Op2(5 downto 0) <= (others => '0');
end if;
Z_i <= (others => '0');
Rd_Data <= (others => '0');
Rr_Data <= (others => '0');
Rd_Addr_r <= (others => '0');
else
-- pragma translate_on
if Clk'event and Clk = '1' then
Rd_Addr_r <= Rd_Addr;
-- pragma translate_off
if not is_x(Rd_Addr) then
-- pragma translate_on
Rd_Data <= RegD(to_integer(unsigned(Rd_Addr)));
-- pragma translate_off
end if;
if not is_x(Rr_Addr) then
-- pragma translate_on
Rr_Data <= RegR(to_integer(unsigned(Rr_Addr)));
-- pragma translate_off
end if;
-- pragma translate_on
if Rd_Addr(4 downto 3) = "11" and (BigISet or Rd_Addr(2 downto 1) = "11") then
case Rd_Addr(2 downto 0) is
when "000" =>
Rd_Data <= std_logic_vector(W_i(7 downto 0));
when "001" =>
Rd_Data <= std_logic_vector(W_i(15 downto 8));
when "010" =>
Rd_Data <= std_logic_vector(X_i(7 downto 0));
when "011" =>
Rd_Data <= std_logic_vector(X_i(15 downto 8));
when "100" =>
Rd_Data <= std_logic_vector(Y_i(7 downto 0));
when "101" =>
Rd_Data <= std_logic_vector(Y_i(15 downto 8));
when "110" =>
Rd_Data <= std_logic_vector(Z_i(7 downto 0));
when others =>
Rd_Data <= std_logic_vector(Z_i(15 downto 8));
end case;
end if;
if Rr_Addr(4 downto 3) = "11" and (BigISet or Rr_Addr(2 downto 1) = "11") then
case Rr_Addr(2 downto 0) is
when "000" =>
Rr_Data <= std_logic_vector(W_i(7 downto 0));
when "001" =>
Rr_Data <= std_logic_vector(W_i(15 downto 8));
when "010" =>
Rr_Data <= std_logic_vector(X_i(7 downto 0));
when "011" =>
Rr_Data <= std_logic_vector(X_i(15 downto 8));
when "100" =>
Rr_Data <= std_logic_vector(Y_i(7 downto 0));
when "101" =>
Rr_Data <= std_logic_vector(Y_i(15 downto 8));
when "110" =>
Rr_Data <= std_logic_vector(Z_i(7 downto 0));
when others =>
Rr_Data <= std_logic_vector(Z_i(15 downto 8));
end case;
end if;
if Wr = '1' then
RegD(to_integer(unsigned(Rd_Addr_r))) <= Data_In;
RegR(to_integer(unsigned(Rd_Addr_r))) <= Data_In;
if Rd_Addr_r = Rd_Addr then
Rd_Data <= Data_In;
end if;
if Rd_Addr_r = Rr_Addr then
Rr_Data <= Data_In;
end if;
if BigISet then
if Rd_Addr_r = "11000" then
W_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11001" then
W_i(15 downto 8) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11010" then
X_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11011" then
X_i(15 downto 8) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11100" then
Y_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11101" then
Y_i(15 downto 8) <= unsigned(Data_In);
end if;
end if;
if Rd_Addr_r = "11110" then
Z_i(7 downto 0) <= unsigned(Data_In);
end if;
if Rd_Addr_r = "11111" then
Z_i(15 downto 8) <= unsigned(Data_In);
end if;
end if;
if BigIset then
AS_A <= Add;
AS_S <= Sub;
case AS_Reg is
when "00" =>
Op1 <= std_logic_vector(W_i);
when "01" =>
Op1 <= std_logic_vector(X_i);
when "10" =>
Op1 <= std_logic_vector(Y_i);
when others =>
Op1 <= std_logic_vector(Z_i);
end case;
Op2(5 downto 0) <= AS_Offset;
if AS_A = '1' or AS_S = '1' then
case AS_Reg is
when "00" =>
W_i <= unsigned(ASR);
when "01" =>
X_i <= unsigned(ASR);
when "10" =>
Y_i <= unsigned(ASR);
when others =>
Z_i <= unsigned(ASR);
end case;
end if;
if Dec_X = '1' then
X_i <= X_i - 1;
end if;
if Dec_Y = '1' then
Y_i <= Y_i - 1;
end if;
if Dec_Z = '1' then
Z_i <= Z_i - 1;
end if;
if Inc_X = '1' then
X_i <= X_i + 1;
end if;
if Inc_Y = '1' then
Y_i <= Y_i + 1;
end if;
if Inc_Z = '1' then
Z_i <= Z_i + 1;
end if;
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
end process;
end;
/ax8/trunk/syn/xilinx/run/a90s1200_leo.bat
0,0 → 1,10
cd ..\out
 
hex2rom ..\..\..\sw\echo1200.hex ROM1200 9l16s > ..\src\ROM1200_Echo_leo.vhd
 
spectrum -file ..\bin\a90s1200.tcl
move exemplar.log ..\log\a90s1200_leo.srp
 
cd ..\run
 
a90s1200 a90s1200_leo.edf xc2s200-pq208-5
/ax8/trunk/syn/xilinx/run/a90s1200.bat
0,0 → 1,46
set name=a90s1200
rem set target=xc2v250-cs144-6
rem set target=xcv300e-pq240-8
set target=xc2s200-pq208-5
 
if "%2" == "" goto default
set target=%2
:default
 
cd ..\out
 
if "%1" == "" goto xst
 
set name=a90s1200_leo
 
copy ..\bin\a90s1200.pin %name%.ucf
 
ngdbuild -p %target% %1 %name%.ngd
 
goto builddone
 
:xst
 
xrom ROM1200 9 16 > ..\src\ROM1200_Echo.vhd
hex2rom ..\..\..\sw\echo1200.hex rom1200 9l16u > rom1200_echo.ini
copy ..\out\rom1200_echo.ini + ..\bin\%name%.pin %name%.ucf
 
xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp
ngdbuild -p %target% %name%.ngc
 
:builddone
 
move %name%.bld ..\log
 
map -p %target% -cm speed -c 100 -tx on -o %name%_map %name%
move %name%_map.mrp ..\log\%name%.mrp
 
par -ol 3 -t 1 -c 0 %name%_map -w %name%
move %name%.par ..\log
 
trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf
 
bitgen -w %name%
move %name%.bgn ..\log
 
cd ..\run
/ax8/trunk/syn/xilinx/run/a90s2313_leo.bat
0,0 → 1,10
cd ..\out
 
hex2rom ..\..\..\sw\sine2313.hex ROM2313 10l16s > ..\src\ROM2313_Sine_leo.vhd
 
spectrum -file ..\bin\a90s2313.tcl
move exemplar.log ..\log\a90s2313_leo.srp
 
cd ..\run
 
a90s2313 a90s2313_leo.edf xc2s200-pq208-5
/ax8/trunk/syn/xilinx/run/a90s2313.bat
0,0 → 1,46
set name=a90s2313
rem set target=xc2v250-cs144-6
rem set target=xcv300e-pq240-8
set target=xc2s200-pq208-5
 
if "%2" == "" goto default
set target=%2
:default
 
cd ..\out
 
if "%1" == "" goto xst
 
set name=a90s2313_leo
 
copy ..\bin\a90s2313.pin %name%.ucf
 
ngdbuild -p %target% %1 %name%.ngd
 
goto builddone
 
:xst
 
xrom ROM2313 10 16 > ..\src\ROM2313_Sine.vhd
hex2rom ..\..\..\sw\sine2313.hex rom2313 10l16u > rom2313_sine.ini
copy ..\out\rom2313_sine.ini + ..\bin\%name%.pin %name%.ucf
 
xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp
ngdbuild -p %target% %name%.ngc
 
:builddone
 
move %name%.bld ..\log
 
map -p %target% -cm speed -c 100 -pr b -timing -tx on -o %name%_map %name%
move %name%_map.mrp ..\log\%name%.mrp
 
par -ol 3 -t 1 -c 0 %name%_map -w %name%
move %name%.par ..\log
 
trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf
 
bitgen -w %name%
move %name%.bgn ..\log
 
cd ..\run
/ax8/trunk/syn/xilinx/bin/a90s2313.prj
0,0 → 1,13
../../../rtl/vhdl/AX_Pack.vhd
../../../rtl/vhdl/AX_DPRAM.vhd
../../../rtl/vhdl/AX_Reg.vhd
../../../rtl/vhdl/AX_ALU.vhd
../../../rtl/vhdl/AX_RAM.vhd
../../../rtl/vhdl/AX_PCS.vhd
../../../rtl/vhdl/AX8.vhd
../../../rtl/vhdl/AX_Port.vhd
../../../rtl/vhdl/AX_TC8.vhd
../../../rtl/vhdl/AX_TC16.vhd
../../../rtl/vhdl/AX_UART.vhd
../src/ROM2313_Sine.vhd
../../../rtl/vhdl/A90S2313.vhd
/ax8/trunk/syn/xilinx/bin/a90s1200.tcl
0,0 → 1,44
set process "5"
set part "2s200pq208"
set tristate_map "FALSE"
set opt_auto_mode "TRUE"
set opt_best_result "29223.458000"
set dont_lock_lcells "auto"
set input2output "20.000000"
set input2register "20.000000"
set register2output "20.000000"
set register2register "20.000000"
set wire_table "xis215-5_avg"
set encoding "auto"
set edifin_ground_port_names "GND"
set edifin_power_port_names "VCC"
set edif_array_range_extraction_style "%s\[%d:%d\]"
 
set_xilinx_eqn
 
load_library xis2
 
read -technology xis2 {
../../../rtl/vhdl/AX_Pack.vhd
../../../rtl/vhdl/AX_DPRAM.vhd
../../../rtl/vhdl/AX_Reg.vhd
../../../rtl/vhdl/AX_ALU.vhd
../../../rtl/vhdl/AX_PCS.vhd
../../../rtl/vhdl/AX8.vhd
../../../rtl/vhdl/AX_Port.vhd
../../../rtl/vhdl/AX_TC8.vhd
../src/ROM1200_Echo_leo.vhd
../../../rtl/vhdl/A90S1200.vhd
}
 
pre_optimize
 
optimize -hierarchy=auto
 
optimize_timing
 
report_area
 
report_delay
 
write a90s1200_leo.edf
/ax8/trunk/syn/xilinx/bin/a90s1200.pin
0,0 → 1,14
#NET "clk" TNM_NET = "clk";
#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
 
# Leonardo
#NET "Clk" LOC = "P77";
#NET "Reset_n" LOC = "P133";
#NET "Port_D(0)" LOC = "P98";
#NET "Port_D(1)" LOC = "P96";
 
# XST
NET "clk" LOC = "P77";
NET "reset_n" LOC = "P133";
NET "port_d<0>" LOC = "P98";
NET "port_d<1>" LOC = "P96";
/ax8/trunk/syn/xilinx/bin/a90s2313.tcl
0,0 → 1,47
set process "5"
set part "2s200pq208"
set tristate_map "FALSE"
set opt_auto_mode "TRUE"
set opt_best_result "29223.458000"
set dont_lock_lcells "auto"
set input2output "20.000000"
set input2register "20.000000"
set register2output "20.000000"
set register2register "20.000000"
set wire_table "xis215-5_avg"
set encoding "auto"
set edifin_ground_port_names "GND"
set edifin_power_port_names "VCC"
set edif_array_range_extraction_style "%s\[%d:%d\]"
 
set_xilinx_eqn
 
load_library xis2
 
read -technology xis2 {
../../../rtl/vhdl/AX_Pack.vhd
../../../rtl/vhdl/AX_DPRAM.vhd
../../../rtl/vhdl/AX_Reg.vhd
../../../rtl/vhdl/AX_ALU.vhd
../../../rtl/vhdl/AX_RAM.vhd
../../../rtl/vhdl/AX_PCS.vhd
../../../rtl/vhdl/AX8.vhd
../../../rtl/vhdl/AX_Port.vhd
../../../rtl/vhdl/AX_TC8.vhd
../../../rtl/vhdl/AX_TC16.vhd
../../../rtl/vhdl/AX_UART.vhd
../src/ROM2313_Sine_leo.vhd
../../../rtl/vhdl/A90S2313.vhd
}
 
pre_optimize
 
optimize -hierarchy=auto
 
optimize_timing
 
report_area
 
report_delay
 
write a90s2313_leo.edf
/ax8/trunk/syn/xilinx/bin/a90s1200.prj
0,0 → 1,10
../../../rtl/vhdl/AX_Pack.vhd
../../../rtl/vhdl/AX_DPRAM.vhd
../../../rtl/vhdl/AX_Reg.vhd
../../../rtl/vhdl/AX_ALU.vhd
../../../rtl/vhdl/AX_PCS.vhd
../../../rtl/vhdl/AX8.vhd
../../../rtl/vhdl/AX_Port.vhd
../../../rtl/vhdl/AX_TC8.vhd
../src/ROM1200_Echo.vhd
../../../rtl/vhdl/A90S1200.vhd
/ax8/trunk/syn/xilinx/bin/a90s2313.pin
0,0 → 1,7
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
 
NET "clk" LOC = "P77";
NET "reset_n" LOC = "P133";
NET "rxd" LOC = "P98";
NET "txd" LOC = "P96";
/ax8/trunk/syn/xilinx/bin/a90s1200.scr
0,0 → 1,7
run
-ifn ../bin/a90s1200.prj
-ifmt VHDL
-ofn ../out/a90s1200.ngc
-ofmt NGC -p xc2s200-pq208-5
-opt_mode Speed
-opt_level 2
/ax8/trunk/syn/xilinx/bin/a90s2313.scr
0,0 → 1,7
run
-ifn ../bin/a90s2313.prj
-ifmt VHDL
-ofn ../out/a90s2313.ngc
-ofmt NGC -p xc2s200-pq208-5
-opt_mode Speed
-opt_level 2
/ax8/trunk/syn/xilinx/log/.keepme
/ax8/trunk/syn/xilinx/src/.keepme --- ax8/trunk/sim/rtl_sim/bin/compile.do (nonexistent) +++ ax8/trunk/sim/rtl_sim/bin/compile.do (revision 31) @@ -0,0 +1,20 @@ +vcom ../../../rtl/vhdl/AX_Pack.vhd +vcom ../../../rtl/vhdl/AX_DPRAM.vhd +vcom ../../../rtl/vhdl/AX_Reg.vhd +vcom ../../../rtl/vhdl/AX_ALU.vhd +vcom ../../../rtl/vhdl/AX_PCS.vhd +vcom ../../../rtl/vhdl/AX_RAM.vhd +vcom ../../../rtl/vhdl/AX8.vhd +vcom ../../../rtl/vhdl/AX_Port.vhd +vcom ../../../rtl/vhdl/AX_TC8.vhd +vcom ../../../rtl/vhdl/AX_TC16.vhd +vcom ../../../rtl/vhdl/AX_UART.vhd +vcom ../../../syn/xilinx/src/ROM1200_Echo_leo.vhd +vcom ../../../syn/xilinx/src/ROM2313_Sine_leo.vhd +vcom ../../../rtl/vhdl/A90S1200.vhd +vcom ../../../rtl/vhdl/A90S2313.vhd +vcom ../../../bench/vhdl/StimLog.vhd -93 +vcom ../../../bench/vhdl/AsyncLog.vhd -93 +vcom ../../../bench/vhdl/AsyncStim.vhd -93 +vcom ../../../bench/vhdl/TestBench1200.vhd -93 +vcom ../../../bench/vhdl/TestBench2313.vhd -93
/ax8/trunk/bench/vhdl/TestBench1200.vhd
0,0 → 1,28
library IEEE;
use IEEE.std_logic_1164.all;
use work.StimLog.all;
 
entity TestBench1200 is
end TestBench1200;
 
architecture behaviour of TestBench1200 is
 
signal Clk : std_logic := '0';
signal Reset_n : std_logic := '0';
signal Port_B : std_logic_vector(7 downto 0);
signal Port_D : std_logic_vector(7 downto 0);
 
begin
 
p1 : entity work.A90S1200 port map (Clk, Reset_n, '1', '1', Port_B, Port_D);
 
as : AsyncStim generic map(FileName => "../../../rtl/vhdl/AX8.vhd", InterCharDelay => 200 us, Baud => 115200, Bits => 8)
port map(Port_D(0));
 
al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 115200, Bits => 8)
port map(Port_D(1));
 
Clk <= not Clk after 50 ns;
Reset_n <= '1' after 200 ns;
 
end;
/ax8/trunk/bench/vhdl/TestBench2313.vhd
0,0 → 1,69
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.StimLog.all;
 
entity TestBench2313 is
end TestBench2313;
 
architecture behaviour of TestBench2313 is
 
signal Clk : std_logic := '0';
signal Reset_n : std_logic := '0';
signal RXD : std_logic;
signal TXD : std_logic;
signal OC : std_logic;
signal Port_B : std_logic_vector(7 downto 0);
signal Port_D : std_logic_vector(7 downto 0);
 
signal KeyboardClk : std_logic;
signal KeyboardData : unsigned(7 downto 0);
 
begin
 
p1 : entity work.A90S2313 port map(Clk, Reset_n, KeyboardClk, '1', '1', '1', '1', RXD, TXD, OC, Port_B, Port_D);
 
as : AsyncStim generic map(FileName => "../../../rtl/vhdl/AX8.vhd", InterCharDelay => 0 us, Baud => 57600, Bits => 8)
port map(RXD);
 
al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 57600, Bits => 8)
port map(TXD);
 
Clk <= not Clk after 50 ns;
Reset_n <= '1' after 200 ns;
 
-- Generate AT keyboard signals
process
begin
Port_D(3) <= '1';
KeyboardClk <= '1';
KeyboardData <= "00000110";
loop
wait for 400 us;
for i in 0 to 10 loop
if i = 0 then
Port_D(3) <= '0';
elsif i = 9 then
Port_D(3) <= not KeyboardData(0) xor
KeyboardData(1) xor
KeyboardData(2) xor
KeyboardData(3) xor
KeyboardData(4) xor
KeyboardData(5) xor
KeyboardData(6) xor
KeyboardData(7);
elsif i = 10 then
Port_D(3) <= '1';
else
Port_D(3) <= KeyboardData(i - 1);
end if;
wait for 20 us;
KeyboardClk <= '0';
wait for 20 us;
KeyboardClk <= '1';
end loop;
KeyboardData <= KeyboardData + 1;
end loop;
end process;
 
end;
/ax8/trunk/bench/vhdl/AsyncLog.vhd
0,0 → 1,124
--
-- Asynchronous serial input with binary file log
--
-- Version : 0146
--
-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AsyncLog is
generic(
FileName : string;
Baud : integer;
Bits : integer := 8; -- Data bits
Parity : boolean := false; -- Enable Parity
P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
);
port(
RXD : in std_logic
);
end AsyncLog;
 
architecture behaviour of AsyncLog is
 
function to_char(
constant Byte : std_logic_vector(7 downto 0)
) return character is
begin
return character'val(to_integer(unsigned(Byte)));
end function;
 
signal Baud16 : std_logic := '0';
 
-- Receive signals
signal Bit_Phase : unsigned(3 downto 0) := "0000";
signal RX_ShiftReg : std_logic_vector(Bits - 1 downto 0) := (others => '0');
signal RX_Bit_Cnt : integer := 0;
signal ParTmp : boolean;
 
begin
 
Baud16 <= not Baud16 after 1000000000 ns / 32 / Baud;
 
process (Baud16)
type ChFile is file of character;
file OutFile : ChFile open write_mode is FileName;
begin
if Baud16'event and Baud16 = '1' then
if RX_Bit_Cnt = 0 and (RXD = '1' or Bit_Phase = "0111") then
Bit_Phase <= "0000";
else
Bit_Phase <= Bit_Phase + 1;
end if;
if RX_Bit_Cnt = 0 then
if Bit_Phase = "0111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
end if;
ParTmp <= false;
elsif Bit_Phase = "1111" then
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
if (RX_Bit_Cnt = Bits + 1 and not Parity) or
(RX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
RX_Bit_Cnt <= 0;
assert RXD = '1'
report "Framing error"
severity error;
write(OutFile, to_char(RX_ShiftReg(7 downto 0)));
elsif RX_Bit_Cnt = Bits + 1 and Parity then -- Parity bit
assert ParTmp xor (RXD = '1') = P_Odd_Even_n
report "Parity error"
severity error;
else
ParTmp <= ParTmp xor (RXD = '1');
RX_ShiftReg(Bits - 2 downto 0) <= RX_ShiftReg(Bits - 1 downto 1);
RX_ShiftReg(Bits - 1) <= RXD;
end if;
end if;
end if;
end process;
 
end;
 
/ax8/trunk/bench/vhdl/AsyncStim.vhd
0,0 → 1,115
--
-- Asynchronous serial generator with input from binary file
--
-- Version : 0146
--
-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity AsyncStim is
generic(
FileName : string;
Baud : integer;
InterCharDelay : time := 0 ns;
Bits : integer := 8; -- Data bits
Parity : boolean := false; -- Enable Parity
P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
);
port(
TXD : out std_logic
);
end AsyncStim;
 
architecture behaviour of AsyncStim is
 
signal TX_ShiftReg : std_logic_vector(Bits - 1 downto 0);
signal TX_Bit_Cnt : integer range 0 to 15 := 0;
signal ParTmp : boolean;
 
begin
 
process
type ChFile is file of character;
file InFile : ChFile open read_mode is FileName;
variable Inited : boolean := false;
variable CharTmp : character;
variable IntTmp : integer;
begin
if not Inited then
Inited := true;
TXD <= '1';
end if;
wait for 1000000000 ns / Baud;
TX_Bit_Cnt <= TX_Bit_Cnt + 1;
case TX_Bit_Cnt is
when 0 =>
TXD <= '1';
wait for InterCharDelay;
when 1 => -- Start bit
read(InFile, CharTmp);
IntTmp := character'pos(CharTmp);
TX_ShiftReg(Bits - 1 downto 0) <= std_logic_vector(to_unsigned(IntTmp, Bits));
TXD <= '0';
ParTmp <= P_Odd_Even_n;
when others =>
TXD <= TX_ShiftReg(0);
ParTmp <= ParTmp xor (TX_ShiftReg(0) = '1');
TX_ShiftReg(Bits - 2 downto 0) <= TX_ShiftReg(Bits - 1 downto 1);
if (TX_Bit_Cnt = Bits + 1 and not Parity) or
(TX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
TX_Bit_Cnt <= 0;
end if;
if Parity and TX_Bit_Cnt = Bits + 2 then
if ParTmp then
TXD <= '1';
else
TXD <= '0';
end if;
end if;
end case;
end process;
 
end;
/ax8/trunk/bench/vhdl/StimLog.vhd
0,0 → 1,142
--
-- File I/O test-bench utilities
--
-- Version : 0146
--
-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package StimLog is
 
component AsyncStim
generic(
FileName : string;
Baud : integer;
InterCharDelay : time := 0 ns;
Bits : integer := 8; -- Data bits
Parity : boolean := false; -- Enable Parity
P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
);
port(
TXD : out std_logic
);
end component;
 
component AsyncLog
generic(
FileName : string;
Baud : integer;
Bits : integer := 8; -- Data bits
Parity : boolean := false; -- Enable Parity
P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
);
port(
RXD : in std_logic
);
end component;
 
component BinaryStim
generic(
FileName : string;
Bytes : integer := 1; -- Number of bytes per word
LittleEndian : boolean := true -- Byte order
);
port(
Rd : in std_logic;
Data : out std_logic_vector(Bytes * 8 - 1 downto 0)
);
end component;
 
component BinaryLog
generic(
FileName : string;
Bytes : integer := 1; -- Number of bytes per word
LittleEndian : boolean := true -- Byte order
);
port(
Clk : in std_logic;
En : in std_logic;
Data : in std_logic_vector(Bytes * 8 - 1 downto 0)
);
end component;
 
component I2SStim is
generic(
FileName : string;
Bytes : integer := 2; -- Number of bytes per word (1 to 4)
LittleEndian : boolean := true -- Byte order
);
port(
BClk : in std_logic;
FSync : in std_logic;
SData : out std_logic
);
end component;
 
component I2SLog is
generic(
FileName : string;
Bytes : integer := 2; -- Number of bytes per word
LittleEndian : boolean := true -- Byte order
);
port(
BClk : in std_logic;
FSync : in std_logic;
SData : in std_logic
);
end component;
 
component IntegerLog is
generic(
FileName : string
);
port(
Clk : in std_logic;
En : in std_logic;
Data : in integer
);
end component;
 
end;
/ax8/trunk
ax8/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ax8/web_uploads =================================================================== --- ax8/web_uploads (nonexistent) +++ ax8/web_uploads (revision 31)
ax8/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ax8/branches =================================================================== --- ax8/branches (nonexistent) +++ ax8/branches (revision 31)
ax8/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ax8/tags =================================================================== --- ax8/tags (nonexistent) +++ ax8/tags (revision 31)
ax8/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.