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trunk/doc/IMSAI SCS-1 Manual.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/designNotes.tex =================================================================== --- trunk/doc/designNotes.tex (revision 30) +++ trunk/doc/designNotes.tex (nonexistent) @@ -1,596 +0,0 @@ -\documentclass[11pt]{article} -\usepackage{graphicx} % needed for including graphics e.g. EPS, PS -\usepackage{multirow} -\usepackage{alltt} -\topmargin -1.5cm % read Lamport p.163 -\oddsidemargin -0.04cm % read Lamport p.163 -\evensidemargin -0.04cm % same as oddsidemargin but for left-hand pages -\textwidth 16.59cm -\textheight 21.94cm -%\pagestyle{empty} % Uncomment if don't want page numbers -\parskip 7.2pt % sets spacing between paragraphs -%\renewcommand{\baselinestretch}{1.5} % Uncomment for 1.5 spacing between lines -\parindent 15pt % sets leading space for paragraphs - -\begin{document} - -\section{Basic behavior} -\label{basics} - -The microcoded machine ($\mu$M) is built around a register bank and an 8-bit -ALU with registered operands T1 and T2. It performs all its operations in two -cycles, so I have divided it in two stages: an operand stage and an ALU stage. -This is nothing more than a 2-stage pipeline. \\ - -In the operand stage, registers T1 and T2 are loaded with either the -contents of the register bank (RB) or the input signal DI.\\ -In the ALU stage, the ALU output is written back into the RB or loaded -into the output register DO. Besides, flags are updated, or not, according to -the microinstruction ($\mu$I) in execution.\\ - -Every microinstruction controls the operation of the operand stage -and the succeeding ALU stage; that is, the execution of a $\mu$I extends over 2 -succeeding clock cycles, and microinstructions overlap each other. This means -that the part of the $\mu$I that controls the 2nd stage has to be pipelined; in -the VHDL code, I have divided the $\mu$I in a field\_1 and a field\_2, the -latter of which is registered (pipelined) and controls the 2nd $\mu$M stage -(ALU). \\ -Many of the control signals are encoded in the microinstructions in what I -have improperly called flags. You will see many references to flags in the -following text (\#end,\#decode, etc.). They are just signals that you can -activate individually in each $\mu$I, some are active in the 1st stage, some in -the 2nd. They are all explained in section ~\ref{ucodeFlags}. \\ - -Note that microinstructions are atomic: both stages are guaranteed to -execute in all circumstances. Once the 1st stage of a $\mu$I has executed, -the only thing that can prevent the execution of the 2nd stage is a reset.\\ -It might have been easier to design the machine so that microinstructions -executed in one cycle, thus needing no pipeline for the $\mu$I itself. I -arbitrarily chose to 'split' the microcode execution, figuring that it would be -easier for me to understand and program the microcode; in hindsight it may have -been a mistake but in the end, once the debugging is over, it makes little -difference.\\ - -The core as it is now does not support wait states: it does all its -external accesses (memory or i/o, read or write) in one clock cycle. It would -not be difficult to improve this with some little modification to the -micromachine, without changes to the microcode.\\ -Since the microcode rom is the same type of memory as will be used for program -memory, the main advantage of microprogramming is lost. Thus, it would make -sense to develop the core a bit further with support for wait states, so it -could take advantage of the speed difference between the FPGA and external slow -memory.\\ -The register bank reads asynchronously, while writes are synchronous. This -is the standard behaviour of a Spartan LUT-based RAM. The register bank holds -all the 8080 registers, including the accumulator, plus temporary, 'hidden' -registers (x,y,w,z). Only the PSW register is held out of the register bank, in -a DFF-8 register. - -\section{Micromachine control} -\label{umachineControl} - -\subsection{Microcode operation} -\label{ucodeOperation} - -There is little more to the core that what has already been said; all the -CPU operations are microcoded, including interrupt response, reset and -instruction opcode fetch. The microcode source code can be seen in file -\texttt{ucode/light8080.m80}, in a format I expect will be less obscure than a -plain vhdl constant table.\\ - -The microcode table is a synchronous ROM with 512 32-bit words, designed -to fit in a Spartan 3 block ram. Each 32-bit word makes up a microinstruction. -The microcode 'program counter' (uc\_addr in the VHDL code) thus is a 9-bit -register.\\ -Out of those 512 words, 256 (the upper half of the table) are used as a -jump-table for instruction decoding. Each entry at 256+NN contains a 'JSR' -$\mu$I to the start of the microcode for the instruction whose opcode is NN. -This seemingly unefficient use of RAM is in fact an optimization for the -Spartan-3 architecture to which this design is tailored �-- the 2KB RAM blocks -are too large for the microcode so I chose to fill them up with the decoding -table.\\ -This scheme is less than efficient where smaller RAM blocks are available (e.g. -Altera Stratix).\\ -The jump table is built automatically by the microcode -assembler, as explained in section ~\ref{ucodeAssembler}.\\ -The upper half of the table can only be used for decoding; JSR -instructions can only point to the lower half, and execution from address 0x0ff -rolls over to 0x00 (or would; the actual microcode does not use this -'feature').\\ - -The ucode address counter uc\_addr has a number of possible sources: the -micromachine supports one level of micro-subroutine calls; it can also -return from those calls; the uc\_addr gets loaded with some constant values upon -reset, interrupt or instruction fetch. And finally, there is the decoding jump -table mentioned above. So, in summary, these are the possible sources of -uc\_addr each cycle: - -\begin{itemize} -\item Constant value of 0x0001 at reset (see VHDL source for details). -\item Constant value of 0x0003 at the beginning (fetch cycle) of every -instruction. -\item Constant value of 0x0007 at interrupt acknowledge. -\item uc\_addr + 1 in normal microinstruction execution -\item Some 8-bit value included in JSR microinstructions (calls). -\item The return value preserved in the last JSR (used when flag \#ret is -raised) -\end{itemize} - -All of this is readily apparent, I hope, by inspecting the VHDL source. -Note that there is only one jump microinstruction (JSR) which doubles as 'call'; -whenever a jump is taken the the 1-level-deep 'return stack' is loaded with -the return address (address of the $\mu$I following the jump). You just have to -ignore the return address when you don't need it (e.g. the jumps in the decoding -jump table). I admit this scheme is awkward and inflexible; but it was the first -I devised, it works and fits the area budget: more than enough in this project. -A list of all predefined, 'special' microcode addresses follows.\\ -\begin{itemize} -\item \textbf{0x001 �-- reset}\\ -After reset, the $\mu$I program counter (uc\_addr in the VHDL code) is -initialized to 0x00. The program counter works as a pre-increment counter when -reading the microcode rom, so the $\mu$I at address 0 never gets executed (unless -'rolling over' from address 0x0ff, which the actual microcode does not). Reset -starts at address 1 and takes 2 microinstructions to clear PC to 0x0000. It does -nothing else. After clearing the PC the microcode runs into the fetch routine. -\item \textbf{0x003 �-- fetch}\\ -The fetch routine places the PC in the address output lines while postincrementing -it, and then enables a memory read cycle. In doing so it relies on -T2 being 0x00 (necessary for the ADC to behave like an INC in the oversimplified -ALU), which is always true by design. After the fetch is done, the \#decode flag -is raised, which instructs the micromachine to take the value in the DI signal -(data input from external memory) and load it into the IR and the microcode -address counter, while setting the high address bit to 1. At the resulting -address there will be a JSR $\mu$I pointing to the microcode for the 8080 opcode in -question (the microcode assembler will make sure of that). The \#decode flag will -also clear registers T1 and T2. -\item \textbf{0x007 �-- halt}\\ -Whenever a HALT instruction is executed, the \#halt flag is raised, which -when used in the same $\mu$I as flag \#end, makes the the micromachine jump to this -address. The $\mu$I at this address does nothing but raise flags \#halt and \#end. The -micromachine will keep jumping to this address until the halt state is left, -something which can only happen by reset or by interrupt. The \#halt flag, when -raised, sets the halt output signal, which will be cleared when the CPU exits -the halt state. -\end{itemize} - -\subsection{Conditional jumps} -\label{conditionalJumps} - -There is a conditional branch microinstruction: TJSR. This instruction -tests certain condition and, if the condition is true, performs exactly as JSR. -Otherwise, it ends the microcode execution exactly as if the flag \#end had been -raised. This microinstruction has been made for the conditional branches and -returns of the 8080 CPU and is not flexible enough for any other use. -The condition tested is encoded in the register IR, in the field ccc (bits -5..3), as encoded in the conditional instructions of the 8080 �-- you can look -them up in any 8080 reference. Flags are updated in the 2nd stage, so a TJSR -cannot test the flags modified by the previous $\mu$I. But it is not necessary; this -instruction will always be used to test conditions set by previous 8080 -instructions, separated at least by the opcode fetch $\mu$Is, and probably many -more. Thus, the condition flags will always be valid upon testing. - -\subsection{Implicit operations} -\label{implicitOperations} - -Most micromachine operations happen only when explicitly commanded. But -some happen automatically and have to be taken into account when coding the -microprogram: - -\begin{enumerate} -\item Register IR is loaded automatically when the flag \#decode is raised. The -microcode program counter is loaded automatically with the same value as -the IR, as has been explained above. From that point on, execution resumes -normally: the jump table contains normal JSR microinstructions. -\item T1 is cleared to 0x00 at reset, when the flag \#decode is active or when -the flag \#clrt1 is used. -\item T2 is cleared to 0x00 at reset, when the flag \#decode is active or when -the flag \#end is used. -\item Microcode flow control: - \begin{enumerate} - \item When flag \#end is raised, execution continues at $\mu$code address - 0x0003. - \item When both flags \#halt and \#end are raised, execution continues at - $\mu$code address 0x0007, unless there is an interrupt pending. - \item Otherwise, when flag \#ret is raised, execution continues in the address - following the last JSR executed. If such a return is tried before a JSR - has executed since the last reset, the results are undefined �-- this - should never happen with the microcode source as it is now. - \item If none of the above flags are used, the next $\mu$I is executed. - \end{enumerate} -\end{enumerate} - -Notice that both T1 and T2 are cleared at the end of the opcode fetch, so -they are guaranteed to be 0x00 at the beginning of the instruction microcode. -And T2 is cleared too at the end of the instruction microcode, so it is -guaranteed clear for its use in the opcode fetch microcode. T1 can be cleared -if a microinstruction so requires. Refer to the section on microinstruction -flags. - - -\section{Microinstructions} -\label{uinstructions} - -The microcode for the CPU is a source text file encoded in a format -described below. This 'microcode source' is assembled by the microcode assembler -(described later) which then builds a microcode table in VHDL format. There's -nothing stopping you from assembling the microcode by hand directly on the VHDL -source, and in a machine this simple it might have been better. - - -\subsection{Microcode source format} -\label{ucodeFormat} - -The microcode source format is more similar to some early assembly language -that to other microcodes you may have seen. Each non-blank, -non-comment line of code contains a single microinstruction in the format -informally described below: - -% there must be some cleaner way to do this in TeX... - -\begin{alltt} -\textless microinstruction line \textgreater := - [\textless label \textgreater]\footnote{Labels appear alone by themselves in a line} \textbar - \textless operand stage control \textgreater ; \textless ALU stage control \textgreater [; [\textless flag list \textgreater]] \textbar - JSR \textless destination address \textgreater\textbar TJSR \textless destination address \textgreater - \\ - \textless label \textgreater := \{':' immediately followed by a common identifier\} - \textless destination address \textgreater := \{an identifier defined as a label anywhere in the file\} - \textless operand stage control \textgreater := \textless op\_reg \textgreater = \textless op\_src \textgreater \textbar NOP - \textless op\_reg \textgreater := T1 \textbar T2 - \textless op\_src \textgreater := \textless register \textgreater \textbar DI \textbar \textless IR register \textgreater - \textless IR register \textgreater := \{s\}\textbar\{d\}\textbar\{p\}0\textbar\{p\}1\footnote{Registers are specified by IR field} - \textless register \textgreater := \_a\textbar\_b\textbar\_c\textbar\_d\textbar\_e\textbar\_h\textbar\_l\textbar\_f\textbar\_a\textbar\_ph\textbar\_pl\textbar\_x\textbar\_y\textbar\_z\textbar\_w\textbar\_sh\textbar\_sl - \textless ALU stage control \textgreater := \textless alu\_dst \textgreater = \textless alu\_op \textgreater \textbar NOP - \textless alu\_dst \textgreater := \textless register \textgreater \textbar DO - \textless alu\_op \textgreater := add\textbar adc\textbar sub\textbar sbb\textbar and\textbar orl\textbar not\textbar xrl\textbar rla\textbar rra\textbar rlca\textbar rrca\textbar aaa\textbar - t1\textbar rst\textbar daa\textbar cpc\textbar sec\textbar psw - \textless flag list \textgreater := \textless flag \textgreater [, \textless flag \textgreater ...] - \textless flag \textgreater := \#decode\textbar\#di\textbar\#ei\textbar\#io\textbar\#auxcy\textbar\#clrt1\textbar\#halt\textbar\#end\textbar\#ret\textbar\#rd\textbar\#wr\textbar\#setacy - \#ld\_al\textbar\#ld\_addr\textbar\#fp\_c\textbar\#fp\_r\textbar\#fp\_rc \footnote{There are some restrictions on the flags that can be used together} \\ -\end{alltt} - - -Please bear in mind that this is just an informal description; I made -it up from my personal notes and the assembler source. The ultimate reference is -the microcode source itself and the assembler source.\\ -Due to the way that flags have been encoded (there's less than one bit per -flag in the microinstruction), there are restrictions on what flags can be used -together. See section ~\ref{ucodeFlags}. - -The assembler will complain if the source does not comply with the -expected format; but syntax check is somewhat weak. -In the microcode source you will see words like \_\_reset, \_\_fetch, etc. -which don't fit the above syntax. Those were supposed to be assembler pragmas, -which the assembler would use to enforce the alignment of the microinstructions -to certain addresses. I finally decided not to use them and align the -instructions myself. The assembler ignores them but I kept them as a reminder. - -The 1st part of the $\mu$I controls the ALU operand stage; we can load either -T1 or T2 with either the contents of the input signal DI, or the selected -register from the register bank. Or, we can do nothing (NOP).\\ -The 2nd part of the $\mu$I controls the ALU stage; we can instruct the ALU to -perform some operation on the operands T1 and T2 loaded by this same -instruction, in the previous stage; and we can select where to load the ALU -result, eiher in the output register DO or in the register bank. Or we can do -nothing of the above (NOP). - -The write address for the register bank used in the 2nd stage has to be the -same as the read address used in the 1st stage; that is, if both $\mu$I parts use the -RB, both have to use the same address (the assembler will enforce this -restriction). This is due to an early, silly mistake that I chose not to fix: -there is a single $\mu$I field that holds both addresses.\\ -This is a very annoying limitation that unduly complicates the microcode -and wastes many microcode slots for no saving in hardware; I just did not want -to make any major refactors until the project is working. As -you can see in the VHDL source, the machine is prepared to use 2 independent -address fields with little modification. I may do this improvement and others -in a later version, but only when I deem the design 'finished' (since the design -as it is already exceeds my modest performance target). - - -\subsection{Microcode ALU operations} -\label{ucodeAluOps} - -\begin{tabular}{|l|l|l|l|} -\hline -\multicolumn{4}{|c|}{ALU operations} \\ -\hline -Operation & encoding & result & notes \\ - -\hline ADD & 001100 & T2 + T1 & \\ -\hline ADC & 001101 & T2 + T1 + CY & \\ -\hline SUB & 001110 & T2 - T1 & \\ -\hline SBB & 001111 & T2 � T1 - CY & \\ -\hline AND & 000100 & T1 AND T2 & \\ -\hline ORL & 000101 & T1 OR T2 & \\ -\hline NOT & 000110 & NOT T1 & \\ -\hline XRL & 000111 & T1 XOR T2 & \\ -\hline RLA & 000000 & 8080 RLC & \\ -\hline RRA & 000001 & 8080 RRC & \\ -\hline RLCA & 000010 & 8080 RAL & \\ -\hline RRCA & 000011 & 8080 RAR & \\ -\hline T1 & 010111 & T1 & \\ -\hline RST & 011111 & 8*IR(5..3) & as per RST instruction \\ -\hline DAA & 101000 & DAA T1 & but only after executing 2 in a row \\ -\hline CPC & 101100 & UNDEFINED & CY complemented \\ -\hline SEC & 101101 & UNDEFINED & CY set \\ -\hline PSW & 110000 & PSW & \\ -\hline - -\end{tabular} - - - -Notice that ALU operation DAA takes two cycles to complete; it uses a -dedicated circuit with an extra pipeline stage. So it has to be executed twice -in a row before taking the result -- refer to microcode source for an example.\\ -The PSW register is updated with the ALU result at every cycle, whatever -ALU operation is executed �- though every ALU operation computes flags by -different means, as it is apparent in the case of CY. Which flags are updated, -and which keep their previous values, is defined by a microinstruction field -named flag\_pattern. See the VHDL code for details. - - -\subsection{Microcode binary format} -\label{ucodeBinFormat} - -\begin{tabular}{|l|l|l|} -\hline -\multicolumn{3}{|c|}{Microcode word bitfields} \\ \hline -POS & VHDL NAME & PURPOSE \\ \hline -31..29 & uc\_flags1 & Encoded flag of group 1 (see section on flags) \\ \hline -28..26 & uc\_flags2 & Encoded flag of group 2 (see section on flags) \\ \hline -25 & load\_addr & Address register load enable (note 1) \\ \hline -24 & load\_al & AL load enable (note 1) \\ \hline -23 & load\_t1 & T1 load enable \\ \hline -22 & load\_t2 & T2 load enable \\ \hline -21 & mux\_in & T1/T2 source mux control (0 for DI, 1 for reg bank) \\ \hline -20..19 & rb\_addr\_sel & Register bank address source control (note 2) \\ \hline -18..15 & ra\_field & Register bank address (used both for write and read) \\ \hline -14 & (unused) & Reserved \\ \hline -13..10 & (unused) & Reserved for write register bank address, unused yet \\ \hline -11..10 & uc\_jmp\_addr(7..6) & JSR/TJSR jump address, higher 2 bits \\ \hline -9..8 & flag\_pattern & PSW flag update control (note 3) (pipelined signal) \\ \hline -7 & load\_do & DO load enable (note 4) (pipelined signal) \\ \hline -6 & we\_rb & Register bank write enable (pipelined signal) \\ \hline -5..0 & uc\_jmp\_addr(5..0) & JSR/TJSR jump address, lower 6 bits \\ \hline -5..0 & (several) & Encoded ALU operation \\ \hline -\end{tabular} - -\begin{itemize} -\item {\bf Note 1: load\_al}\\ -AL is a temporary register for the lower byte of the external 16 bit -address. The memory interface (and the IO interface) assumes external -synchronous memory, so the 16 bit address has to be externally loaded as -commanded by load\_addr. -Note that both halves of the address signal load directly from the -register bank output; you can load AL with PC, for instance, in the same cycle -in which you modify the PC �- AL will load with the pre-modified value. - -\item {\bf Note 2 : rb\_addr\_sel}\\ -A microinstruction can access any register as specified by ra\_field, or -the register fields in the 8080 instruction opcode: S, D and RP (the -microinstruction can select which register of the pair). In the microcode source -this is encoded like this: -\begin{description} -\item[\{s\}] $\Rightarrow$ 0 \& SSS -\item[\{d\}] $\Rightarrow$ 0 \& DDD -\item[\{p\}0] $\Rightarrow$ 1 \& PP \& 0 (HIGH byte of register pair) -\item[\{p\}1] $\Rightarrow$ 1 \& PP \& 1 (LOW byte of register pair) -\end{description} -\small SSS = IR(5 downto 3) (source register)\\ -\small DDD = IR(2 downto 0) (destination register)\\ -\small PP = IR(5 downto 4) (register pair)\\ - -\item {\bf Note 3 : flag\_pattern}\\ -Selects which flags of the PSW, if any, will be updated by the -microinstruction: -\begin{itemize} -\item When flag\_pattern(0)='1', CY is updated in the PSW. -\item When flag\_pattern(1)='1', all flags other than CY are updated in the PSW. -\end{itemize} - -\item {\bf Note 4 : load\_do}\\ -DO is the data ouput register that is loaded with the ALU output, so the -load enable signal is pipelined. - -\item {\bf Note 5 : JSR-H and JSR-L}\\ -These fields overlap existing fields which are unused in JSR/TJSR -instructions (fields which can be used with no secondary effects). - -\end{itemize} - -\subsection{Microcode flags} -\label{ucodeFlags} - - -Flags is what I have called those signals of the microinstruction that you -assert individually in the microcode source. Due to the way they have been -encoded, I have separated them in two groups. Only one flag in each group can be -used in any instruction. These are all the flags in the format thay appear in -the microcode source: - -\begin{itemize} -\item Flags from group 1: use only one of these - \begin{itemize} - \item \#decode : Load address counter and IR with contents of data input - lines, thus starting opcode decoging. - \item \#ei : Set interrupt enable register. - \item \#di : Reset interrupt enable register. - \item \#io : Activate io signal for 1st cycle. - \item \#auxcy : Use aux carry instead of regular carry for this $\mu$I. - \item \#clrt1 : Clear T1 at the end of 1st cycle. - \item \#halt : Jump to microcode address 0x07 without saving return value, - when used with flag \#end, and only if there is no interrupt - pending. Ignored otherwise. - \end{itemize} - -\item Flags from group 2: use only one of these - \begin{itemize} - \item \#setacy : Set aux carry at the start of 1st cycle (used for ++). - \item \#end : Jump to microinstruction address 3 after the present m.i. - \item \#ret : Jump to address saved by the last JST or TJSR m.i. - \item \#rd : Activate rd signal for the 2nd cycle. - \item \#wr : Activate wr signal for the 2nd cycle. - \end{itemize} - -\item Independent flags: no restrictions - \begin{itemize} - \item \#ld\_al : Load AL register with register bank output as read by opn. 1 - (used in memory and io access). - \item \#ld\_addr : Load address register (H byte = register bank output as read - by operation 1, L byte = AL). - Activate vma signal for 1st cycle. - \end{itemize} - -\item PSW update flags: use only one of these - \begin{itemize} - \item \#fp\_r : This instruction updates all PSW flags except for C. - \item \#fp\_c : This instruction updates only the C flag in the PSW. - \item \#fp\_rc : This instruction updates all the flags in the PSW. - \end{itemize} - -\end{itemize} - -\section{Notes on the microcode assembler} -\label{ucodeAssembler} - -The microcode assembler is a Perl script (\texttt{util/uasm.pl}). Please refer -to the comments in the script for a reference on the usage of the assembler.\\ -I will admit up front that the microcode source format and the assembler -program itself are a mess. They were hacked quickly and then often retouched -but never redesigned, in order to avoid the 'never ending project' syndrome.\\ -Please note that use of the assembler, and the microcode assembly source, -is optional and perhaps overkill for this simple core. All you need to build the -core is the vhdl source file.\\ - -The perl assembler itself accounted for more than half of all the bugs I caught -during development. -Though the assembler certainly saved me a lot of mistakes in the hand-assembly -of the microcode, a half-cooked assembler like -this one may do more harm than good. I expect that the program now behaves -correctly; I have done a lot of modifications to the microcode source for -testing purposes and I have not found any more bugs in the assembler. But you -have been warned: don't trust the assembler too much (in case someone actually -wants to mess with these things at all).\\ -The assembler is a Perl program (\texttt{util/uasm.pl}) that will read a -microcode text source file and write to stdout a microcode table in the form of -a chunk of VHDL code. You are supposed to capture that output and paste it into -the VHDL source (Actually, I used another perl script to do that, but I don't -want to overcomplicate an already messy documentation).\\ -The assembler can do some other simple operations on the source, for debug -purposes. The invocation options are documented in the program file.\\ -You don't need any extra Perl modules or libraries, any distribution of Perl 5 -will do -� earlier versions should too but might not, I haven't -tested. - -\section{CPU details} -\label{cpuDetails} - -\subsection{Synchronous memory and i/o interface} -\label{syncMem} - -The core is designed to connect to external synchronous memory similar to -the internal fpga ram blocks found in the Spartan series. It can be used with -asynchronous ram provided that you add the necessary registers (I have used it -with external SRAM included on a development board with no trouble). - -Signal 'vma' is the master read/write enable. It is designed to be used as -a synchronous rd/wr enable. All other memory/io signals are only valid when vma -is active. Read data is sampled in the positive clock edge following deassertion -of vma. Than is, the core expects external memory and io to behave as an -internal fpga block ram would.\\ -I think the interface is simple enough to be fully described by the -comments in the header of the VHDL source file. - -\subsection{Interrupt response} -\label{irqResponse} - -Interrupt response has been greatly simplified, but it follows the outline -of the original procedure. The biggest difference is that inta is -active for the entire duration of the instruction, and not only the opcode fetch -cycle. - -Whenever a high value is sampled in line intr in any positive clock edge, -an interrupt pending flag is internally raised. After the current instruction -finishes execution, the interrupt pending flag is sampled. If active, it is -cleared, interrupts are disabled and the processor enters an inta cycle. If -inactive, the processor enters a fetch cycle as usual. -The inta cycle is identical to a fetch cycle, with the exception that inta -signal is asserted high. - -The processor will fetch an opcode during the first inta cycle and will -execute it normally, except the PC increment will not happen and inta will be -high for the duration of the instruction. Note that though pc increment is -inhibited while inta is high, pc can be explicitly changed (rst, jmp, etc.). -After the special inta instruction execution is done, the processor -resumes normal execution, with interrupts disabled.\\ -The above means that any instruction (even XTHL, which the original 8080 -forbids) can be used as an interrupt vector and will be executed normally. The -core has been tested with rst, lxi and inr, for example. - -Since there's no M1 signal available, feeding multi-byte instructions as -interrupt vectors can be a little complicated. It is up to you to deal with this -situation (i.e. use only single-byte vectors or make up some sort of cycle -counter). - -\subsection{Instruction timing} -\label{timing} - -This core is slower than the original in terms of clocks per instruction. -Since the original 8080 was itself one of the slowest micros ever, this does not -say much for the core. Yet, one of these clocked at 50MHz would outperform an -original 8080 at 25 Mhz, which is fast enough for many control applications --- -except that there are possibly better alternatives.\\ -A comparative table follows. - - -\begin{tabular}{|l|l|l|l|l|l|l|} -\hline -\multicolumn{7}{|c|}{Instruction timing (core vs. original)} \\ \hline - -Opcode & Intel 8080 & Light8080 & & Opcode & Intel 8080 & Light8080 \\ \hline - -MOV r1, r2 & 5 & 6 & & XRA M & 7 & 9 \\ \hline -MOV r, M & 7 & 9 & & XRI data & 7 & 9 \\ \hline -MOV M, r & 7 & 9 & & ORA r & 4 & 6 \\ \hline -MVI r, data & 7 & 9 & & ORA M & 7 & 9 \\ \hline -MVI M, data & 10 & 12 & & ORI data & 7 & 9 \\ \hline -LXI rp, data16 & 10 & 14 & & CMP r & 4 & 6 \\ \hline -LDA addr & 13 & 16 & & CMP M & 7 & 9 \\ \hline -STA addr & 13 & 16 & & CPI data & 7 & 9 \\ \hline -LHLD addr & 16 & 19 & & RLC & 4 & 5 \\ \hline -SHLD addr & 16 & 19 & & RRC & 4 & 5 \\ \hline -LDAX rp & 7 & 9 & & RAL & 4 & 5 \\ \hline -STAX rp & 7 & 9 & & RAR & 4 & 5 \\ \hline -XCHG & 4 & 16 & & CMA & 4 & 5 \\ \hline -ADD r & 4 & 6 & & CMC & 4 & 5 \\ \hline -ADD M & 7 & 9 & & STC & 4 & 5 \\ \hline -ADI data & 7 & 9 & & JMP & 10 & 15 \\ \hline -ADC r & 4 & 6 & & Jcc & 10 & 12/16 \\ \hline -ADC M & 7 & 9 & & CALL & 17 & 29 \\ \hline -ACI data & 7 & 9 & & Ccc & 11/17 & 12/30 \\ \hline -SUB r & 4 & 6 & & RET & 10 & 14 \\ \hline -SUB M & 7 & 9 & & Rcc & 5/11 & 5/15 \\ \hline -SUI data & 7 & 9 & & RST n & 11 & 20 \\ \hline -SBB r & 4 & 6 & & PCHL & 5 & 8 \\ \hline -SBB M & 7 & 9 & & PUSH rp & 11 & 19 \\ \hline -SBI data & 7 & 9 & & PUSH PSW & 11 & 19 \\ \hline -INR r & 5 & 6 & & POP rp & 10 & 14 \\ \hline -INR M & 10 & 13 & & POP PSW & 10 & 14 \\ \hline -INX rp & 5 & 6 & & XTHL & 18 & 32 \\ \hline -DCR r & 5 & 6 & & SPHL & 5 & 8 \\ \hline -DCR M & 10 & 14 & & EI & 4 & 5 \\ \hline -DCX rp & 5 & 6 & & DI & 4 & 5 \\ \hline -DAD rp & 10 & 8 & & IN port & 10 & 14 \\ \hline -DAA & 4 & 6 & & OUT port & 10 & 14 \\ \hline -ANA r & 4 & 6 & & HLT & 7 & 5 \\ \hline -ANA M & 7 & 9 & & NOP & 4 & 5 \\ \hline -ANI data & 7 & 9 & & & & \\ \hline -XRA r & 4 & 6 & & & & \\ \hline - -\end{tabular} - - -\end{document} - Index: trunk/COPYING.TXT =================================================================== --- trunk/COPYING.TXT (revision 30) +++ trunk/COPYING.TXT (nonexistent) @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. - - If the disclaimer of warranty and limitation of liability provided -above cannot be given local legal effect according to their terms, -reviewing courts shall apply local law that most closely approximates -an absolute waiver of all civil liability in connection with the -Program, unless a warranty or assumption of liability accompanies a -copy of the Program in return for a fee. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Programs - - If you develop a new program, and you want it to be of the greatest -possible use to the public, the best way to achieve this is to make it -free software which everyone can redistribute and change under these terms. - - To do so, attach the following notices to the program. It is safest -to attach them to the start of each source file to most effectively -state the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. Index: trunk/synthesis/tb0_modelsim_wave.do =================================================================== --- trunk/synthesis/tb0_modelsim_wave.do (revision 30) +++ trunk/synthesis/tb0_modelsim_wave.do (nonexistent) @@ -1,42 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(14) &rbank(15) )} SP -quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(8) &rbank(9) )} PC004 -quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(0) &rbank(1) )} BC -quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(2) &rbank(3) )} DE -quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(4) &rbank(5) )} HL -add wave -noupdate -divider {External signals} -add wave -noupdate -format Logic /light8080_tb0/clk -add wave -noupdate -format Logic /light8080_tb0/halt_o -add wave -noupdate -color {Pale Green} -format Literal -radix hexadecimal /light8080_tb0/data_i -add wave -noupdate -color Pink -format Literal -radix hexadecimal /light8080_tb0/data_o -add wave -noupdate -color {Medium Aquamarine} -format Literal -radix hexadecimal /light8080_tb0/addr_o -add wave -noupdate -format Logic /light8080_tb0/vma_o -add wave -noupdate -format Logic /light8080_tb0/rd_o -add wave -noupdate -format Logic /light8080_tb0/wr_o -add wave -noupdate -format Logic /light8080_tb0/fetch_o -add wave -noupdate -divider Registers -add wave -noupdate -color {Medium Slate Blue} -format Literal -label SP -radix hexadecimal /light8080_tb0/uut/SP -add wave -noupdate -color {Indian Red} -format Literal -label PC -radix hexadecimal /light8080_tb0/uut/PC004 -add wave -noupdate -color Yellow -format Literal -itemcolor Yellow -label PSW -radix binary /light8080_tb0/uut/flag_reg -add wave -noupdate -color {Dark Green} -format Literal -label ACC -radix hexadecimal /light8080_tb0/uut/rbank(7) -add wave -noupdate -color Pink -format Literal -itemcolor Pink -label BC -radix hexadecimal /light8080_tb0/uut/BC -add wave -noupdate -color {Indian Red} -format Literal -itemcolor {Indian Red} -label DE -radix hexadecimal /light8080_tb0/uut/DE -add wave -noupdate -color {Yellow Green} -format Literal -itemcolor {Yellow Green} -label HL -radix hexadecimal /light8080_tb0/uut/HL -add wave -noupdate -divider {Internal signals} -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {351700000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 70 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {417733549 ps} {419238323 ps} Index: trunk/synthesis/tb1_modelsim_wave.do =================================================================== --- trunk/synthesis/tb1_modelsim_wave.do (revision 30) +++ trunk/synthesis/tb1_modelsim_wave.do (nonexistent) @@ -1,44 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(14) &rbank(15) )} SP -quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(8) &rbank(9) )} PC004 -quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(0) &rbank(1) )} BC -quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(2) &rbank(3) )} DE -quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(4) &rbank(5) )} HL -add wave -noupdate -divider External -add wave -noupdate -format Logic /light8080_tb1/clk -add wave -noupdate -format Logic /light8080_tb1/halt_o -add wave -noupdate -format Logic /light8080_tb1/inte_o -add wave -noupdate -format Logic /light8080_tb1/intr_i -add wave -noupdate -format Logic /light8080_tb1/inta_o -add wave -noupdate -color {Lime Green} -format Literal -radix hexadecimal /light8080_tb1/data_i -add wave -noupdate -color {Cadet Blue} -format Literal -radix hexadecimal /light8080_tb1/data_o -add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/addr_o -add wave -noupdate -format Logic /light8080_tb1/vma_o -add wave -noupdate -format Logic /light8080_tb1/rd_o -add wave -noupdate -format Logic /light8080_tb1/wr_o -add wave -noupdate -format Logic /light8080_tb1/fetch_o -add wave -noupdate -divider Registers -add wave -noupdate -color {Medium Slate Blue} -format Literal -label SP -radix hexadecimal /light8080_tb1/uut/SP -add wave -noupdate -color {Indian Red} -format Literal -label PC -radix hexadecimal /light8080_tb1/uut/PC004 -add wave -noupdate -color Yellow -format Literal -itemcolor Yellow -label PSW -radix binary /light8080_tb1/uut/flag_reg -add wave -noupdate -color {Dark Green} -format Literal -label ACC -radix hexadecimal /light8080_tb1/uut/rbank(7) -add wave -noupdate -color Pink -format Literal -itemcolor Pink -label BC -radix hexadecimal /light8080_tb1/uut/BC -add wave -noupdate -color {Indian Red} -format Literal -itemcolor {Indian Red} -label DE -radix hexadecimal /light8080_tb1/uut/DE -add wave -noupdate -color {Yellow Green} -format Literal -itemcolor {Yellow Green} -label HL -radix hexadecimal /light8080_tb1/uut/HL -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {81481481 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 70 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {49383750 ps} {126558750 ps} Index: trunk/readme.txt =================================================================== --- trunk/readme.txt (revision 30) +++ trunk/readme.txt (nonexistent) @@ -1,35 +0,0 @@ - -The test programs have been assembled with TASM (Telemark Cross Assembler), -a free assembler available for DOS and Linux. - - -FILE LIST -========== - -vhdl\light8080.vhdl Core source (single file) - -vhdl\test\light8080_tb0.vhdl Test bench 0 (Kelly test) -vhdl\test\light8080_tb1.vhdl Test bench 1 (Interrupts) - -vhdl\demo\cs2b_light8080_demo.vhd Demo for Cyclone 2 starter board -vhdl\demo\rs232_tx.vhdl Serial tx code for demo -vhdl\demo\rs232_rx.vhdl Serial rx code for demo -vhdl\demo\cs2b_demo.csv Pin assignment file for Quartus II - -util\uasm.pl Microcode assembler -util\microrom.bat Sample DOS bat file for assembler - -ucode\light8080.m80 Microcode source file - -synthesis\tb0_modelsim_wave.do Modelsim macro for test bench 0 -synthesis\tb1_modelsim_wave.do Modelsim macro for test bench 1 - -doc\designNotes.tex Core documentation in LaTeX format -doc\designNotes.pdf Core documentation in PDF format -doc\IMSAI SCS-1 Manual.pdf IMSAI SCS-1 original documentation - -asm\tb0.asm Test bench 0 program assembler source -asm\tb1.asm Test bench 1 program assembler source -asm\hexconv.pl Intel HEX to VHDL converter -asm\tasmtb.bat BATCH script to build the test benches -asm\readme.txt How to assemble the sources \ No newline at end of file Index: trunk/vhdl/test/light8080_tb0.vhdl =================================================================== --- trunk/vhdl/test/light8080_tb0.vhdl (revision 30) +++ trunk/vhdl/test/light8080_tb0.vhdl (nonexistent) @@ -1,521 +0,0 @@ --------------------------------------------------------------------------------- --- Generated from template tb_template.vhdl by hexconv.pl --------------------------------------------------------------------------------- --- Light8080 simulation test bench. --------------------------------------------------------------------------------- --- Source for the 8080 program is in asm\tb0.asm --------------------------------------------------------------------------------- --- --- This test bench provides a simulated CPU system to test programs. This test --- bench does not do any assertions or checks, all assertions are left to the --- software. --- --- The simulated environment has 2KB of RAM, mirror-mapped to all the memory --- map of the 8080, initialized with the test program object code. See the perl --- script 'util\hexconv.pl' and BAT files in the asm directory. --- --- Besides, it provides some means to trigger hardware irq from software, --- including the specification of the instructions fed to the CPU as interrupt --- vectors during inta cycles. --- --- We will simulate 8 possible irq sources. The software can trigger any one of --- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq --- source to be triggered (0 to 7) and register 0x011 holds the number of clock --- cycles that will elapse from the end of the instruction that writes to the --- register to the assertion of intr. --- --- When the interrupt is acknowledged and inta is asserted, the test bench reads --- the value at register 0x010 as the irq source, and feeds an instruction to --- the CPU starting from the RAM address 0040h+source*4. --- That is, address range 0040h-005fh is reserved for the simulated 'interrupt --- vectors', a total of 4 bytes for each of the 8 sources. This allows the --- software to easily test different interrupt vectors without any hand --- assembly. All of this is strictly simulation-only stuff. --- --- --- Upon completion, the software must write a value to register 0x020. Writing --- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and --- failure conditions are defined by the software. --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.ALL; - -entity light8080_tb0 is -end entity light8080_tb0; - -architecture behavior of light8080_tb0 is - --------------------------------------------------------------------------------- --- Simulation parameters - --- T: simulated clock period -constant T : time := 100 ns; - --- MAX_SIM_LENGTH: maximum simulation time -constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0 - - --------------------------------------------------------------------------------- - - -- Component Declaration for the Unit Under Test (UUT) -component light8080 - port ( - addr_out : out std_logic_vector(15 downto 0); - - inta : out std_logic; - inte : out std_logic; - halt : out std_logic; - intr : in std_logic; - - vma : out std_logic; - io : out std_logic; - rd : out std_logic; - wr : out std_logic; - fetch : out std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - - clk : in std_logic; - reset : in std_logic ); -end component; - - -signal data_i : std_logic_vector(7 downto 0) := (others=>'0'); -signal vma_o : std_logic; -signal rd_o : std_logic; -signal wr_o : std_logic; -signal io_o : std_logic; -signal data_o : std_logic_vector(7 downto 0); -signal data_mem : std_logic_vector(7 downto 0); -signal addr_o : std_logic_vector(15 downto 0); -signal fetch_o : std_logic; -signal inta_o : std_logic; -signal inte_o : std_logic; -signal intr_i : std_logic := '0'; -signal halt_o : std_logic; - -signal reset : std_logic := '0'; -signal clk : std_logic := '1'; -signal done : std_logic := '0'; - -type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0); - -signal rom : t_rom := ( - -X"31",X"f3",X"05",X"3e",X"77",X"e6",X"00",X"ca", -X"0d",X"00",X"cd",X"e0",X"04",X"d2",X"13",X"00", -X"cd",X"e0",X"04",X"ea",X"19",X"00",X"cd",X"e0", -X"04",X"f2",X"1f",X"00",X"cd",X"e0",X"04",X"c2", -X"2e",X"00",X"da",X"2e",X"00",X"e2",X"2e",X"00", -X"fa",X"2e",X"00",X"c3",X"31",X"00",X"cd",X"e0", -X"04",X"c6",X"06",X"c2",X"39",X"00",X"cd",X"e0", -X"04",X"da",X"42",X"00",X"e2",X"42",X"00",X"f2", -X"45",X"00",X"cd",X"e0",X"04",X"c6",X"70",X"e2", -X"4d",X"00",X"cd",X"e0",X"04",X"fa",X"56",X"00", -X"ca",X"56",X"00",X"d2",X"59",X"00",X"cd",X"e0", -X"04",X"c6",X"81",X"fa",X"61",X"00",X"cd",X"e0", -X"04",X"ca",X"6a",X"00",X"da",X"6a",X"00",X"e2", -X"6d",X"00",X"cd",X"e0",X"04",X"c6",X"fe",X"da", -X"75",X"00",X"cd",X"e0",X"04",X"ca",X"7e",X"00", -X"e2",X"7e",X"00",X"fa",X"81",X"00",X"cd",X"e0", -X"04",X"fe",X"00",X"da",X"99",X"00",X"ca",X"99", -X"00",X"fe",X"f5",X"da",X"99",X"00",X"c2",X"99", -X"00",X"fe",X"ff",X"ca",X"99",X"00",X"da",X"9c", -X"00",X"cd",X"e0",X"04",X"ce",X"0a",X"ce",X"0a", -X"fe",X"0b",X"ca",X"a8",X"00",X"cd",X"e0",X"04", -X"d6",X"0c",X"d6",X"0f",X"fe",X"f0",X"ca",X"b4", -X"00",X"cd",X"e0",X"04",X"de",X"f1",X"de",X"0e", -X"fe",X"f0",X"ca",X"c0",X"00",X"cd",X"e0",X"04", -X"e6",X"55",X"fe",X"50",X"ca",X"ca",X"00",X"cd", -X"e0",X"04",X"f6",X"3a",X"fe",X"7a",X"ca",X"d4", -X"00",X"cd",X"e0",X"04",X"ee",X"0f",X"fe",X"75", -X"ca",X"de",X"00",X"cd",X"e0",X"04",X"e6",X"00", -X"dc",X"e0",X"04",X"e4",X"e0",X"04",X"fc",X"e0", -X"04",X"c4",X"e0",X"04",X"fe",X"00",X"ca",X"f4", -X"00",X"cd",X"e0",X"04",X"d6",X"77",X"d4",X"e0", -X"04",X"ec",X"e0",X"04",X"f4",X"e0",X"04",X"cc", -X"e0",X"04",X"fe",X"89",X"ca",X"0a",X"01",X"cd", -X"e0",X"04",X"e6",X"ff",X"e4",X"17",X"01",X"fe", -X"d9",X"ca",X"74",X"01",X"cd",X"e0",X"04",X"e8", -X"c6",X"10",X"ec",X"23",X"01",X"c6",X"02",X"e0", -X"cd",X"e0",X"04",X"e0",X"c6",X"20",X"fc",X"2f", -X"01",X"c6",X"04",X"e8",X"cd",X"e0",X"04",X"f0", -X"c6",X"80",X"f4",X"3b",X"01",X"c6",X"80",X"f8", -X"cd",X"e0",X"04",X"f8",X"c6",X"40",X"d4",X"47", -X"01",X"c6",X"40",X"f0",X"cd",X"e0",X"04",X"d8", -X"c6",X"8f",X"dc",X"53",X"01",X"d6",X"02",X"d0", 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Test (UUT) - uut: light8080 PORT MAP( - clk => clk, - reset => reset, - vma => vma_o, - rd => rd_o, - wr => wr_o, - io => io_o, - fetch => fetch_o, - addr_out => addr_o, - data_in => data_i, - data_out => data_o, - - intr => intr_i, - inte => inte_o, - inta => inta_o, - halt => halt_o - ); - - --- clock: run clock until test is done -clock: -process(done, clk) -begin - if done = '0' then - clk <= not clk after T/2; - end if; -end process clock; - - --- Drive reset and done -main_test: -process -begin - -- Assert reset for at least one full clk period - reset <= '1'; - wait until clk = '1'; - wait for T/2; - reset <= '0'; - - -- Remember to 'cut away' the preceding 3 clk semiperiods from - -- the wait statement... - wait for (MAX_SIM_LENGTH - T*1.5); - - -- Maximum sim time elapsed, assume the program ran away and - -- stop the clk process asserting 'done' (which will stop the simulation) - done <= '1'; - - assert (done = '1') - report "Test timed out." - severity failure; - - wait; -end process main_test; - - --- Synchronous RAM; 2KB mirrored everywhere -synchronous_ram: -process(clk) -begin - if (clk'event and clk='1') then - data_mem <= rom(conv_integer(addr_o(10 downto 0))); - if wr_o = '1' and addr_o(15 downto 11)="00000" then - rom(conv_integer(addr_o(10 downto 0))) <= data_o; - end if; - end if; -end process synchronous_ram; - - -irq_trigger_register: -process(clk) -begin - if (clk'event and clk='1') then - if reset='1' then - cycles_to_intr <= -10; -- meaning no interrupt pending - intr_i <= '0'; - else - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then - cycles_to_intr <= conv_integer(data_o) + 1; - else - if cycles_to_intr >= 0 then - cycles_to_intr <= cycles_to_intr - 1; - end if; - if cycles_to_intr = 0 then - intr_i <= '1'; - else - intr_i <= '0'; - end if; - end if; - end if; - end if; -end process irq_trigger_register; - - -irq_source_register: -process(clk) -begin - if (clk'event and clk='1') then - if reset='1' then - irq_source <= 0; - else - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then - irq_source <= conv_integer(data_o(2 downto 0)); - end if; - end if; - end if; -end process irq_source_register; - - --- 'interrupt vector' logic. -irq_vector_table: -process(clk) -begin - if (clk'event and clk='1') then - if vma_o = '1' and rd_o='1' then - if inta_o = '1' then - int_vector_index <= int_vector_index + 1; - else - int_vector_index <= 0; - end if; - end if; - -- this is the address of the byte we'll feed to the CPU - addr_vector_table <= 64+irq_source*4+int_vector_index; - end if; -end process irq_vector_table; -irq_vector_byte <= rom(addr_vector_table); - -data_i <= data_mem when inta_o='0' else irq_vector_byte; - - -test_outcome_register: -process(clk) -variable outcome : std_logic_vector(7 downto 0); -begin - if (clk'event and clk='1') then - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then - assert (data_o /= X"55") report "Software reports SUCCESS" severity failure; - assert (data_o /= X"aa") report "Software reports FAILURE" severity failure; - assert ((data_o = X"aa") or (data_o = X"55")) - report "Software reports unexpected outcome value." - severity failure; - end if; - end if; -end process test_outcome_register; - - -end; Index: trunk/vhdl/test/light8080_tb1.vhdl =================================================================== --- trunk/vhdl/test/light8080_tb1.vhdl (revision 30) +++ trunk/vhdl/test/light8080_tb1.vhdl (nonexistent) @@ -1,521 +0,0 @@ --------------------------------------------------------------------------------- --- Generated from template tb_template.vhdl by hexconv.pl --------------------------------------------------------------------------------- --- Light8080 simulation test bench. --------------------------------------------------------------------------------- --- Source for the 8080 program is in asm\tb1.asm --------------------------------------------------------------------------------- --- --- This test bench provides a simulated CPU system to test programs. This test --- bench does not do any assertions or checks, all assertions are left to the --- software. --- --- The simulated environment has 2KB of RAM, mirror-mapped to all the memory --- map of the 8080, initialized with the test program object code. See the perl --- script 'util\hexconv.pl' and BAT files in the asm directory. --- --- Besides, it provides some means to trigger hardware irq from software, --- including the specification of the instructions fed to the CPU as interrupt --- vectors during inta cycles. --- --- We will simulate 8 possible irq sources. The software can trigger any one of --- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq --- source to be triggered (0 to 7) and register 0x011 holds the number of clock --- cycles that will elapse from the end of the instruction that writes to the --- register to the assertion of intr. --- --- When the interrupt is acknowledged and inta is asserted, the test bench reads --- the value at register 0x010 as the irq source, and feeds an instruction to --- the CPU starting from the RAM address 0040h+source*4. --- That is, address range 0040h-005fh is reserved for the simulated 'interrupt --- vectors', a total of 4 bytes for each of the 8 sources. This allows the --- software to easily test different interrupt vectors without any hand --- assembly. All of this is strictly simulation-only stuff. --- --- --- Upon completion, the software must write a value to register 0x020. Writing --- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and --- failure conditions are defined by the software. --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.ALL; - -entity light8080_tb1 is -end entity light8080_tb1; - -architecture behavior of light8080_tb1 is - --------------------------------------------------------------------------------- --- Simulation parameters - --- T: simulated clock period -constant T : time := 100 ns; - --- MAX_SIM_LENGTH: maximum simulation time -constant MAX_SIM_LENGTH : time := T*5000; - - --------------------------------------------------------------------------------- - - -- Component Declaration for the Unit Under Test (UUT) -component light8080 - port ( - addr_out : out std_logic_vector(15 downto 0); - - inta : out std_logic; - inte : out std_logic; - halt : out std_logic; - intr : in std_logic; - - vma : out std_logic; - io : out std_logic; - rd : out std_logic; - wr : out std_logic; - fetch : out std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - - clk : in std_logic; - reset : in std_logic ); -end component; - - -signal data_i : std_logic_vector(7 downto 0) := (others=>'0'); -signal vma_o : std_logic; -signal rd_o : std_logic; -signal wr_o : std_logic; -signal io_o : std_logic; -signal data_o : std_logic_vector(7 downto 0); -signal data_mem : std_logic_vector(7 downto 0); -signal addr_o : std_logic_vector(15 downto 0); -signal fetch_o : std_logic; -signal inta_o : std_logic; -signal inte_o : std_logic; -signal intr_i : std_logic := '0'; -signal halt_o : std_logic; - -signal reset : std_logic := '0'; -signal clk : std_logic := '1'; -signal done : std_logic := '0'; - -type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0); - -signal rom : t_rom := ( - -X"c3",X"60",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", 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Test (UUT) - uut: light8080 PORT MAP( - clk => clk, - reset => reset, - vma => vma_o, - rd => rd_o, - wr => wr_o, - io => io_o, - fetch => fetch_o, - addr_out => addr_o, - data_in => data_i, - data_out => data_o, - - intr => intr_i, - inte => inte_o, - inta => inta_o, - halt => halt_o - ); - - --- clock: run clock until test is done -clock: -process(done, clk) -begin - if done = '0' then - clk <= not clk after T/2; - end if; -end process clock; - - --- Drive reset and done -main_test: -process -begin - -- Assert reset for at least one full clk period - reset <= '1'; - wait until clk = '1'; - wait for T/2; - reset <= '0'; - - -- Remember to 'cut away' the preceding 3 clk semiperiods from - -- the wait statement... - wait for (MAX_SIM_LENGTH - T*1.5); - - -- Maximum sim time elapsed, assume the program ran away and - -- stop the clk process asserting 'done' (which will stop the simulation) - done <= '1'; - - assert (done = '1') - report "Test timed out." - severity failure; - - wait; -end process main_test; - - --- Synchronous RAM; 2KB mirrored everywhere -synchronous_ram: -process(clk) -begin - if (clk'event and clk='1') then - data_mem <= rom(conv_integer(addr_o(10 downto 0))); - if wr_o = '1' and addr_o(15 downto 11)="00000" then - rom(conv_integer(addr_o(10 downto 0))) <= data_o; - end if; - end if; -end process synchronous_ram; - - -irq_trigger_register: -process(clk) -begin - if (clk'event and clk='1') then - if reset='1' then - cycles_to_intr <= -10; -- meaning no interrupt pending - intr_i <= '0'; - else - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then - cycles_to_intr <= conv_integer(data_o) + 1; - else - if cycles_to_intr >= 0 then - cycles_to_intr <= cycles_to_intr - 1; - end if; - if cycles_to_intr = 0 then - intr_i <= '1'; - else - intr_i <= '0'; - end if; - end if; - end if; - end if; -end process irq_trigger_register; - - -irq_source_register: -process(clk) -begin - if (clk'event and clk='1') then - if reset='1' then - irq_source <= 0; - else - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then - irq_source <= conv_integer(data_o(2 downto 0)); - end if; - end if; - end if; -end process irq_source_register; - - --- 'interrupt vector' logic. -irq_vector_table: -process(clk) -begin - if (clk'event and clk='1') then - if vma_o = '1' and rd_o='1' then - if inta_o = '1' then - int_vector_index <= int_vector_index + 1; - else - int_vector_index <= 0; - end if; - end if; - -- this is the address of the byte we'll feed to the CPU - addr_vector_table <= 64+irq_source*4+int_vector_index; - end if; -end process irq_vector_table; -irq_vector_byte <= rom(addr_vector_table); - -data_i <= data_mem when inta_o='0' else irq_vector_byte; - - -test_outcome_register: -process(clk) -variable outcome : std_logic_vector(7 downto 0); -begin - if (clk'event and clk='1') then - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then - assert (data_o /= X"55") report "Software reports SUCCESS" severity failure; - assert (data_o /= X"aa") report "Software reports FAILURE" severity failure; - assert ((data_o = X"aa") or (data_o = X"55")) - report "Software reports unexpected outcome value." - severity failure; - end if; - end if; -end process test_outcome_register; - - -end; Index: trunk/vhdl/test/tb_template.vhdl =================================================================== --- trunk/vhdl/test/tb_template.vhdl (revision 30) +++ trunk/vhdl/test/tb_template.vhdl (nonexistent) @@ -1,264 +0,0 @@ --------------------------------------------------------------------------------- --- Light8080 simulation test bench. --------------------------------------------------------------------------------- --- Source for the 8080 program is in asm\@PROGNAME@.asm --------------------------------------------------------------------------------- --- --- This test bench provides a simulated CPU system to test programs. This test --- bench does not do any assertions or checks, all assertions are left to the --- software. --- --- The simulated environment has 2KB of RAM, mirror-mapped to all the memory --- map of the 8080, initialized with the test program object code. See the perl --- script 'util\hexconv.pl' and BAT files in the asm directory. --- --- Besides, it provides some means to trigger hardware irq from software, --- including the specification of the instructions fed to the CPU as interrupt --- vectors during inta cycles. --- --- We will simulate 8 possible irq sources. The software can trigger any one of --- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq --- source to be triggered (0 to 7) and register 0x011 holds the number of clock --- cycles that will elapse from the end of the instruction that writes to the --- register to the assertion of intr. --- --- When the interrupt is acknowledged and inta is asserted, the test bench reads --- the value at register 0x010 as the irq source, and feeds an instruction to --- the CPU starting from the RAM address 0040h+source*4. --- That is, address range 0040h-005fh is reserved for the simulated 'interrupt --- vectors', a total of 4 bytes for each of the 8 sources. This allows the --- software to easily test different interrupt vectors without any hand --- assembly. All of this is strictly simulation-only stuff. --- --- --- Upon completion, the software must write a value to register 0x020. Writing --- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and --- failure conditions are defined by the software. --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.ALL; - -entity light8080_@PROGNAME@ is -end entity light8080_@PROGNAME@; - -architecture behavior of light8080_@PROGNAME@ is - --------------------------------------------------------------------------------- --- Simulation parameters - --- T: simulated clock period -constant T : time := 100 ns; - --- MAX_SIM_LENGTH: maximum simulation time -constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0 - - --------------------------------------------------------------------------------- - - -- Component Declaration for the Unit Under Test (UUT) -component light8080 - port ( - addr_out : out std_logic_vector(15 downto 0); - - inta : out std_logic; - inte : out std_logic; - halt : out std_logic; - intr : in std_logic; - - vma : out std_logic; - io : out std_logic; - rd : out std_logic; - wr : out std_logic; - fetch : out std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - - clk : in std_logic; - reset : in std_logic ); -end component; - - -signal data_i : std_logic_vector(7 downto 0) := (others=>'0'); -signal vma_o : std_logic; -signal rd_o : std_logic; -signal wr_o : std_logic; -signal io_o : std_logic; -signal data_o : std_logic_vector(7 downto 0); -signal data_mem : std_logic_vector(7 downto 0); -signal addr_o : std_logic_vector(15 downto 0); -signal fetch_o : std_logic; -signal inta_o : std_logic; -signal inte_o : std_logic; -signal intr_i : std_logic := '0'; -signal halt_o : std_logic; - -signal reset : std_logic := '0'; -signal clk : std_logic := '1'; -signal done : std_logic := '0'; - -type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0); - -signal rom : t_rom := ( - ---@rom_data - -); - -signal irq_vector_byte: std_logic_vector(7 downto 0); -signal irq_source : integer range 0 to 7; -signal cycles_to_intr : integer range -10 to 255; -signal int_vector_index : integer range 0 to 3; -signal addr_vector_table: integer range 0 to 65535; - -begin - - -- Instantiate the Unit Under Test (UUT) - uut: light8080 PORT MAP( - clk => clk, - reset => reset, - vma => vma_o, - rd => rd_o, - wr => wr_o, - io => io_o, - fetch => fetch_o, - addr_out => addr_o, - data_in => data_i, - data_out => data_o, - - intr => intr_i, - inte => inte_o, - inta => inta_o, - halt => halt_o - ); - - --- clock: run clock until test is done -clock: -process(done, clk) -begin - if done = '0' then - clk <= not clk after T/2; - end if; -end process clock; - - --- Drive reset and done -main_test: -process -begin - -- Assert reset for at least one full clk period - reset <= '1'; - wait until clk = '1'; - wait for T/2; - reset <= '0'; - - -- Remember to 'cut away' the preceding 3 clk semiperiods from - -- the wait statement... - wait for (MAX_SIM_LENGTH - T*1.5); - - -- Maximum sim time elapsed, assume the program ran away and - -- stop the clk process asserting 'done' (which will stop the simulation) - done <= '1'; - - assert (done = '1') - report "Test timed out." - severity failure; - - wait; -end process main_test; - - --- Synchronous RAM; 2KB mirrored everywhere -synchronous_ram: -process(clk) -begin - if (clk'event and clk='1') then - data_mem <= rom(conv_integer(addr_o(10 downto 0))); - if wr_o = '1' and addr_o(15 downto 11)="00000" then - rom(conv_integer(addr_o(10 downto 0))) <= data_o; - end if; - end if; -end process synchronous_ram; - - -irq_trigger_register: -process(clk) -begin - if (clk'event and clk='1') then - if reset='1' then - cycles_to_intr <= -10; -- meaning no interrupt pending - intr_i <= '0'; - else - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then - cycles_to_intr <= conv_integer(data_o) + 1; - else - if cycles_to_intr >= 0 then - cycles_to_intr <= cycles_to_intr - 1; - end if; - if cycles_to_intr = 0 then - intr_i <= '1'; - else - intr_i <= '0'; - end if; - end if; - end if; - end if; -end process irq_trigger_register; - - -irq_source_register: -process(clk) -begin - if (clk'event and clk='1') then - if reset='1' then - irq_source <= 0; - else - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then - irq_source <= conv_integer(data_o(2 downto 0)); - end if; - end if; - end if; -end process irq_source_register; - - --- 'interrupt vector' logic. -irq_vector_table: -process(clk) -begin - if (clk'event and clk='1') then - if vma_o = '1' and rd_o='1' then - if inta_o = '1' then - int_vector_index <= int_vector_index + 1; - else - int_vector_index <= 0; - end if; - end if; - -- this is the address of the byte we'll feed to the CPU - addr_vector_table <= 64+irq_source*4+int_vector_index; - end if; -end process irq_vector_table; -irq_vector_byte <= rom(addr_vector_table); - -data_i <= data_mem when inta_o='0' else irq_vector_byte; - - -test_outcome_register: -process(clk) -variable outcome : std_logic_vector(7 downto 0); -begin - if (clk'event and clk='1') then - if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then - assert (data_o /= X"55") report "Software reports SUCCESS" severity failure; - assert (data_o /= X"aa") report "Software reports FAILURE" severity failure; - assert ((data_o = X"aa") or (data_o = X"55")) - report "Software reports unexpected outcome value." - severity failure; - end if; - end if; -end process test_outcome_register; - - -end; Index: trunk/vhdl/light8080.vhdl =================================================================== --- trunk/vhdl/light8080.vhdl (revision 30) +++ trunk/vhdl/light8080.vhdl (nonexistent) @@ -1,1349 +0,0 @@ ---############################################################################## --- light8080 : Intel 8080 binary compatible core ---############################################################################## --- v1.1 (20 sep 2008) Microcode bug in INR fixed. --- v1.0 (05 nov 2007) First release. Jose A. Ruiz. --- --- This file and all the light8080 project files are freeware (See COPYING.TXT) ---############################################################################## --- (See timing diagrams at bottom of file. More comprehensive explainations can --- be found in the design notes) ---############################################################################## - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ---############################################################################## --- vma : enable a memory or io r/w access. --- io : access in progress is io (and not memory) --- rd : read memory or io --- wr : write memory or io --- data_out : data output --- addr_out : memory and io address --- data_in : data input --- halt : halt status (1 when in halt state) --- inte : interrupt status (1 when enabled) --- intr : interrupt request --- inta : interrupt acknowledge --- reset : synchronous reset --- clk : clock --- --- (see timing diagrams at bottom of file) ---############################################################################## -entity light8080 is - Port ( - addr_out : out std_logic_vector(15 downto 0); - - inta : out std_logic; - inte : out std_logic; - halt : out std_logic; - intr : in std_logic; - - vma : out std_logic; - io : out std_logic; - rd : out std_logic; - wr : out std_logic; - fetch : out std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - - clk : in std_logic; - reset : in std_logic ); -end light8080; - ---############################################################################## --- All memory and io accesses are synchronous (rising clock edge). Signal vma --- works as the master memory and io synchronous enable. More specifically: --- --- * All memory/io control signals (io,rd,wr) are valid only when vma is --- high. They never activate when vms is inactive. --- * Signals data_out and address are only valid when vma='1'. The high --- address byte is 0x00 for all io accesses. --- * Signal data_in should be valid by the end of the cycle after vma='1', --- data is clocked in by the rising clock edge. --- --- All signals are assumed to be synchronous to the master clock. Prevention of --- metastability, if necessary, is up to you. --- --- Signal reset needs to be active for just 1 clock cycle (it is sampled on a --- positive clock edge and is subject to setup and hold times). --- Once reset is deasserted, the first fetch at address 0x0000 will happen 4 --- cycles later. --- --- Signal intr is sampled on all positive clock edges. If asserted when inte is --- high, interrupts will be disabled, inta will be asserted high and a fetch --- cycle will occur. The fetched instruction will be executed normally, except --- PC will not be valid in any subsequent fetch cycles of the same instruction, --- and will not be incremented (In practice, the same as the original 8080). --- inta will remain high for the duration of the fetched instruction (in the --- original 8080 it was high only for the opcode fetch cycle). --- PC will not be autoincremented while inta is high, but it can be explicitly --- modified (e.g. RTS, CALL, etc.). Again, the same as the original. --- Interrupts will be disabled upon assertion of inta, and remain disabled --- until explicitly enabled by the program (as in the original). --- --- The above means that any instruction can be supplied in an inta cycle, --- either single byte or multibyte. See the design notes. ---############################################################################## - -architecture microcoded of light8080 is - --- addr_low: low byte of address -signal addr_low : std_logic_vector(7 downto 0); --- IR: instruction register. some bits left unused. -signal IR : std_logic_vector(7 downto 0); --- s_field: IR field, sss source reg code -signal s_field : std_logic_vector(2 downto 0); --- d_field: IR field, ddd destination reg code -signal d_field : std_logic_vector(2 downto 0); --- p_field: IR field, pp 16-bit reg pair code -signal p_field : std_logic_vector(1 downto 0); --- rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs -signal rbh : std_logic; -- 1 when P=11 (special case) --- alu_op: uinst field, ALU operation code -signal alu_op : std_logic_vector(3 downto 0); --- DI: data input to ALU block from data_in, unregistered -signal DI : std_logic_vector(7 downto 0); --- uc_addr: microcode (ucode) address -signal uc_addr : std_logic_vector(7 downto 0); --- next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch) -signal next_uc_addr : std_logic_vector(8 downto 0); --- uc_jmp_addr: uinst field, absolute ucode jump address -signal uc_jmp_addr : std_logic_vector(7 downto 0); --- uc_ret_address: ucode return address saved in previous jump -signal uc_ret_addr : std_logic_vector(7 downto 0); --- addr_plus_1: uaddr + 1 -signal addr_plus_1 : std_logic_vector(7 downto 0); --- do_reset: reset, delayed 1 cycle -- used to reset the microcode sequencer -signal do_reset : std_logic; - --- uc_flags1: uinst field, encoded flag of group 1 (see ucode file) -signal uc_flags1 : std_logic_vector(2 downto 0); --- uc_flags2: uinst field, encoded flag of group 2 (see ucode file) -signal uc_flags2 : std_logic_vector(2 downto 0); --- uc_addr_sel: selection of next uc_addr, composition of 4 flags -signal uc_addr_sel : std_logic_vector(3 downto 0); --- NOTE: see microcode file for information on flags -signal uc_jsr : std_logic; -- uinst field, decoded 'jsr' flag -signal uc_tjsr : std_logic; -- uinst field, decoded 'tjsr' flag -signal uc_decode : std_logic; -- uinst field, decoded 'decode' flag -signal uc_end : std_logic; -- uinst field, decoded 'end' flag -signal condition_reg :std_logic; -- registered tjst condition --- condition: tjsr condition (computed ccc condition from '80 instructions) -signal condition : std_logic; --- condition_sel: IR field, ccc condition code -signal condition_sel :std_logic_vector(2 downto 0); -signal uc_do_jmp : std_logic; -- uinst jump (jsr/tjsr) flag, pipelined -signal uc_do_ret : std_logic; -- ret flag, pipelined -signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag -signal uc_halt : std_logic; -- halt command -signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal -signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag -signal uc_di : std_logic; -- uinst field, decoded 'ei' flag -signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal -signal int_pending : std_logic; -- intr requested, inta not active yet -signal inta_reg : std_logic; -- inta status reg, output as 'inta' -signal clr_t1 : std_logic; -- uinst field, explicitly erase T1 -signal do_clr_t1 : std_logic; -- clr_t1 pipelined -signal clr_t2 : std_logic; -- uinst field, explicitly erase T2 -signal do_clr_t2 : std_logic; -- clr_t2 pipelined -signal ucode : std_logic_vector(31 downto 0); -- microcode word -signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode - --- microcode ROM : see design notes and microcode source file -type t_rom is array (0 to 511) of std_logic_vector(31 downto 0); - -signal rom : t_rom := ( -"00000000000000000000000000000000", -- 000 -"00000000000001001000000001000100", -- 001 -"00000000000001000000000001000100", -- 002 -"10111101101001001000000001001101", -- 003 -"10110110101001000000000001001101", -- 004 -"00100000000000000000000000000000", -- 005 -"00000000000000000000000000000000", -- 006 -"11100100000000000000000000000000", -- 007 -"00000000101010000000000000000000", -- 008 -"00000100000100000000000001010111", -- 009 -"00001000000000000000110000011001", -- 00a -"00000100000100000000000001010111", -- 00b -"00000000101010000000000010010111", -- 00c -"00001000000000000000110000011100", -- 00d -"00001000000000000000110000011111", -- 00e -"00000100000100000000000001010111", -- 00f -"00001000000000000000110000011111", -- 010 -"00001000000000000000110000011100", -- 011 -"00001000000000000000110000011111", -- 012 -"00000000000110001000000001010111", -- 013 -"00001000000000000000110000011111", -- 014 -"00000100000110000000000001010111", -- 015 -"00001000000000000000110000101110", -- 016 -"00001000000000000000110000100010", -- 017 -"00000100000000111000000001010111", -- 018 -"00001000000000000000110000101110", -- 019 -"00000000101000111000000010010111", -- 01a -"00001000000000000000110000100101", -- 01b -"00001000000000000000110000101110", -- 01c -"10111101101001100000000001001101", -- 01d -"10110110101001101000000001001101", -- 01e -"00000000100000101000000001010111", -- 01f -"00001000000000000000110000100010", -- 020 -"00000100000000100000000001010111", -- 021 -"00001000000000000000110000101110", -- 022 -"00000000101000101000000010010111", -- 023 -"10111101101001100000000001001101", -- 024 -"10111010101001101000000001001101", -- 025 -"00000000101000100000000010010111", -- 026 -"00001000000000000000110000100101", -- 027 -"00001000000000000000110000101000", -- 028 -"00000100000000111000000001010111", -- 029 -"00000000101000111000000010010111", -- 02a -"00001000000000000000110000101011", -- 02b -"00000000101000010000000000000000", -- 02c -"00000000000001010000000001010111", -- 02d -"00000000101000011000000000000000", -- 02e -"00000000000001011000000001010111", -- 02f -"00000000101000100000000000000000", -- 030 -"00000000000000010000000001010111", -- 031 -"00000000101000101000000000000000", -- 032 -"00000000000000011000000001010111", -- 033 -"00000000101001010000000000000000", -- 034 -"00000000000000100000000001010111", -- 035 -"00000000101001011000000000000000", -- 036 -"00000100000000101000000001010111", -- 037 -"00001000000000000000110000011111", -- 038 -"00000100011000111000001101001100", -- 039 -"00001000000000000000110000011111", -- 03a -"00000100011000111000001101001101", -- 03b -"00001000000000000000110000011111", -- 03c -"00000100011000111000001101001110", -- 03d -"00001000000000000000110000011111", -- 03e -"00000100011000111000001101001111", -- 03f -"00001000000000000000110000011111", -- 040 -"00000100011000111000001101000100", -- 041 -"00001000000000000000110000011111", -- 042 -"00000100011000111000001101000101", -- 043 -"00001000000000000000110000011111", -- 044 -"00000100011000111000001101000110", -- 045 -"00001000000000000000110000011111", -- 046 -"00000100011000111000001110001110", -- 047 -"00000000101010000000000000000000", -- 048 -"00000100011000111000001101001100", -- 049 -"00000000101010000000000000000000", -- 04a -"00000100011000111000001101001101", -- 04b -"00000000101010000000000000000000", -- 04c -"00000100011000111000001101001110", -- 04d -"00000000101010000000000000000000", -- 04e -"00000100011000111000001101001111", -- 04f -"00000000101010000000000000000000", -- 050 -"00000100011000111000001101000100", -- 051 -"00000000101010000000000000000000", -- 052 -"00000100011000111000001101000101", -- 053 -"00000000101010000000000000000000", -- 054 -"00000100011000111000001101000110", -- 055 -"00000000101010000000000000000000", -- 056 -"00000100011000111000001110001110", -- 057 -"00001000000000000000110000011001", -- 058 -"00000100011000111000001101001100", -- 059 -"00001000000000000000110000011001", -- 05a -"00000100011000111000001101001101", -- 05b -"00001000000000000000110000011001", -- 05c -"00000100011000111000001101001110", -- 05d -"00001000000000000000110000011001", -- 05e -"00000100011000111000001101001111", -- 05f -"00001000000000000000110000011001", -- 060 -"00000100011000111000001101000100", -- 061 -"00001000000000000000110000011001", -- 062 -"00000100011000111000001101000101", -- 063 -"00001000000000000000110000011001", -- 064 -"00000100011000111000001101000110", -- 065 -"00001000000000000000110000011001", -- 066 -"00000100011000111000001110001110", -- 067 -"10111100101100000000001001001101", -- 068 -"00000100000000000000000000000000", -- 069 -"00001000000000000000110000011001", -- 06a -"10111100000000000000001010001101", -- 06b -"00001000000000000000110000011100", -- 06c -"10111100011100000000001001001111", -- 06d -"00000100000000000000000000000000", -- 06e -"00001000000000000000110000011001", -- 06f -"11000000000000000000000000000000", -- 070 -"10111100011001010000001010001111", -- 071 -"00001000000000000000110000011100", -- 072 -"10111100101110001000000001001101", -- 073 -"10100100101110000000000001001101", -- 074 -"10111100011110001000000001001111", -- 075 -"10100100011110000000000001001111", -- 076 -"00000000011110001000000000000000", -- 077 -"00000000101000101000000101001100", -- 078 -"00000000011110000000000000000000", -- 079 -"00000100101000100000000101001101", -- 07a -"00000000101000111000000010101000", -- 07b -"00000100101000111000001101101000", -- 07c -"00000100101000111000000101000000", -- 07d -"00000100101000111000000101000001", -- 07e -"00000100101000111000000101000010", -- 07f -"00000100101000111000000101000011", -- 080 -"00000100101000111000000001000111", -- 081 -"00000100000000000000000100101100", -- 082 -"00000100000000000000000100101101", -- 083 -"00001000000000000000110000101110", -- 084 -"00000000101001100000000000000000", -- 085 -"00000000000001001000000001010111", -- 086 -"00000000101001101000000000000000", -- 087 -"00000100000001000000000001010111", -- 088 -"00000100000000000000000000000000", -- 089 -"00001000000000000000110000101110", -- 08a -"00010000000000000000100000000101", -- 08b -"00001000000000000000110000101110", -- 08c -"11000000101001000000000010010111", -- 08d -"00001000000000000000110000110100", -- 08e -"11000000101001001000000010010111", -- 08f -"00001000000000000000110000110100", -- 090 -"00000000101001100000000000000000", -- 091 -"00000000000001001000000001010111", -- 092 -"00000000101001101000000000000000", -- 093 -"00000100000001000000000001010111", -- 094 -"00001000000000000000110000101110", -- 095 -"00010000000000000000100000001101", -- 096 -"00001000000000000000110000111001", -- 097 -"00000000000001001000000001010111", -- 098 -"00001000000000000000110000111001", -- 099 -"00000100000001000000000001010111", -- 09a -"00010000000000000000100000010111", -- 09b -"11000000101001000000000010010111", -- 09c -"00001000000000000000110000110100", -- 09d -"11000000101001001000000010010111", -- 09e -"00001000000000000000110000110100", -- 09f -"11000000000001001000000001011111", -- 0a0 -"00000100000001000000000001000100", -- 0a1 -"00000000101000101000000000000000", -- 0a2 -"00000000000001001000000001010111", -- 0a3 -"00000000101000100000000000000000", -- 0a4 -"00000100000001000000000001010111", -- 0a5 -"11000000101110000000000010010111", -- 0a6 -"00001000000000000000110000110100", -- 0a7 -"11000000101110001000000010010111", -- 0a8 -"00001000000000000000110000110100", -- 0a9 -"00000100000000000000000000000000", -- 0aa -"11000000101000111000000010010111", -- 0ab -"00001000000000000000110000110100", -- 0ac -"11000000000000000000000010110000", -- 0ad -"00001000000000000000110000110100", -- 0ae -"00000100000000000000000000000000", -- 0af -"00001000000000000000110000111001", -- 0b0 -"00000000000110001000000001010111", -- 0b1 -"00001000000000000000110000111001", -- 0b2 -"00000100000110000000000001010111", -- 0b3 -"00001000000000000000110000111001", -- 0b4 -"00000000000000110000001101010111", -- 0b5 -"00001000000000000000110000111001", -- 0b6 -"00000100000000111000000001010111", -- 0b7 -"00001000000000000000110000111001", -- 0b8 -"00000000000001100000000001010111", -- 0b9 -"00001000000000000000110000111001", -- 0ba -"00000000000001101000000001010111", -- 0bb -"11000000101000100000000010010111", -- 0bc -"00001000000000000000110000110100", -- 0bd -"11000000101000101000000010010111", -- 0be -"00001000000000000000110000110100", -- 0bf -"00000000101001100000000000000000", -- 0c0 -"00000000000000101000000001010111", -- 0c1 -"00000000101001101000000000000000", -- 0c2 -"00000100000000100000000001010111", -- 0c3 -"00000000101000101000000000000000", -- 0c4 -"00000000000001111000000001010111", -- 0c5 -"00000000101000100000000000000000", -- 0c6 -"00000100000001110000000001010111", -- 0c7 -"01100100000000000000000000000000", -- 0c8 -"01000100000000000000000000000000", -- 0c9 -"00000000000001101000000001010111", -- 0ca -"00001000000000000000110000011111", -- 0cb -"00000000000001100000000001010111", -- 0cc -"00000000000000000000000000000000", -- 0cd -"00000001101001100000000000000000", -- 0ce -"10010110101001101000000000000000", -- 0cf -"00000100100000111000000001010111", -- 0d0 -"00000000000001101000000001010111", -- 0d1 -"00001000000000000000110000011111", -- 0d2 -"00000000000001100000000001010111", -- 0d3 -"00000000101000111000000010010111", -- 0d4 -"00000001101001100000000000000000", -- 0d5 -"10011010101001101000000000000000", -- 0d6 -"00000100000000000000000000000000", -- 0d7 -"11100100000000000000000000000000", -- 0d8 -"00000001101000101000000000000000", -- 0d9 -"00010110101000100000000000000000", -- 0da -"00001100100001010000000001010111", -- 0db -"00000001101000101000000000000000", -- 0dc -"00011010101000100000000000000000", -- 0dd -"00000100000000000000000000000000", -- 0de -"10111101101001001000000001001101", -- 0df -"10110110101001000000000001001101", -- 0e0 -"00001100100000000000000010010111", -- 0e1 -"00000001101001100000000000000000", -- 0e2 -"00010110101001101000000000000000", -- 0e3 -"00001100100000000000000000000000", -- 0e4 -"00000001101001100000000000000000", -- 0e5 -"00011010101001101000000000000000", -- 0e6 -"00000100000000000000000000000000", -- 0e7 -"00000001101110001000000000000000", -- 0e8 -"00010110101110000000000000000000", -- 0e9 -"00001100100000000000000000000000", -- 0ea -"00000001101110001000000000000000", -- 0eb -"00011010101110000000000000000000", -- 0ec -"00000100000000000000000000000000", -- 0ed -"10111101101001001000000001001101", -- 0ee -"10110110101001000000000001001101", -- 0ef -"00000000100001100000000001010111", -- 0f0 -"10111101101001001000000001001101", -- 0f1 -"10110110101001000000000001001101", -- 0f2 -"00001100100001101000000001010111", -- 0f3 -"10111100011001111000000001001111", -- 0f4 -"10100000011001110000000001001111", -- 0f5 -"00000001101001111000000000000000", -- 0f6 -"00011010101001110000000000000000", -- 0f7 -"00001100000000000000000000000000", -- 0f8 -"10111101101001111000000001001101", -- 0f9 -"10110110101001110000000001001101", -- 0fa -"00001100100000000000000000000000", -- 0fb -"00000100000000000000000000000000", -- 0fc -"00000100000000000000000000000000", -- 0fd -"00000100000000000000000000000000", -- 0fe -"00000100000000000000000000000000", -- 0ff -"00001000000000000000100000001001", -- 100 -"00001000000000000000000000010010", -- 101 -"00001000000000000000000000101010", -- 102 -"00001000000000000000010000110011", -- 103 -"00001000000000000000010000101000", -- 104 -"00001000000000000000010000101101", -- 105 -"00001000000000000000000000001110", -- 106 -"00001000000000000000010000111101", -- 107 -"00001000000000000000000000000000", -- 108 -"00001000000000000000010000110111", -- 109 -"00001000000000000000000000101000", -- 10a -"00001000000000000000010000110101", -- 10b -"00001000000000000000010000101000", -- 10c -"00001000000000000000010000101101", -- 10d -"00001000000000000000000000001110", -- 10e -"00001000000000000000010000111110", -- 10f -"00001000000000000000000000000000", -- 110 -"00001000000000000000000000010010", -- 111 -"00001000000000000000000000101010", -- 112 -"00001000000000000000010000110011", -- 113 -"00001000000000000000010000101000", -- 114 -"00001000000000000000010000101101", -- 115 -"00001000000000000000000000001110", -- 116 -"00001000000000000000010000111111", -- 117 -"00001000000000000000000000000000", -- 118 -"00001000000000000000010000110111", -- 119 -"00001000000000000000000000101000", -- 11a -"00001000000000000000010000110101", -- 11b -"00001000000000000000010000101000", -- 11c -"00001000000000000000010000101101", -- 11d -"00001000000000000000000000001110", -- 11e -"00001000000000000000100000000000", -- 11f -"00001000000000000000000000000000", -- 120 -"00001000000000000000000000010010", -- 121 -"00001000000000000000000000100010", -- 122 -"00001000000000000000010000110011", -- 123 -"00001000000000000000010000101000", -- 124 -"00001000000000000000010000101101", -- 125 -"00001000000000000000000000001110", -- 126 -"00001000000000000000010000111011", -- 127 -"00001000000000000000000000000000", -- 128 -"00001000000000000000010000110111", -- 129 -"00001000000000000000000000011100", -- 12a -"00001000000000000000010000110101", -- 12b -"00001000000000000000010000101000", -- 12c -"00001000000000000000010000101101", -- 12d -"00001000000000000000000000001110", -- 12e -"00001000000000000000100000000001", -- 12f -"00001000000000000000000000000000", -- 130 -"00001000000000000000000000010010", -- 131 -"00001000000000000000000000011001", -- 132 -"00001000000000000000010000110011", -- 133 -"00001000000000000000010000101010", -- 134 -"00001000000000000000010000101111", -- 135 -"00001000000000000000000000010000", -- 136 -"00001000000000000000100000000011", -- 137 -"00001000000000000000000000000000", -- 138 -"00001000000000000000010000110111", -- 139 -"00001000000000000000000000010110", -- 13a -"00001000000000000000010000110101", -- 13b -"00001000000000000000010000101000", -- 13c -"00001000000000000000010000101101", -- 13d -"00001000000000000000000000001110", -- 13e -"00001000000000000000100000000010", -- 13f -"00001000000000000000000000001000", -- 140 -"00001000000000000000000000001000", -- 141 -"00001000000000000000000000001000", -- 142 -"00001000000000000000000000001000", -- 143 -"00001000000000000000000000001000", -- 144 -"00001000000000000000000000001000", -- 145 -"00001000000000000000000000001010", -- 146 -"00001000000000000000000000001000", -- 147 -"00001000000000000000000000001000", -- 148 -"00001000000000000000000000001000", -- 149 -"00001000000000000000000000001000", -- 14a -"00001000000000000000000000001000", -- 14b -"00001000000000000000000000001000", -- 14c -"00001000000000000000000000001000", -- 14d -"00001000000000000000000000001010", -- 14e -"00001000000000000000000000001000", -- 14f -"00001000000000000000000000001000", -- 150 -"00001000000000000000000000001000", -- 151 -"00001000000000000000000000001000", -- 152 -"00001000000000000000000000001000", -- 153 -"00001000000000000000000000001000", -- 154 -"00001000000000000000000000001000", -- 155 -"00001000000000000000000000001010", -- 156 -"00001000000000000000000000001000", -- 157 -"00001000000000000000000000001000", -- 158 -"00001000000000000000000000001000", -- 159 -"00001000000000000000000000001000", -- 15a -"00001000000000000000000000001000", -- 15b -"00001000000000000000000000001000", -- 15c -"00001000000000000000000000001000", -- 15d -"00001000000000000000000000001010", -- 15e -"00001000000000000000000000001000", -- 15f -"00001000000000000000000000001000", -- 160 -"00001000000000000000000000001000", -- 161 -"00001000000000000000000000001000", -- 162 -"00001000000000000000000000001000", -- 163 -"00001000000000000000000000001000", -- 164 -"00001000000000000000000000001000", -- 165 -"00001000000000000000000000001010", -- 166 -"00001000000000000000000000001000", -- 167 -"00001000000000000000000000001000", -- 168 -"00001000000000000000000000001000", -- 169 -"00001000000000000000000000001000", -- 16a -"00001000000000000000000000001000", -- 16b -"00001000000000000000000000001000", -- 16c -"00001000000000000000000000001000", -- 16d -"00001000000000000000000000001010", -- 16e -"00001000000000000000000000001000", -- 16f -"00001000000000000000000000001100", -- 170 -"00001000000000000000000000001100", -- 171 -"00001000000000000000000000001100", -- 172 -"00001000000000000000000000001100", -- 173 -"00001000000000000000000000001100", -- 174 -"00001000000000000000000000001100", -- 175 -"00001000000000000000110000011000", -- 176 -"00001000000000000000000000001100", -- 177 -"00001000000000000000000000001000", -- 178 -"00001000000000000000000000001000", -- 179 -"00001000000000000000000000001000", -- 17a -"00001000000000000000000000001000", -- 17b -"00001000000000000000000000001000", -- 17c -"00001000000000000000000000001000", -- 17d -"00001000000000000000000000001010", -- 17e -"00001000000000000000000000001000", -- 17f -"00001000000000000000010000001000", -- 180 -"00001000000000000000010000001000", -- 181 -"00001000000000000000010000001000", -- 182 -"00001000000000000000010000001000", -- 183 -"00001000000000000000010000001000", -- 184 -"00001000000000000000010000001000", -- 185 -"00001000000000000000010000011000", -- 186 -"00001000000000000000010000001000", -- 187 -"00001000000000000000010000001010", -- 188 -"00001000000000000000010000001010", -- 189 -"00001000000000000000010000001010", -- 18a -"00001000000000000000010000001010", -- 18b -"00001000000000000000010000001010", -- 18c -"00001000000000000000010000001010", -- 18d -"00001000000000000000010000011010", -- 18e -"00001000000000000000010000001010", -- 18f -"00001000000000000000010000001100", -- 190 -"00001000000000000000010000001100", -- 191 -"00001000000000000000010000001100", -- 192 -"00001000000000000000010000001100", -- 193 -"00001000000000000000010000001100", -- 194 -"00001000000000000000010000001100", -- 195 -"00001000000000000000010000011100", -- 196 -"00001000000000000000010000001100", -- 197 -"00001000000000000000010000001110", -- 198 -"00001000000000000000010000001110", -- 199 -"00001000000000000000010000001110", -- 19a -"00001000000000000000010000001110", -- 19b -"00001000000000000000010000001110", -- 19c -"00001000000000000000010000001110", -- 19d -"00001000000000000000010000011110", -- 19e -"00001000000000000000010000001110", -- 19f -"00001000000000000000010000010000", -- 1a0 -"00001000000000000000010000010000", -- 1a1 -"00001000000000000000010000010000", -- 1a2 -"00001000000000000000010000010000", -- 1a3 -"00001000000000000000010000010000", -- 1a4 -"00001000000000000000010000010000", -- 1a5 -"00001000000000000000010000100000", -- 1a6 -"00001000000000000000010000010000", -- 1a7 -"00001000000000000000010000010010", -- 1a8 -"00001000000000000000010000010010", -- 1a9 -"00001000000000000000010000010010", -- 1aa -"00001000000000000000010000010010", -- 1ab -"00001000000000000000010000010010", -- 1ac -"00001000000000000000010000010010", -- 1ad -"00001000000000000000010000100010", -- 1ae -"00001000000000000000010000010010", -- 1af -"00001000000000000000010000010100", -- 1b0 -"00001000000000000000010000010100", -- 1b1 -"00001000000000000000010000010100", -- 1b2 -"00001000000000000000010000010100", -- 1b3 -"00001000000000000000010000010100", -- 1b4 -"00001000000000000000010000010100", -- 1b5 -"00001000000000000000010000100100", -- 1b6 -"00001000000000000000010000010100", -- 1b7 -"00001000000000000000010000010110", -- 1b8 -"00001000000000000000010000010110", -- 1b9 -"00001000000000000000010000010110", -- 1ba -"00001000000000000000010000010110", -- 1bb -"00001000000000000000010000010110", -- 1bc -"00001000000000000000010000010110", -- 1bd -"00001000000000000000010000100110", -- 1be -"00001000000000000000010000010110", -- 1bf -"00001000000000000000100000011011", -- 1c0 -"00001000000000000000100000110000", -- 1c1 -"00001000000000000000100000001010", -- 1c2 -"00001000000000000000100000000100", -- 1c3 -"00001000000000000000100000010101", -- 1c4 -"00001000000000000000100000100110", -- 1c5 -"00001000000000000000000000111000", -- 1c6 -"00001000000000000000100000011100", -- 1c7 -"00001000000000000000100000011011", -- 1c8 -"00001000000000000000100000010111", -- 1c9 -"00001000000000000000100000001010", -- 1ca -"00001000000000000000000000000000", -- 1cb -"00001000000000000000100000010101", -- 1cc -"00001000000000000000100000001100", -- 1cd -"00001000000000000000000000111010", -- 1ce -"00001000000000000000100000011100", -- 1cf -"00001000000000000000100000011011", -- 1d0 -"00001000000000000000100000110000", -- 1d1 -"00001000000000000000100000001010", -- 1d2 -"00001000000000000000110000010001", -- 1d3 -"00001000000000000000100000010101", -- 1d4 -"00001000000000000000100000100110", -- 1d5 -"00001000000000000000000000111100", -- 1d6 -"00001000000000000000100000011100", -- 1d7 -"00001000000000000000100000011011", -- 1d8 -"00001000000000000000000000000000", -- 1d9 -"00001000000000000000100000001010", -- 1da -"00001000000000000000110000001010", -- 1db -"00001000000000000000100000010101", -- 1dc -"00001000000000000000000000000000", -- 1dd -"00001000000000000000000000111110", -- 1de -"00001000000000000000100000011100", -- 1df -"00001000000000000000100000011011", -- 1e0 -"00001000000000000000100000110000", -- 1e1 -"00001000000000000000100000001010", -- 1e2 -"00001000000000000000100000111000", -- 1e3 -"00001000000000000000100000010101", -- 1e4 -"00001000000000000000100000100110", -- 1e5 -"00001000000000000000010000000000", -- 1e6 -"00001000000000000000100000011100", -- 1e7 -"00001000000000000000100000011011", -- 1e8 -"00001000000000000000100000100010", -- 1e9 -"00001000000000000000100000001010", -- 1ea -"00001000000000000000000000101100", -- 1eb -"00001000000000000000100000010101", -- 1ec -"00001000000000000000000000000000", -- 1ed -"00001000000000000000010000000010", -- 1ee -"00001000000000000000100000011100", -- 1ef -"00001000000000000000100000011011", -- 1f0 -"00001000000000000000100000110100", -- 1f1 -"00001000000000000000100000001010", -- 1f2 -"00001000000000000000110000001001", -- 1f3 -"00001000000000000000100000010101", -- 1f4 -"00001000000000000000100000101011", -- 1f5 -"00001000000000000000010000000100", -- 1f6 -"00001000000000000000100000011100", -- 1f7 -"00001000000000000000100000011011", -- 1f8 -"00001000000000000000110000000100", -- 1f9 -"00001000000000000000100000001010", -- 1fa -"00001000000000000000110000001000", -- 1fb -"00001000000000000000100000010101", -- 1fc -"00001000000000000000000000000000", -- 1fd -"00001000000000000000010000000110", -- 1fe -"00001000000000000000100000011100" -- 1ff - -); - --- end of microcode ROM - -signal load_al : std_logic; -- uinst field, load AL reg from rbank -signal load_addr : std_logic; -- uinst field, enable external addr reg load -signal load_t1 : std_logic; -- uinst field, load reg T1 -signal load_t2 : std_logic; -- uinst field, load reg T2 -signal mux_in : std_logic; -- uinst field, T1/T2 input data selection -signal load_do : std_logic; -- uinst field, pipelined, load DO reg --- rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field) -signal rb_addr_sel : std_logic_vector(1 downto 0); --- ra_field: uinst field, explicit reg bank address -signal ra_field : std_logic_vector(3 downto 0); -signal rbank_data : std_logic_vector(7 downto 0); -- rbank output -signal alu_output : std_logic_vector(7 downto 0); -- ALU output --- data_output: datapath output: ALU output vs. F reg -signal data_output : std_logic_vector(7 downto 0); -signal T1 : std_logic_vector(7 downto 0); -- T1 reg (ALU operand) -signal T2 : std_logic_vector(7 downto 0); -- T2 reg (ALU operand) --- alu_input: data loaded into T1, T2: rbank data vs. DI -signal alu_input : std_logic_vector(7 downto 0); -signal we_rb : std_logic; -- uinst field, commands a write to the rbank -signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA) -signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr -signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr -signal DO : std_logic_vector(7 downto 0); -- data output reg - --- Register bank as an array of 16 bytes (asynch. LUT ram) -type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0); --- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP] -signal rbank : t_reg_bank; - -signal flag_reg : std_logic_vector(7 downto 0); -- F register --- flag_pattern: uinst field, F update pattern: which flags are updated -signal flag_pattern : std_logic_vector(1 downto 0); -signal flag_s : std_logic; -- new computed S flag -signal flag_z : std_logic; -- new computed Z flag -signal flag_p : std_logic; -- new computed P flag -signal flag_cy : std_logic; -- new computed C flag -signal flag_cy_1 : std_logic; -- C flag computed from arith/logic operation -signal flag_cy_2 : std_logic; -- C flag computed from CPC circuit -signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.) -signal do_cy_op_d : std_logic; -- do_cy_op, pipelined -signal do_cpc : std_logic; -- ALU operation is CPC -signal do_cpc_d : std_logic; -- do_cpc, pipelined -signal do_daa : std_logic; -- ALU operation is DAA -signal flag_ac : std_logic; -- new computed half carry flag --- flag_aux_cy: new computed half carry flag (used in 16-bit ops) -signal flag_aux_cy : std_logic; -signal load_psw : std_logic; -- load F register - --- aux carry computation and control signals -signal use_aux : std_logic; -- decoded from flags in 1st phase -signal use_aux_cy : std_logic; -- 2nd phase signal -signal reg_aux_cy : std_logic; -signal aux_cy_in : std_logic; -signal set_aux_cy : std_logic; -signal set_aux : std_logic; - --- ALU control signals -- together they select ALU operation -signal alu_fn : std_logic_vector(1 downto 0); -signal use_logic : std_logic; -- logic/arith mux control -signal mux_fn : std_logic_vector(1 downto 0); -signal use_psw : std_logic; -- ALU/F mux control - --- ALU arithmetic operands and result -signal arith_op1 : std_logic_vector(8 downto 0); -signal arith_op2 : std_logic_vector(8 downto 0); -signal arith_op2_sgn: std_logic_vector(8 downto 0); -signal arith_res : std_logic_vector(8 downto 0); -signal arith_res8 : std_logic_vector(7 downto 0); - --- ALU DAA intermediate signals (DAA has fully dedicated logic) -signal daa_res : std_logic_vector(8 downto 0); -signal daa_res8 : std_logic_vector(7 downto 0); -signal daa_res9 : std_logic_vector(8 downto 0); -signal daa_test1 : std_logic; -signal daa_test1a : std_logic; -signal daa_test2 : std_logic; -signal daa_test2a : std_logic; -signal arith_daa_res :std_logic_vector(7 downto 0); -signal cy_daa : std_logic; - --- ALU CY flag intermediate signals -signal cy_in_sgn : std_logic; -signal cy_in : std_logic; -signal cy_in_gated : std_logic; -signal cy_adder : std_logic; -signal cy_arith : std_logic; -signal cy_shifter : std_logic; - --- ALU intermediate results -signal logic_res : std_logic_vector(7 downto 0); -signal shift_res : std_logic_vector(7 downto 0); -signal alu_mux1 : std_logic_vector(7 downto 0); - -begin - -DI <= data_in; - -process(clk) -- IR register, load when uc_decode flag activates -begin - if clk'event and clk='1' then - if uc_decode = '1' then - IR <= DI; - end if; - end if; -end process; - -s_field <= IR(2 downto 0); -- IR field extraction : sss reg code -d_field <= IR(5 downto 3); -- ddd reg code -p_field <= IR(5 downto 4); -- pp 16-bit reg pair code - - ---############################################################################## --- Microcode sequencer - -process(clk) -- do_reset is reset delayed 1 cycle -begin - if clk'event and clk='1' then - do_reset <= reset; - end if; -end process; - -uc_flags1 <= ucode(31 downto 29); -uc_flags2 <= ucode(28 downto 26); - --- microcode address control flags are gated by do_reset (reset has priority) -uc_do_ret <= '1' when uc_flags2 = "011" and do_reset = '0' else '0'; -uc_jsr <= '1' when uc_flags2 = "010" and do_reset = '0' else '0'; -uc_tjsr <= '1' when uc_flags2 = "100" and do_reset = '0' else '0'; -uc_decode <= '1' when uc_flags1 = "001" and do_reset = '0' else '0'; -uc_end <= '1' when (uc_flags2 = "001" or (uc_tjsr='1' and condition_reg='0')) - and do_reset = '0' else '0'; - --- other microinstruction flags are decoded -uc_halt_flag <= '1' when uc_flags1 = "111" else '0'; -uc_halt <= '1' when uc_halt_flag='1' and inta_reg='0' else '0'; -uc_ei <= '1' when uc_flags1 = "011" else '0'; -uc_di <= '1' when uc_flags1 = "010" or inta_reg='1' else '0'; --- clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly --- at the end of each instruction (by uc_decode) -clr_t2 <= '1' when uc_flags2 = "001" else '0'; -clr_t1 <= '1' when uc_flags1 = "110" else '0'; -use_aux <= '1' when uc_flags1 = "101" else '0'; -set_aux <= '1' when uc_flags2 = "111" else '0'; - -load_al <= ucode(24); -load_addr <= ucode(25); - -do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op -do_cpc_d <= ucode(0); -- decode CPC ALU op - --- uinst jump command, either unconditional or on a given condition -uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg); - -vma <= load_addr; -- addr is valid, either for memmory or io - --- assume the only uinst that does memory access in the range 0..f is 'fetch' -fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0'; - --- external bus interface control signals -io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory) -rd <= '1' when uc_flags2="101" else '0'; -- RD access -wr <= '1' when uc_flags2="110" else '0'; -- WR access - -uc_jmp_addr <= ucode(11 downto 10) & ucode(5 downto 0); - -uc_addr_sel <= uc_do_ret & uc_do_jmp & uc_decode & uc_end; - -addr_plus_1 <= uc_addr + 1; - --- TODO simplify this!! - --- NOTE: when end='1' we jump either to the FETCH ucode ot to the HALT ucode --- depending on the value of the halt signal. --- We use the unregistered uc_halt instead of halt_reg because otherwise #end --- should be on the cycle following #halt, wasting a cycle. --- This means that the flag #halt has to be used with #end or will be ignored. - -with uc_addr_sel select - next_uc_addr <= '0'&uc_ret_addr when "1000", -- ret - '0'&uc_jmp_addr when "0100", -- jsr/tjsr - '0'&addr_plus_1 when "0000", -- uaddr++ - "000000"&uc_halt&"11" - when "0001", -- end: go to fetch/halt uaddr - '1'&DI when others; -- decode fetched address - --- Note how we used DI (containing instruction opcode) as a microcode address - --- read microcode rom -process (clk) -begin - if clk'event and clk='1' then - ucode <= rom(conv_integer(next_uc_addr)); - end if; -end process; - --- microcode address register -process (clk) -begin - if clk'event and clk='1' then - if reset = '1' then - uc_addr <= X"00"; - else - uc_addr <= next_uc_addr(7 downto 0); - end if; - end if; -end process; - --- ucode address 1-level 'return stack' -process (clk) -begin - if clk'event and clk='1' then - if reset = '1' then - uc_ret_addr <= X"00"; - elsif uc_do_jmp='1' then - uc_ret_addr <= addr_plus_1; - end if; - end if; -end process; - - -alu_op <= ucode(3 downto 0); - --- pipeline uinst field2 for 1-cycle delayed execution. --- note the same rbank addr field is used in cycles 1 and 2; this enforces --- some constraints on uinst programming but simplifies the system. -process(clk) -begin - if clk'event and clk='1' then - ucode_field2 <= do_cy_op_d & do_cpc_d & clr_t2 & clr_t1 & - set_aux & use_aux & rbank_rd_addr & - ucode(14 downto 4) & alu_op; - end if; -end process; - ---#### HALT logic -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' or int_pending = '1' then --inta_reg - halt_reg <= '0'; - else - if uc_halt = '1' then - halt_reg <= '1'; - end if; - end if; - end if; -end process; - -halt <= halt_reg; - ---#### INTE logic -- inte_reg = '1' means interrupts ENABLED -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' then - inte_reg <= '0'; - else - if uc_di='1' or uc_ei='1' then - inte_reg <= uc_ei; - end if; - end if; - end if; -end process; - -inte <= inte_reg; - --- interrupts are ignored when inte='0' -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' then - int_pending <= '0'; - else - if intr = '1' and inte_reg = '1' and int_pending = '0' then - int_pending <= '1'; - else - if inte_reg = '1' and uc_end='1' then - int_pending <= '0'; - end if; - end if; - end if; - end if; -end process; - - ---#### INTA logic --- INTA goes high from END to END, that is for the entire time the instruction --- takes to fetch and execute; in the original 8080 it was asserted only for --- the M1 cycle. --- All instructions can be used in an inta cycle, including XTHL which was --- forbidden in the original 8080. --- It's up to you figuring out which cycle is which in multibyte instructions. -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' then - inta_reg <= '0'; - else - if int_pending = '1' and uc_end='1' then - -- enter INTA state - inta_reg <= '1'; - else - -- exit INTA state - -- NOTE: don't reset inta when exiting halt state (uc_halt_flag='1'). - -- If we omit this condition, when intr happens on halt state, inta - -- will only last for 1 cycle, because in halt state uc_end is - -- always asserted. - if uc_end = '1' and uc_halt_flag='0' then - inta_reg <= '0'; - end if; - end if; - end if; - end if; -end process; - -inta <= inta_reg; - - ---############################################################################## --- Datapath - --- extract pipelined microcode fields -ra_field <= ucode(18 downto 15); -load_t1 <= ucode(23); -load_t2 <= ucode(22); -mux_in <= ucode(21); -rb_addr_sel <= ucode(20 downto 19); -load_do <= ucode_field2(7); -set_aux_cy <= ucode_field2(20); -do_clr_t1 <= ucode_field2(21); -do_clr_t2 <= ucode_field2(22); - - --- T1 register -process (clk) -begin - if clk'event and clk='1' then - if reset = '1' or uc_decode = '1' or do_clr_t1='1' then - T1 <= X"00"; - else - if load_t1 = '1' then - T1 <= alu_input; - end if; - end if; - end if; -end process; - --- T2 register -process (clk) -begin - if clk'event and clk='1' then - if reset = '1' or uc_decode = '1' or do_clr_t2='1' then - T2 <= X"00"; - else - if load_t2 = '1' then - T2 <= alu_input; - end if; - end if; - end if; -end process; - --- T1/T2 input data mux -alu_input <= rbank_data when mux_in = '1' else DI; - --- register bank address mux logic - -rbh <= '1' when p_field = "11" else '0'; - -with rb_addr_sel select - rbank_rd_addr <= ra_field when "00", - "0"&s_field when "01", - "0"&d_field when "10", - rbh&p_field&ra_field(0) when others; - --- RBank writes are inhibited in INTA state, but only for PC increments. -inhibit_pc_increment <= '1' when inta_reg='1' and use_aux_cy='1' - and rbank_wr_addr(3 downto 1) = "100" - else '0'; -we_rb <= ucode_field2(6) and not inhibit_pc_increment; - --- Register bank logic --- NOTE: read is asynchronous, while write is synchronous; but note also --- that write phase for a given uinst happens the cycle after the read phase. --- This way we give the ALU time to do its job. -rbank_wr_addr <= ucode_field2(18 downto 15); -process(clk) -begin - if clk'event and clk='1' then - if we_rb = '1' then - rbank(conv_integer(rbank_wr_addr)) <= alu_output; - end if; - end if; -end process; -rbank_data <= rbank(conv_integer(rbank_rd_addr)); - --- should we read F register or ALU output? -use_psw <= '1' when ucode_field2(5 downto 4)="11" else '0'; -data_output <= flag_reg when use_psw = '1' else alu_output; - - -process (clk) -begin - if clk'event and clk='1' then - if load_do = '1' then - DO <= data_output; - end if; - end if; -end process; - ---############################################################################## --- ALU - -alu_fn <= ucode_field2(1 downto 0); -use_logic <= ucode_field2(2); -mux_fn <= ucode_field2(4 downto 3); ---#### make sure this is "00" in the microcode when no F updates should happen! -flag_pattern <= ucode_field2(9 downto 8); -use_aux_cy <= ucode_field2(19); -do_cpc <= ucode_field2(23); -do_cy_op <= ucode_field2(24); -do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0'; - -aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1'; - --- carry input selection: normal or aux (for 16 bit increments)? -cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in; - --- carry is not used (0) in add/sub operations -cy_in_gated <= cy_in and alu_fn(0); - ---##### Adder/substractor - --- zero extend adder operands to 9 bits to ease CY output synthesis --- use zero extension because we're only interested in cy from 7 to 8 -arith_op1 <= '0' & T2; -arith_op2 <= '0' & T1; - --- The adder/substractor is done in 2 stages to help XSL synth it properly --- Other codings result in 1 adder + a substractor + 1 mux - --- do 2nd op 2's complement if substracting... -arith_op2_sgn <= arith_op2 when alu_fn(1) = '0' else not arith_op2; --- ...and complement cy input too -cy_in_sgn <= cy_in_gated when alu_fn(1) = '0' else not cy_in_gated; - --- once 2nd operand has been negated (or not) add operands normally -arith_res <= arith_op1 + arith_op2_sgn + cy_in_sgn; - --- take only 8 bits; 9th bit of adder is cy output -arith_res8 <= arith_res(7 downto 0); -cy_adder <= arith_res(8); - ---##### DAA dedicated logic --- Note a DAA takes 2 cycles to complete! - ---daa_test1a='1' when daa_res9(7 downto 4) > 0x06 -daa_test1a <= arith_op2(3) and (arith_op2(2) or arith_op2(1) or arith_op2(0)); -daa_test1 <= '1' when flag_reg(4)='1' or daa_test1a='1' else '0'; - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - daa_res9 <= "000000000"; - else - if daa_test1='1' then - daa_res9 <= arith_op2 + "000000110"; - else - daa_res9 <= arith_op2; - end if; - end if; - end if; -end process; - ---daa_test2a='1' when daa_res9(7 downto 4) > 0x06 FIXME unused? -daa_test2a <= daa_res9(7) and (daa_res9(6) or daa_res9(5) or daa_res9(4)); -daa_test2 <= '1' when flag_reg(0)='1' or daa_test1a='1' else '0'; - -daa_res <= '0'&daa_res9(7 downto 0) + "01100000" when daa_test2='1' - else daa_res9; - -cy_daa <= daa_res(8); - --- DAA vs. adder mux -arith_daa_res <= daa_res(7 downto 0) when do_daa='1' else arith_res8; - --- DAA vs. adder CY mux -cy_arith <= cy_daa when do_daa='1' else cy_adder; - ---##### Logic operations block -logic_res <= T1 and T2 when alu_fn = "00" else - T1 xor T2 when alu_fn = "01" else - T1 or T2 when alu_fn = "10" else - not T1; - ---##### Shifter -shifter: -for i in 1 to 6 generate -begin - shift_res(i) <= T1(i-1) when alu_fn(0) = '0' else T1(i+1); -end generate; -shift_res(0) <= T1(7) when alu_fn = "00" else -- rot left - cy_in when alu_fn = "10" else -- rot left through carry - T1(1); -- rot right -shift_res(7) <= T1(0) when alu_fn = "01" else -- rot right - cy_in when alu_fn = "11" else -- rot right through carry - T1(6); -- rot left - -cy_shifter <= T1(7) when alu_fn(0) = '0' else -- left - T1(0); -- right - -alu_mux1 <= logic_res when use_logic = '1' else shift_res; - - -with mux_fn select - alu_output <= alu_mux1 when "00", - arith_daa_res when "01", - not alu_mux1 when "10", - "00"&d_field&"000" when others; -- RST - ---###### flag computation - -flag_s <= alu_output(7); -flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor - alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0)); -flag_z <= '1' when alu_output=X"00" else '0'; -flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4)); - -flag_cy_1 <= cy_arith when use_logic = '1' else cy_shifter; -flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc -flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2; - -flag_aux_cy <= cy_adder; - --- auxiliary carry reg -process(clk) -begin - if clk'event and clk='1' then - if reset='1' or uc_decode = '1' then - reg_aux_cy <= '1'; -- inits to 0 every instruction - else - reg_aux_cy <= flag_aux_cy; - end if; - end if; -end process; - --- load PSW from ALU (i.e. POP AF) or from flag signals -load_psw <= '1' when we_rb='1' and rbank_wr_addr="0110" else '0'; - --- The F register has been split in two separate groupt that always update --- together (C and all others). - --- F register, flags S,Z,AC,P -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - flag_reg(7) <= '0'; - flag_reg(6) <= '0'; - flag_reg(4) <= '0'; - flag_reg(2) <= '0'; - elsif flag_pattern(1) = '1' then - if load_psw = '1' then - flag_reg(7) <= alu_output(7); - flag_reg(6) <= alu_output(6); - flag_reg(4) <= alu_output(4); - flag_reg(2) <= alu_output(2); - else - flag_reg(7) <= flag_s; - flag_reg(6) <= flag_z; - flag_reg(4) <= flag_ac; - flag_reg(2) <= flag_p; - end if; - end if; - end if; -end procesS; - --- F register, flag C -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' then - flag_reg(0) <= '0'; - elsif flag_pattern(0) = '1' then - if load_psw = '1' then - flag_reg(0) <= alu_output(0); - else - flag_reg(0) <= flag_cy; - end if; - end if; - end if; -end procesS; - -flag_reg(5) <= '0'; -- constant flag -flag_reg(3) <= '0'; -- constant flag -flag_reg(1) <= '1'; -- constant flag - ---##### Condition computation - -condition_sel <= d_field(2 downto 0); -with condition_sel select - condition <= - not flag_reg(6) when "000", -- NZ - flag_reg(6) when "001", -- Z - not flag_reg(0) when "010", -- NC - flag_reg(0) when "011", -- C - not flag_reg(2) when "100", -- PO - flag_reg(2) when "101", -- PE - not flag_reg(7) when "110", -- P - flag_reg(7) when others;-- M - - --- condition is registered to shorten the delay path; the extra 1-cycle --- delay is not relevant because conditions are tested in the next instruction --- at the earliest, and there's at least the fetch uinsts intervening. -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' then - condition_reg <= '0'; - else - condition_reg <= condition; - end if; - end if; -end process; - --- low byte address register -process(clk) -begin - if clk'event and clk='1' then - if reset = '1' then - addr_low <= X"00"; - elsif load_al = '1' then - addr_low <= rbank_data; - end if; - end if; -end process; - --- note external address registers (high byte) are loaded directly from rbank -addr_out <= rbank_data & addr_low; - -data_out <= DO; - -end microcoded; - --------------------------------------------------------------------------------- --- Timing diagram 1: RD and WR cycles --------------------------------------------------------------------------------- --- 1 2 3 4 5 6 7 8 --- __ __ __ __ __ __ __ __ --- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ --- --- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx --- --- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx --- --- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx --- _____ _____ --- vma_o ______________/ \___________/ \___________ --- _____ --- rd_o ______________/ \_____________________________ --- _____ --- wr_o ________________________________/ \___________ --- --- (functional diagram, actual time delays not shown) --------------------------------------------------------------------------------- --- This diagram shows a read cycle and a write cycle back to back. --- In clock edges (4) and (7), the address is loaded into the external --- synchronous RAM address register. --- In clock edge (5), read data is loaded into the CPU. --- In clock edge (7), write data is loaded into the external synchronous RAM. --- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock --- cycles, which is a waste of RAM bandwidth. --- Index: trunk/vhdl/demo/rs232_rx.vhdl =================================================================== --- trunk/vhdl/demo/rs232_rx.vhdl (revision 30) +++ trunk/vhdl/demo/rs232_rx.vhdl (nonexistent) @@ -1,218 +0,0 @@ ---############################################################################## --- RS-232 receiver, hardwired to 9600 bauds when clocked at 50MHz. --- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing! --- I don't advise using this for any purpose. ---############################################################################## - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity rs232_rx is - Port ( - rxd : in std_logic; - - data_rx : out std_logic_vector(7 downto 0); - rx_rdy : out std_logic; - read_rx : in std_logic; - - clk : in std_logic; - reset : in std_logic); -end rs232_rx; - -architecture demo of rs232_rx is - - ---############################################################################## - --- Serial port signals -signal rxd_q : std_logic; -signal tick_ctr : std_logic_vector(3 downto 0); -signal state : std_logic_vector(3 downto 0); -signal next_state : std_logic_vector(3 downto 0); -signal start_bit_detected : std_logic; -signal reset_tick_ctr : std_logic; -signal stop_bit_sampled : std_logic; -signal load_rx_buffer : std_logic; -signal stop_error : std_logic; -signal samples : std_logic_vector(2 downto 0); -signal sampled_bit : std_logic; -signal do_shift : std_logic; -signal rx_buffer : std_logic_vector(7 downto 0); -signal rx_shift_reg : std_logic_vector(9 downto 0); -signal tick_ctr_enable : std_logic; -signal tick_baud_ctr : integer; - -signal rx_rdy_flag : std_logic; -signal set_rx_rdy_flag : std_logic; - - -begin - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - tick_baud_ctr <= 0; - else - if tick_baud_ctr=325 then - tick_baud_ctr <= 0; - else - tick_baud_ctr <= tick_baud_ctr + 1; - end if; - end if; - end if; -end process; - -tick_ctr_enable <= '1' when tick_baud_ctr=325 else '0'; - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - rxd_q <= '0'; - else - if tick_ctr_enable='1' then - rxd_q <= rxd; - end if; - end if; - end if; -end process; - - -start_bit_detected <= '1' when state="0000" and rxd_q='1' and rxd='0' else '0'; -reset_tick_ctr <= '1' when start_bit_detected='1' else '0'; - -stop_bit_sampled <= '1' when state="1010" and tick_ctr="1011" else '0'; -load_rx_buffer <= '1' when stop_bit_sampled='1' and sampled_bit='1' else '0'; -stop_error <= '1' when stop_bit_sampled='1' and sampled_bit='0' else '0'; - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - tick_ctr <= "0000"; - else - if tick_ctr_enable='1' then - if tick_ctr="1111" or reset_tick_ctr='1' then - tick_ctr <= "0000"; - else - tick_ctr <= tick_ctr + 1; - end if; - end if; - end if; - end if; -end process; - -next_state <= - "0001" when state="0000" and start_bit_detected='1' else - "0000" when state="0001" and tick_ctr="1010" and sampled_bit='1' else - "0000" when state="1010" and tick_ctr="1111" else - state + 1 when tick_ctr="1111" and do_shift='1' else - state; - - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - state <= "0000"; - else - if tick_ctr_enable='1' then - state <= next_state; - end if; - end if; - end if; -end process; - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - samples <= "000"; - else - if tick_ctr_enable='1' then - if tick_ctr="0111" then - samples(0) <= rxd; - end if; - if tick_ctr="1000" then - samples(1) <= rxd; - end if; - if tick_ctr="1001" then - samples(2) <= rxd; - end if; - end if; - end if; - end if; -end process; - -with samples select - sampled_bit <= '0' when "000", - '0' when "001", - '0' when "010", - '1' when "011", - '0' when "100", - '1' when "101", - '1' when "110", - '1' when others; - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - rx_buffer <= "00000000"; - set_rx_rdy_flag <= '0'; - else - if tick_ctr_enable='1' and load_rx_buffer='1' and rx_rdy_flag='0' then - rx_buffer <= rx_shift_reg(8 downto 1); - set_rx_rdy_flag <= '1'; - else - set_rx_rdy_flag <= '0'; - end if; - end if; - end if; -end process; - -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - rx_rdy_flag <= '0'; - else - if set_rx_rdy_flag='1' then - rx_rdy_flag <= '1'; - else - if read_rx = '1' then - rx_rdy_flag <= '0'; - end if; - end if; - end if; - end if; -end process; - -do_shift <= state(0) or state(1) or state(2) or state(3); - --- reception shift register -process(clk) -begin - if clk'event and clk='1' then - if reset='1' then - rx_shift_reg <= "1111111111"; - else - if tick_ctr_enable='1' then - if tick_ctr="1010" and do_shift='1' then - rx_shift_reg(9) <= sampled_bit; - rx_shift_reg(8 downto 0) <= rx_shift_reg(9 downto 1); - end if; - end if; - end if; - end if; -end process; - -rx_rdy <= rx_rdy_flag; - -data_rx <= rx_buffer; - -end demo; Index: trunk/vhdl/demo/rs232_tx.vhdl =================================================================== --- trunk/vhdl/demo/rs232_tx.vhdl (revision 30) +++ trunk/vhdl/demo/rs232_tx.vhdl (nonexistent) @@ -1,69 +0,0 @@ ---############################################################################## --- RS-232 transmitter, hardwired to 9600 bauds when clocked at 50MHz. --- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing! --- I don't advise using this for any purpose. ---############################################################################## - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity rs232_tx is - port ( clk : in std_logic; - reset : in std_logic; - rdy : out std_logic; - load : in std_logic; - data_i : in std_logic_vector(7 downto 0); - txd : out std_logic); -end rs232_tx; - -architecture demo of rs232_tx is - -signal counter : integer; - -signal data : std_logic_vector(10 downto 0); -signal ctr_bit : std_logic_vector(3 downto 0); -signal tx : std_logic; - -begin - - -process(clk) -begin -if clk'event and clk='1' then - - if reset='1' then - data <= "10111111111"; - tx <= '0'; - ctr_bit <= "0000"; - counter <= 0; - elsif load='1' and tx='0' then - data <= "1"&data_i&"01"; - tx <= '1'; - else - if tx='1' then - if counter = 5200 then - counter <= 0; - data(9 downto 0) <= data(10 downto 1); - data(10) <= '1'; - if ctr_bit = "1010" then - tx <= '0'; - ctr_bit <= "0000"; - else - ctr_bit <= ctr_bit + 1; - end if; - else - counter <= counter + 1; - end if; - end if; - end if; -end if; -end process; - -rdy <= not tx; -txd <= data(0); - -end demo; \ No newline at end of file Index: trunk/vhdl/demo/c2sb_light8080_demo.vhd =================================================================== --- trunk/vhdl/demo/c2sb_light8080_demo.vhd (revision 30) +++ trunk/vhdl/demo/c2sb_light8080_demo.vhd (nonexistent) @@ -1,842 +0,0 @@ ---############################################################################# --- Light8080 core demo 0 : IMSAI SCS1 monitor/assembler --- --- Designed for Cyclone II FPGA Starter Develoment Kit from terasIC. --- Runs IMSAI SCS1 monitor on serial port, using 4KB of internal RAM. --- Documentation for the monitor and Altera Quartus pin assignment files are --- included. --- --- All that's really needed to run the demo is the serial interface (2 pins), --- so this should be easy to adapt to any other dev board. ---############################################################################# - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity c2sb_light8080_demo is - port ( - clk_50MHz : in std_logic; - - flash_addr : out std_logic_vector(21 downto 0); - flash_data : in std_logic_vector(7 downto 0); - flash_oe : out std_logic; - flash_we : out std_logic; - flash_reset : out std_logic; - - rxd : in std_logic; - txd : out std_logic; - - switches : in std_logic_vector(9 downto 0); - buttons : in std_logic_vector(3 downto 0); - - red_leds : out std_logic_vector(9 downto 0); - green_leds : out std_logic_vector(7 downto 0) - ); -end c2sb_light8080_demo; - -architecture demo of c2sb_light8080_demo is - - -component light8080 -port ( - addr_out : out std_logic_vector(15 downto 0); - - inta : out std_logic; - inte : out std_logic; - halt : out std_logic; - intr : in std_logic; - - vma : out std_logic; - io : out std_logic; - rd : out std_logic; - wr : out std_logic; - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - - clk : in std_logic; - reset : in std_logic ); -end component; - --- Serial port, RX -component rs232_rx -port( - rxd : IN std_logic; - read_rx : IN std_logic; - clk : IN std_logic; - reset : IN std_logic; - data_rx : OUT std_logic_vector(7 downto 0); - rx_rdy : OUT std_logic - ); -end component; - --- Serial port, TX -component rs232_tx -port( - clk : IN std_logic; - reset : IN std_logic; - load : IN std_logic; - data_i : IN std_logic_vector(7 downto 0); - rdy : OUT std_logic; - txd : OUT std_logic - ); -end component; - - ---############################################################################## --- light8080 CPU system signals - -signal data_in : std_logic_vector(7 downto 0); -signal vma : std_logic; -signal rd : std_logic; -signal wr : std_logic; -signal io : std_logic; -signal data_out : std_logic_vector(7 downto 0); -signal addr : std_logic_vector(15 downto 0); -signal inta : std_logic; -signal inte : std_logic; -signal intr : std_logic; -signal halt : std_logic; - - -signal reg_h : std_logic_vector(7 downto 0); -signal reg_l : std_logic_vector(7 downto 0); -signal io_q : std_logic; -signal rd_q : std_logic; -signal io_read : std_logic; -signal io_write : std_logic; - ---############################################################################## --- RS232 signals - -signal rx_rdy : std_logic; -signal tx_rdy : std_logic; -signal rs232_data_rx : std_logic_vector(7 downto 0); -signal rs232_status : std_logic_vector(7 downto 0); -signal data_io_out : std_logic_vector(7 downto 0); -signal io_port : std_logic_vector(7 downto 0); -signal read_rx : std_logic; -signal write_tx : std_logic; - -signal rom_addr : std_logic_vector(11 downto 0); -type t_rom is array(0 to 4095) of std_logic_vector(7 downto 0); - -signal rom : t_rom := ( --- @begin_rom - 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-X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", -X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00" - - --- @end_rom -); - - --- i/o signals -signal data_io_in : std_logic_vector(7 downto 0); -signal data_mem_in : std_logic_vector(7 downto 0); - - - --- Clock & reset signals -signal clk_1hz : std_logic; -signal counter_1hz : integer; -signal reset : std_logic; - - -begin - - --- Program memory (it's RAM really) -rom_addr <= addr(11 downto 0); -process(clk_50MHz) -begin - if (clk_50MHz'event and clk_50MHz='1') then - data_mem_in <= rom(conv_integer(rom_addr)); - if wr = '1' then - rom(conv_integer(rom_addr)) <= data_out; - end if; - end if; -end process; - - -process(clk_50MHz) -begin - if (clk_50MHz'event and clk_50MHz='1') then - if reset='1' then - reg_h <= "00000000"; - reg_l <= "00000000"; - else - if io_write='1' then - if addr(7 downto 0)=X"40" then - reg_l <= data_out; - end if; - if addr(7 downto 0)=X"f1" then -- FIXME - reg_h <= data_out; - end if; - end if; - end if; - end if; -end process; - - --- CPU control signals -intr <= '0'; - --- CPU instance -cpu: light8080 port map( - clk => clk_50MHz, - reset => reset, - vma => vma, - rd => rd, - wr => wr, - io => io, - addr_out => addr, - data_in => data_in, - data_out => data_out, - intr => intr, - inte => inte, - inta => inta, - halt => halt -); - - -process(clk_50MHz) -begin - if clk_50MHz'event and clk_50MHz = '1' then - if reset = '1' then - io_q <= '0'; - rd_q <= '0'; - io_port <= X"00"; - data_io_out <= X"00"; - else - io_q <= io; - rd_q <= rd; - io_port <= addr(7 downto 0); - data_io_out <= data_out; - end if; - end if; -end process; - -red_leds(0) <= halt; -red_leds(1) <= inte; -red_leds(2) <= vma; -red_leds(3) <= rd; -red_leds(4) <= wr; - -red_leds(9) <= tx_rdy; -red_leds(8) <= rx_rdy; -red_leds(7 downto 5) <= "000"; - ---##### Input ports ########################################################### - --- mem vs. io input mux -data_in <= data_io_in when io_q='1' else data_mem_in; - --- io read enable (for async io ports; data read in cycle following io='1') -io_read <= '1' when io_q='1' and rd_q='1' else '0'; - --- io write enable (for sync io ports; dara written in cycle following io='1') -io_write <= '1' when io='1' and wr='1' else '0'; - --- read/write signals for rs232 modules -read_rx <= '1' when io_read='1' and addr(7 downto 0)=X"21" else '0'; -write_tx <= '1' when io_write='1' and addr(7 downto 0)=X"21" else '0'; - --- synchronized input port mux (using registered port address) -with io_port select - data_io_in <= rs232_status when X"20", - rs232_data_rx when X"21", - switches(7 downto 0) when others; -- X"40" - - - ---############################################################################## --- terasIC Cyclone II STARTER KIT BOARD ---############################################################################## - ---############################################################################## --- FLASH ---############################################################################## - - -- Flash is unused - flash_addr <= "000000000000" & switches; - flash_we <= '1'; - flash_oe <= '1'; - flash_reset <= '1'; - --green_leds <= flash_data; - ---############################################################################## --- RESET, CLOCK ---############################################################################## - --- Use button 3 as reset -reset <= not buttons(3); - --- Generate a 1-Hz clock for visual reference -process(clk_50MHz) -begin - if clk_50MHz'event and clk_50MHz='1' then - if buttons(3) = '1' then - clk_1hz <= '0'; - counter_1hz <= 0; - else - if buttons(2) = '0' then - if counter_1hz = 25000000 then - counter_1hz <= 0; - clk_1hz <= not clk_1hz; - else - counter_1hz <= counter_1hz + 1; - end if; - end if; - end if; - end if; -end process; - - ---############################################################################## --- LEDS, SWITCHES ---############################################################################## - -green_leds <= reg_l; - ---############################################################################## --- SERIAL ---############################################################################## - ---txd <= rxd; -- loopback rs-232 - -serial_rx : rs232_rx port map( - rxd => rxd, - data_rx => rs232_data_rx, - rx_rdy => rx_rdy, - read_rx => read_rx, - clk => clk_50MHz, - reset => reset - ); - -serial_tx : rs232_tx port map( - clk => clk_50MHz, - reset => reset, - rdy => tx_rdy, - load => write_tx, - data_i => data_out, - txd => txd - ); - -rs232_status <= (not tx_rdy) & "000000" & (not rx_rdy); - - -end demo; Index: trunk/vhdl/demo/c2sb_demo.csv =================================================================== --- trunk/vhdl/demo/c2sb_demo.csv (revision 30) +++ trunk/vhdl/demo/c2sb_demo.csv (nonexistent) @@ -1,197 +0,0 @@ -# Copyright (C) 1991-2006 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - -# Quartus II Version 6.1 Build 201 11/27/2006 SJ Web Edition -# File: C:\Documents and Settings\ja_rd\Escritorio\light8080\vhdl\demo\c2sb_demo.csv -# Generated on: Sun Nov 04 23:24:25 2007 - -# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software. - -To,Direction,Location,I/O Bank,Vref Group,I/O Standard,Reserved,Group -addr_out[15],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[14],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[13],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[12],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[11],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[10],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[9],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[8],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[7],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[6],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[5],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[4],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[3],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[2],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[1],Output,,,,3.3-V LVTTL,,addr_out[15..0] -addr_out[0],Output,,,,3.3-V LVTTL,,addr_out[15..0] -clk,Input,PIN_L1,2,B2_N1,3.3-V LVTTL,, -data_in[7],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[6],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[5],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[4],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[3],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[2],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[1],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_in[0],Input,,,,3.3-V LVTTL,,data_in[7..0] -data_out[7],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[6],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[5],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[4],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[3],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[2],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[1],Output,,,,3.3-V LVTTL,,data_out[7..0] -data_out[0],Output,,,,3.3-V LVTTL,,data_out[7..0] -halt,Output,,,,3.3-V LVTTL,, -inta,Output,,,,3.3-V LVTTL,, -inte,Output,,,,3.3-V LVTTL,, -intr,Input,,,,3.3-V LVTTL,, -io,Output,,,,3.3-V LVTTL,, -rd,Output,,,,3.3-V LVTTL,, -reset,Input,,,,3.3-V LVTTL,, -vma,Output,,,,3.3-V LVTTL,, -wr,Output,,,,3.3-V LVTTL,, -hex0[0],Unknown,PIN_J2,2,B2_N1,3.3-V LVTTL,, -hex0[1],Unknown,PIN_J1,2,B2_N1,3.3-V LVTTL,, -hex0[2],Unknown,PIN_H2,2,B2_N1,3.3-V LVTTL,, -hex0[3],Unknown,PIN_H1,2,B2_N1,3.3-V LVTTL,, -hex0[4],Unknown,PIN_F2,2,B2_N1,3.3-V LVTTL,, -hex0[5],Unknown,PIN_F1,2,B2_N1,3.3-V LVTTL,, -hex0[6],Unknown,PIN_E2,2,B2_N1,3.3-V LVTTL,, -hex1[0],Unknown,PIN_E1,2,B2_N1,3.3-V LVTTL,, -hex1[1],Unknown,PIN_H6,2,B2_N0,3.3-V LVTTL,, -hex1[2],Unknown,PIN_H5,2,B2_N0,3.3-V LVTTL,, -hex1[3],Unknown,PIN_H4,2,B2_N0,3.3-V LVTTL,, -hex1[4],Unknown,PIN_G3,2,B2_N0,3.3-V LVTTL,, -hex1[5],Unknown,PIN_D2,2,B2_N0,3.3-V LVTTL,, -hex1[6],Unknown,PIN_D1,2,B2_N0,3.3-V LVTTL,, -hex2[0],Unknown,PIN_G5,2,B2_N0,3.3-V LVTTL,, -hex2[1],Unknown,PIN_G6,2,B2_N0,3.3-V LVTTL,, -hex2[2],Unknown,PIN_C2,2,B2_N0,3.3-V LVTTL,, -hex2[3],Unknown,PIN_C1,2,B2_N0,3.3-V LVTTL,, -hex2[4],Unknown,PIN_E3,2,B2_N0,3.3-V LVTTL,, -hex2[5],Unknown,PIN_E4,2,B2_N0,3.3-V LVTTL,, -hex2[6],Unknown,PIN_D3,2,B2_N0,3.3-V LVTTL,, -hex3[0],Unknown,PIN_F4,2,B2_N0,3.3-V LVTTL,, -hex3[1],Unknown,PIN_D5,2,B2_N0,3.3-V LVTTL,, -hex3[2],Unknown,PIN_D6,2,B2_N0,3.3-V LVTTL,, -hex3[3],Unknown,PIN_J4,2,B2_N1,3.3-V LVTTL,, -hex3[4],Unknown,PIN_L8,2,B2_N1,3.3-V LVTTL,, -hex3[5],Unknown,PIN_F3,2,B2_N0,3.3-V LVTTL,, -hex3[6],Unknown,PIN_D4,2,B2_N0,3.3-V LVTTL,, -green_leds[0],Unknown,PIN_U22,6,B6_N1,3.3-V LVTTL,, -green_leds[1],Unknown,PIN_U21,6,B6_N1,3.3-V LVTTL,, -green_leds[2],Unknown,PIN_V22,6,B6_N1,3.3-V LVTTL,, -green_leds[3],Unknown,PIN_V21,6,B6_N1,3.3-V LVTTL,, -green_leds[4],Unknown,PIN_W22,6,B6_N1,3.3-V LVTTL,, -green_leds[5],Unknown,PIN_W21,6,B6_N1,3.3-V LVTTL,, -green_leds[6],Unknown,PIN_Y22,6,B6_N1,3.3-V LVTTL,, -green_leds[7],Unknown,PIN_Y21,6,B6_N1,3.3-V LVTTL,, -flash_addr[0],Unknown,PIN_AB20,7,B7_N0,3.3-V LVTTL,, -flash_addr[1],Unknown,PIN_AA14,7,B7_N1,3.3-V LVTTL,, -flash_addr[2],Unknown,PIN_Y16,7,B7_N0,3.3-V LVTTL,, -flash_addr[3],Unknown,PIN_R15,7,B7_N0,3.3-V LVTTL,, -flash_addr[4],Unknown,PIN_T15,7,B7_N0,3.3-V LVTTL,, -flash_addr[5],Unknown,PIN_U15,7,B7_N0,3.3-V LVTTL,, -flash_addr[6],Unknown,PIN_V15,7,B7_N0,3.3-V LVTTL,, -flash_addr[7],Unknown,PIN_W15,7,B7_N0,3.3-V LVTTL,, -flash_addr[8],Unknown,PIN_R14,7,B7_N0,3.3-V LVTTL,, -flash_addr[9],Unknown,PIN_Y13,7,B7_N1,3.3-V LVTTL,, -flash_addr[10],Unknown,PIN_R12,7,B7_N1,3.3-V LVTTL,, -flash_addr[11],Unknown,PIN_T12,7,B7_N1,3.3-V LVTTL,, -flash_addr[12],Unknown,PIN_AB14,7,B7_N1,3.3-V LVTTL,, -flash_addr[13],Unknown,PIN_AA13,7,B7_N1,3.3-V LVTTL,, -flash_addr[14],Unknown,PIN_AB13,7,B7_N1,3.3-V LVTTL,, -flash_addr[15],Unknown,PIN_AA12,7,B7_N1,3.3-V LVTTL,, -flash_addr[16],Unknown,PIN_AB12,7,B7_N1,3.3-V LVTTL,, -flash_addr[17],Unknown,PIN_AA20,7,B7_N0,3.3-V LVTTL,, -flash_addr[18],Unknown,PIN_U14,7,B7_N0,3.3-V LVTTL,, -flash_addr[19],Unknown,PIN_V14,7,B7_N1,3.3-V LVTTL,, -flash_addr[20],Unknown,PIN_U13,7,B7_N1,3.3-V LVTTL,, -flash_addr[21],Unknown,PIN_R13,7,B7_N0,3.3-V LVTTL,, -flash_data[0],Unknown,PIN_AB16,7,B7_N1,3.3-V LVTTL,, -flash_data[1],Unknown,PIN_AA16,7,B7_N1,3.3-V LVTTL,, -flash_data[2],Unknown,PIN_AB17,7,B7_N1,3.3-V LVTTL,, -flash_data[3],Unknown,PIN_AA17,7,B7_N1,3.3-V LVTTL,, -flash_data[4],Unknown,PIN_AB18,7,B7_N0,3.3-V LVTTL,, -flash_data[5],Unknown,PIN_AA18,7,B7_N0,3.3-V LVTTL,, -flash_data[6],Unknown,PIN_AB19,7,B7_N0,3.3-V LVTTL,, -flash_data[7],Unknown,PIN_AA19,7,B7_N0,3.3-V LVTTL,, -flash_oe,Unknown,PIN_AA15,7,B7_N1,3.3-V LVTTL,, -flash_reset,Unknown,PIN_W14,7,B7_N1,3.3-V LVTTL,, -flash_we,Unknown,PIN_Y14,7,B7_N0,3.3-V LVTTL,, -switches[0],Unknown,PIN_L22,5,B5_N1,3.3-V LVTTL,, -switches[1],Unknown,PIN_L21,5,B5_N1,3.3-V LVTTL,, -switches[2],Unknown,PIN_M22,6,B6_N0,3.3-V LVTTL,, -switches[3],Unknown,PIN_V12,7,B7_N1,3.3-V LVTTL,, -switches[4],Unknown,PIN_W12,7,B7_N1,3.3-V LVTTL,, -switches[5],Unknown,PIN_U12,8,B8_N0,3.3-V LVTTL,, -switches[6],Unknown,PIN_U11,8,B8_N0,3.3-V LVTTL,, -switches[7],Unknown,PIN_M2,1,B1_N0,3.3-V LVTTL,, -switches[8],Unknown,PIN_M1,1,B1_N0,3.3-V LVTTL,, -switches[9],Unknown,PIN_L2,2,B2_N1,3.3-V LVTTL,, -buttons[0],Unknown,PIN_R22,6,B6_N0,3.3-V LVTTL,, -buttons[1],Unknown,PIN_R21,6,B6_N0,3.3-V LVTTL,, -buttons[2],Unknown,PIN_T22,6,B6_N0,3.3-V LVTTL,, -buttons[3],Unknown,PIN_T21,6,B6_N0,3.3-V LVTTL,, -red_leds[0],Unknown,PIN_R20,6,B6_N0,3.3-V LVTTL,, -red_leds[1],Unknown,PIN_R19,6,B6_N0,3.3-V LVTTL,, -red_leds[2],Unknown,PIN_U19,6,B6_N1,3.3-V LVTTL,, -red_leds[3],Unknown,PIN_Y19,6,B6_N1,3.3-V LVTTL,, -red_leds[4],Unknown,PIN_T18,6,B6_N1,3.3-V LVTTL,, -red_leds[5],Unknown,PIN_V19,6,B6_N1,3.3-V LVTTL,, -red_leds[6],Unknown,PIN_Y18,6,B6_N1,3.3-V LVTTL,, -red_leds[7],Unknown,PIN_U18,6,B6_N1,3.3-V LVTTL,, -red_leds[8],Unknown,PIN_R18,6,B6_N0,3.3-V LVTTL,, -red_leds[9],Unknown,PIN_R17,6,B6_N1,3.3-V LVTTL,, -rxd,Unknown,PIN_F14,4,B4_N1,3.3-V LVTTL,, -txd,Unknown,PIN_G12,4,B4_N1,3.3-V LVTTL,, -sram_addr[0],Unknown,PIN_AA3,8,B8_N1,3.3-V LVTTL,, -sram_addr[1],Unknown,PIN_AB3,8,B8_N1,3.3-V LVTTL,, -sram_addr[2],Unknown,PIN_AA4,8,B8_N1,3.3-V LVTTL,, -sram_addr[3],Unknown,PIN_AB4,8,B8_N1,3.3-V LVTTL,, -sram_addr[4],Unknown,PIN_AA5,8,B8_N1,3.3-V LVTTL,, -sram_addr[5],Unknown,PIN_AB10,8,B8_N0,3.3-V LVTTL,, -sram_addr[6],Unknown,PIN_AA11,8,B8_N0,3.3-V LVTTL,, -sram_addr[7],Unknown,PIN_AB11,8,B8_N0,3.3-V LVTTL,, -sram_addr[8],Unknown,PIN_V11,8,B8_N0,3.3-V LVTTL,, -sram_addr[9],Unknown,PIN_W11,8,B8_N0,3.3-V LVTTL,, -sram_addr[10],Unknown,PIN_R11,8,B8_N0,3.3-V LVTTL,, -sram_addr[11],Unknown,PIN_T11,8,B8_N0,3.3-V LVTTL,, -sram_addr[12],Unknown,PIN_Y10,8,B8_N0,3.3-V LVTTL,, -sram_addr[13],Unknown,PIN_U10,8,B8_N0,3.3-V LVTTL,, -sram_addr[14],Unknown,PIN_R10,8,B8_N0,3.3-V LVTTL,, -sram_addr[15],Unknown,PIN_T7,8,B8_N1,3.3-V LVTTL,, -sram_addr[16],Unknown,PIN_Y6,8,B8_N1,3.3-V LVTTL,, -sram_addr[17],Unknown,PIN_Y5,8,B8_N1,3.3-V LVTTL,, -sram_data[0],Unknown,PIN_AA6,8,B8_N1,3.3-V LVTTL,, -sram_data[1],Unknown,PIN_AB6,8,B8_N1,3.3-V LVTTL,, -sram_data[2],Unknown,PIN_AA7,8,B8_N1,3.3-V LVTTL,, -sram_data[3],Unknown,PIN_AB7,8,B8_N1,3.3-V LVTTL,, -sram_data[4],Unknown,PIN_AA8,8,B8_N0,3.3-V LVTTL,, -sram_data[5],Unknown,PIN_AB8,8,B8_N0,3.3-V LVTTL,, -sram_data[6],Unknown,PIN_AA9,8,B8_N0,3.3-V LVTTL,, -sram_data[7],Unknown,PIN_AB9,8,B8_N0,3.3-V LVTTL,, -sram_data[8],Unknown,PIN_Y9,8,B8_N0,3.3-V LVTTL,, -sram_data[9],Unknown,PIN_W9,8,B8_N0,3.3-V LVTTL,, -sram_data[10],Unknown,PIN_V9,8,B8_N1,3.3-V LVTTL,, -sram_data[11],Unknown,PIN_U9,8,B8_N0,3.3-V LVTTL,, -sram_data[12],Unknown,PIN_R9,8,B8_N0,3.3-V LVTTL,, -sram_data[13],Unknown,PIN_W8,8,B8_N1,3.3-V LVTTL,, -sram_data[14],Unknown,PIN_V8,8,B8_N1,3.3-V LVTTL,, -sram_data[15],Unknown,PIN_U8,8,B8_N1,3.3-V LVTTL,, -sram_ce_n,Unknown,PIN_AB5,8,B8_N1,3.3-V LVTTL,, -sram_we_n,Unknown,PIN_AA10,8,B8_N0,3.3-V LVTTL,, -sram_ub_n,Unknown,PIN_W7,8,B8_N1,3.3-V LVTTL,, -sram_lb_n,Unknown,PIN_Y7,8,B8_N1,3.3-V LVTTL,, -sram_oe_n,Unknown,PIN_T8,8,B8_N1,3.3-V LVTTL,, Index: trunk/util/microrom.bat =================================================================== --- trunk/util/microrom.bat (revision 30) +++ trunk/util/microrom.bat (nonexistent) @@ -1 +0,0 @@ -perl uasm.pl ..\ucode\light8080.m80 -rom_vhdl > ..\ucode\rom.txt \ No newline at end of file Index: trunk/util/uasm.pl =================================================================== --- trunk/util/uasm.pl (revision 30) +++ trunk/util/uasm.pl (nonexistent) @@ -1,892 +0,0 @@ -################################################################################ -# uasm.pl : light8080 core microcode assembler -################################################################################ -# Usage: perl uasm.pl -# -# The command list is a space-separated sequence of the following: -# -# -lst : Shows a listing of the assembled microinstructions next to their -# assembler source lines. Not very useful because it does not show -# assembler pragma, label or comment lines. -# -labels : Shows a list of all defined labels with their address and the -# number of times they are used. -# -bitfields: Shows a list of all the different microinstructions generated, -# plus the number of times they are used. Might be useful to encode -# the microinstructions and save rom bits. -# -instructions: Shows a list of all defined instructions with the address their -# microcode starts at. -# -rom_bin : Shows a raw list of all the binary microinstructions. -# -rom_vhdl : Shows a vhdl block containing the microcode rom declaration. -# -# If none of the above commands is given, the program just exits silently. Any -# unrecognized command is silently ignored. -################################################################################ -# Assembler format (informal definition, source is the ultimate reference!): -# -# := -# [] | (*1) -# ; [; []] | -# JSR |TJSR -# -# := {':' immediately followed by a common identifier} -# := {an identifier defined as label anywhere in the file} -# := = | NOP -# := T1 | T2 -# := | DI | -# := {s}|{d}|{p}0|{p}1 (*3) -# := _a|_b|_c|_d|_e|_h|_l|_f|_a|_ph|_pl|_x|_y|_z|_w|_sh|_sl| -# := = | NOP -# := | DO -# := add|adc|sub|sbb| and|orl|not|xrl| rla|rra|rlca|rrca| aaa| -# t1|rst|daa|cpc|sec|psw -# := [, ...] -# := #decode|#di|#ei|#io|#auxcy|#clrt1|#halt|#end|#ret|#rd|#wr|#setacy -# #ld_al|#ld_addr|#fp_c|#fp_r|#fp_rc (*2) -# -# *1 Labels appear alone by themselves in a line -# *2 There are some restrictions on the flags that can be used together -# *3 Registers are specified by IR field -# -################################################################################ -# ALU operations -# -#Operation Encoding ALU result -#=============================================================================== -#ADD 001100 T2 + T1 -#ADC 001101 T2 + T1 + CY -#SUB 001110 T2 - T1 -#SBB 001111 T2 � T1 - CY -#AND 000100 T1 AND T2 -#ORL 000101 T1 OR T2 -#NOT 000110 NOT T1 -#XRL 000111 T1 XOR T2 -#RLA 000000 8080 RLC -#RRA 000001 8080 RRC -#RLCA 000010 8080 RAL -#RRCA 000011 8080 RAR -#T1 010111 T1 -#RST 011111 8*IR(5..3), as per RST instruction -#DAA 101000 DAA T1 (but only after executing 2 in a row) -#CPC 101100 UNDEFINED (CY complemented) -#SEC 101101 UNDEFINED (CY set) -################################################################################ -# Flags : -# --- Flags from group 1: use only one of these -# #decode : Load address counter and IR with contents of data input lines, -# thus starting opcode decoging. -# #ei : Set interrupt enable register. -# #di : Reset interrupt enable register. -# #io : Activate io signal for 1st cycle. -# #auxcy : Use aux carry instead of regular carry for this operation. -# #clrt1 : Clear T1 at the end of 1st cycle. -# #halt : Jump to microcode address 0x07 without saving return value. -# -# --- Flags from group 2: use only one of these -# #setacy : Set aux carry at the start of 1st cycle (used for ++). -# #end : Jump to microinstruction address 3 after the present m.i. -# #ret : Jump to address saved by the last JST or TJSR m.i. -# #rd : Activate rd signal for the 2nd cycle. -# #wr : Activate wr signal for the 2nd cycle. -# --- Independent flags: no restrictions -# #ld_al : Load AL register with register bank output as read by operation 1. -# (used in memory and io access). -# #ld_addr : Load address register (H byte = register bank output as read by -# operation 1, L byte = AL). -# Activate vma signal for 1st cycle. -# --- PSW update flags: use only one of these -# #fp_r : This instruction updates all PSW flags except for C. -# #fp_c : This instruction updates only the C flag in the PSW. -# #fp_rc : This instruction updates all the flags in the PSW. -################################################################################ -# Read the design notes for a brief reference to the micromachine internal -# behavior, including implicit loads/erases. -################################################################################ - -$file = shift(@ARGV); - -open(INFO, $file) or die "unable to open file '$file'\n"; -@lines = ; -close(INFO); - -$field2_nop = '0'.'0000'.'00'.'0'.'0'.'000000'; -$field2_jsr = '0'.'0000'.'00'.'0'.'0'.'000000'; - -%field1_ops = - ( 'nop', '000'.'000'.'00000'.'00'.'0000'.$field2_nop, - 'jsr', '000'.'010'.'00000'.'00'.'0000'.$field2_jsr, - 'tjsr', '000'.'100'.'00000'.'00'.'0000'.$field2_jsr, - - 't1 = {s}', '000'.'000'.'00101'.'01'.'0000'.$field2_nop, - 't1 = {d}', '000'.'000'.'00101'.'10'.'0000'.$field2_nop, - 't1 = {p}0', '000'.'000'.'00101'.'11'.'0000'.$field2_nop, - 't1 = {p}1', '000'.'000'.'00101'.'11'.'0001'.$field2_nop, - 't1 = di', '000'.'000'.'00100'.'00'.'0000'.$field2_nop, - 't1 = _b', '000'.'000'.'00101'.'00'.'0000'.$field2_nop, - 't1 = _c', '000'.'000'.'00101'.'00'.'0001'.$field2_nop, - 't1 = _d', '000'.'000'.'00101'.'00'.'0010'.$field2_nop, - 't1 = _e', '000'.'000'.'00101'.'00'.'0011'.$field2_nop, - 't1 = _h', '000'.'000'.'00101'.'00'.'0100'.$field2_nop, - 't1 = _l', '000'.'000'.'00101'.'00'.'0101'.$field2_nop, - 't1 = _a', '000'.'000'.'00101'.'00'.'0111'.$field2_nop, - 't1 = _f', '000'.'000'.'00101'.'00'.'0110'.$field2_nop, - 't1 = _ph', '000'.'000'.'00101'.'00'.'1000'.$field2_nop, - 't1 = _pl', '000'.'000'.'00101'.'00'.'1001'.$field2_nop, - 't1 = _x', '000'.'000'.'00101'.'00'.'1010'.$field2_nop, - 't1 = _y', '000'.'000'.'00101'.'00'.'1011'.$field2_nop, - 't1 = _z', '000'.'000'.'00101'.'00'.'1100'.$field2_nop, - 't1 = _w', '000'.'000'.'00101'.'00'.'1101'.$field2_nop, - 't1 = _sh', '000'.'000'.'00101'.'00'.'1110'.$field2_nop, - 't1 = _sl', '000'.'000'.'00101'.'00'.'1111'.$field2_nop, - - 't2 = {s}', '000'.'000'.'00011'.'01'.'0000'.$field2_nop, - 't2 = {d}', '000'.'000'.'00011'.'10'.'0000'.$field2_nop, - 't2 = {p}0', '000'.'000'.'00011'.'11'.'0000'.$field2_nop, - 't2 = {p}1', '000'.'000'.'00011'.'11'.'0001'.$field2_nop, - 't2 = di', '000'.'000'.'00010'.'00'.'0000'.$field2_nop, - 't2 = _b', '000'.'000'.'00011'.'00'.'0000'.$field2_nop, - 't2 = _c', '000'.'000'.'00011'.'00'.'0001'.$field2_nop, - 't2 = _d', '000'.'000'.'00011'.'00'.'0010'.$field2_nop, - 't2 = _e', '000'.'000'.'00011'.'00'.'0011'.$field2_nop, - 't2 = _h', '000'.'000'.'00011'.'00'.'0100'.$field2_nop, - 't2 = _l', '000'.'000'.'00011'.'00'.'0101'.$field2_nop, - 't2 = _a', '000'.'000'.'00011'.'00'.'0111'.$field2_nop, - 't2 = _f', '000'.'000'.'00011'.'00'.'0110'.$field2_nop, - 't2 = _ph', '000'.'000'.'00011'.'00'.'1000'.$field2_nop, - 't2 = _pl', '000'.'000'.'00011'.'00'.'1001'.$field2_nop, - 't2 = _x', '000'.'000'.'00011'.'00'.'1010'.$field2_nop, - 't2 = _y', '000'.'000'.'00011'.'00'.'1011'.$field2_nop, - 't2 = _z', '000'.'000'.'00011'.'00'.'1100'.$field2_nop, - 't2 = _w', '000'.'000'.'00011'.'00'.'1101'.$field2_nop, - 't2 = _sh', '000'.'000'.'00011'.'00'.'1110'.$field2_nop, - 't2 = _sl', '000'.'000'.'00011'.'00'.'1111'.$field2_nop - - ); - - -$re_field1 = "(".join('|',keys %field1_ops).")"; -$re_field1 =~ s/\[/\\\[/g; -$re_field1 =~ s/\]/\\\]/g; - -%field2_ops = - ( 'add', '001100', - 'adc', '001101', - 'sub', '001110', - 'sbb', '001111', - - 'and', '000100', - 'orl', '000110', - 'not', '000111', - 'xrl', '000101', - - 'rla', '000000', - 'rra', '000001', - 'rlca', '000010', - 'rrca', '000011', - - 'aaa', '111000', - - 't1', '010111', - 'rst', '011111', - 'daa', '101000', - 'cpc', '101100', - 'sec', '101101', - 'psw', '110000' - ); - - -$re_f2_ops = "(".join('|',keys %field2_ops).")"; -$re_f2_ops =~ s/\[/\\\[/g; -$re_f2_ops =~ s/\]/\\\]/g; - -# 'parse' command line flags into a string -$cmdline = join ':', @ARGV; - -$num_line = 0; -$addr = 0; - -%labels = (); # -@label_uses = (); # -@undefined_targets = (); # array of -$num_errors = 0; - -@bitfields = (); - -@rom = (); -@asm = (); -@errors = (); -@num_lines = (); - -%asm_to_uaddr = (); # opcode asm -> uaddress -%uaddr_to_asm = (); # uaddress -> opcode asm - -%uaddr_to_pattern = (); # uaddress -> pattern -%pattern_to_uaddr = (); # pattern -> uaddress -- simulation, decoder - -LINE: foreach $line (@lines) { - - $num_line++; - - $line =~ tr/A-Z/a-z/; - $line =~ s/(--|\/\/).*//; - $line =~ s/^\s*//g; - $line =~ s/\s*\$//g; - chomp($line); - - $uinst = { - field_1 => '', - src => '', - special => '', - field_2 => '', - field_0 => '000000', - flags => '', - error => '', - asm => $line - }; - - - # if line is whitespace or comment (which has been changed to whitespace) - # then skip to next line - if($line eq ''){ - next; - } - - # if $line is a label declaration, get it and skip to next line - # note labels come alone in the line, unlike other assemblers - # TODO it'd be simple to change this... - if($line =~ /^\s*:(\w+)/){ - # subroutine label (labels are only used for jsrs) - $labels{$1} = $addr; - next; - } - - # if line is a pragma, process it - if($line =~ /^\s*__/){ - # TODO process pragmas __reset, __fetch, __int - - #if($line =~ /^\s*__code\s+"([0|1|s|d|p|a|r]+)"/){ - # we do nothing with the opcode byte; it's for reference only - #printf "%04d # %s\n",$addr,$1; - #} - if($line =~ /^\s*__asm\s+(.*)/){ - # save the start address for the CPU instruction - # it will be used in the design of the decoder - $asm_to_uaddr{$1} = $addr; - $uaddr_to_asm{$addr} = $1; - } - - if($line =~ /^\s*__code\s+"(.*)".*/){ - # save the start address for the CPU instruction - # it will be used in the design of the decoder - $pattern_to_uaddr{$1} = $addr; - $uaddr_to_pattern{$addr} = $1; - } - - - next; - } - - # get flags field (all text following 1st '#' included) - # remove it so we're left with 'field1 ; field2 [;]' - $line = process_flags($line); - - # break line in 1 or 2 fields - @fields = split /;/, $line; - - # process 1st field... - $done = process_field1($fields[0]); - - # ...and process 2nd field if there is one (depends on field1 format) - # TODO check that there's no field2 when there shouldn't - if($done != 1){ - $done = process_field2($fields[1]); - } - - # finally, process extra flags produced by field1 assembly (jsr/tjsr) - process_extra_flags(); - - # complete bitfield with flags... - substr($uinst->{field1}, 0, 6) = $uinst->{field_0}; - - # Now, we already have the bitfields. - - push(@rom, $uinst->{field1}); - push(@asm, substr($line,0,40)); - push(@num_lines, $num_line); - if($uinst->{error} eq ''){ - push(@errors, ''); - } - else{ - push(@errors, $uinst->{error}); - } - - $addr++; #addr++ even for error uinsts - -} -continue { -} - -# Line processing finished (1st pass). Start 2nd pass and do listings -# if requested - -# 2nd pass - -# now we know the value of all labels, fill in address field of forward jumps -foreach $target (@undefined_targets){ - @item = @{$target}; - $value = to_bin($labels{$item[0]}, 8); - $adr = $item[1]*1; - - substr($rom[$adr], 20,2, substr($value, 0,2)); - substr($rom[$adr], 26,6, substr($value, 2,6)); -} - -foreach $bf (@rom){ - push(@bitfields, $bf); -} - -# listings - -if($cmdline =~ /-lst/){ - $do_lst = 1; -} - -$i = 0; -foreach $bf (@rom){ - if($do_lst){ - printf "%02x %32s :: %s\n", $i, $bf, $asm[$i]; - if($errors[$i] ne ''){ - printf " ERROR (%d): %s\n", $num_lines[$i], $errors[$i]; - } - } - - $i++; -} - -if($do_lst){ - # completion message - printf "\nDone. %d uinsts, %d errors.\n", $addr, $num_errors; -} - -# label listing -if($cmdline =~ /\-labels/){ - label_list(); -} - -# bitfield histogram -if($cmdline =~ /\-bitfields/){ - bitfield_histogram(); -} - -# show cpu instruction microcode addresses -if($cmdline =~ /\-instructions/){ - foreach $asm (sort {$asm_to_uaddr{$a} <=> $asm_to_uaddr{$b}}(keys %asm_to_uaddr)){ - $uaddress = $asm_to_uaddr{$asm}; - printf "%02x %s %s\n", $uaddress, $uaddr_to_pattern{$uaddress}, $asm; - } -} - -if($cmdline =~ /\-rom_vhdl/){ - show_decoder_table('vhdl'); -} - -if($cmdline =~ /\-rom_bin/){ - show_decoder_table('bin'); -} - -# end of main program - - -################################################################################ - - -sub show_decoder_table { - - my $fmat = shift(@_); - - # show decoder rom contents - %decoder_hash = (); - foreach $pat (keys %pattern_to_uaddr){ - $add = $pattern_to_uaddr{$pat}; - $pat =~ s/[a-z]/\[01\]/g; - $decoder_hash{$pat} = $add; - } - - @decoder_rom = (); - for($i = 0; $i<256; $i++){ - $b = to_bin($i, 8); - $val = 0; - # We'll match the opcode to the pattern with the shortest length; that is, - # the one with the less wildcards in it. Crude but effective in this case. - $len_matched_pat = 1000; - foreach $pat (keys %decoder_hash){ - if($b =~ /$pat/){ - if(length($pat) < $len_matched_pat){ - $val = $decoder_hash{$pat}; - $len_matched_pat = length($pat); - } - #last; - } - } - push @decoder_rom, $val; - } - - if($fmat eq 'vhdl'){ - # print rom vhdl header... - print "type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);\n"; - print "signal rom : t_rom := (\n"; - } - - # The 1st half of the uinst rom holds 256 uinstructions - my $i=0; - foreach $bf (@rom){ - if($fmat eq 'vhdl'){ - printf "\"%s\", -- %03x\n", $bf, $i; - } - else{ - printf "%s\n", $bf; - } - $i++; - } - # Fill remaining slots with ENDs - for(;$i<256;$i++){ - my $val = '00000100000000000000000000000000'; - if($fmat eq 'vhdl'){ - printf "\"%s\", -- %03x\n", $val, $i; - } - else{ - printf "%s\n", $val; - } - } - - # The 2nd half (upper 256 entries) of the ucode rom contains a jump table - # with a jsr for each of the 256 opcodes, serving as cheap decoder: - foreach $entry (@decoder_rom){ - my $val = to_bin($entry, 8); - $val = '00001000000000000000'.substr($val,0,2).'0000'.substr($val,2,6); - $i++; - if($fmat eq 'vhdl'){ - printf "\"%s\"", $val; - if($i<512){ - print ","; - } - else{ - print " "; - } - printf " -- %03x\n", ($i - 1); - } - else{ - printf "%s\n", $val; - } - } - - if($fmat eq 'vhdl'){ - # close vhdl declaration - print "\n);\n"; - } - -} - -sub label_list { - # label table listing - print "\nlabels:\n"; - print "---------------------------------\n"; - print "label addr uses\n"; - print "---------------------------------\n"; - - %hist_labels; - $hist_labels{$_}++ for @label_uses; - - foreach $label (keys %hist_labels){ - printf "%-20s %04x %d\n", $label, $labels{$label}, $hist_labels{$label}; - } -} - -sub bitfield_histogram { - - %hist_bitfields; - $hist_bitfields{$_}++ for @bitfields; - @unique_bitfields = keys %hist_bitfields; - - printf "\nbitfield usage (total: %d)\n", $#unique_bitfields; - print "------------------------------------------------\n"; - print "bitfield uses\n"; - print "------------------------------------------------\n"; - - foreach $bfield (sort sortFieldsByFrequency(keys %hist_bitfields)){ - printf "%-32s %d\n", $bfield, $hist_bitfields{$bfield}; - } -} - -sub sortFieldsByFrequency { - $hist_bitfields{$b} <=> $hist_bitfields{$a}; -} - -sub process_extra_flags { - - $flags1 = ''; - $flags2 = ''; - - - # first, process flags produced by 1st field processing - if($uinst->{flags} =~ /#jsr/){ - if($flags2 ne ''){$error = 'incompatible flags'}; - $flags2 = '010'; - } - if($uinst->{flags} =~ /#tjsr/){ - if($flags2 ne ''){$error = 'incompatible flags'}; - $flags2 = '100'; - } - - $provisional_flags2 = substr($uinst->{field_0},3,3); - if($flags2 ne ''){ - if($provisional_flags2 ne '000'){ - $error = "flags incompatible with jsr/tjsr operation: " - .$provisional_flags2; - $num_errors++; - $uinst->{error} = $error; - } - else{ - substr($uinst->{field_0},3,3) = $flags2; - } - } - - if($uinst->{flags} =~ /#ld_al/){ - substr($uinst->{field1},7,1) = '1'; - } - if($uinst->{flags} =~ /#ld_addr/){ - substr($uinst->{field1},6,1) = '1'; - } - - if($uinst->{flags} =~ /#fp_c/){ - substr($uinst->{field1},22,2) = '01'; - } - if($uinst->{flags} =~ /#fp_r/){ - substr($uinst->{field1},22,2) = '10'; - } - if($uinst->{flags} =~ /#fp_rc/){ - substr($uinst->{field1},22,2) = '11'; - } - - -} - -sub process_flags { - - my $line = shift(@_); - - $line =~ s/#/##/; - $line =~ /(.*)#(#.*)/; - - $flags1 = ''; - $flags2 = ''; - - - if($1 ne ''){ - $line_without_flags = $1; - $flag_str = $2; - - @flags = split /,/, $flag_str; - $error = ''; - - if($flag_str =~ /#end/){ - if($flags2 ne ''){$error = 'incompatible flags'}; - $flags2 = '001'; - } - if($flag_str =~ /#ret/){ - if($flags2 ne ''){$error = 'incompatible flags'}; - $flags2 = '011'; - } - if($flag_str =~ /#rd/){ - if($flags2 ne ''){$error = 'incompatible flags'}; - $flags2 = '101'; - } - if($flag_str =~ /#wr/){ - if($flags2 ne ''){$error = 'incompatible flags'}; - $flags2 = '110'; - } - if($flag_str =~ /#auxcy/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '101'; - } - - if($flag_str =~ /#decode/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '001'; - } - if($flag_str =~ /#clrt1/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '110'; - } - if($flag_str =~ /#halt/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '111'; - } - if($flag_str =~ /#di/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '010'; - } - if($flag_str =~ /#ei/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '011'; - } - if($flag_str =~ /#io/){ - if($flags1 ne ''){$error = 'incompatible flags'}; - $flags1 = '100'; - } - if($flag_str =~ /#setacy/){ - if($flags2 ne ''){$error = 'incompatible flags:'.$flags2}; - $flags2 = '111'; - } - - if($flags2 eq ''){ $flags2 = '000';}; - if($flags1 eq ''){ $flags1 = '000';}; - - $uinst->{field_0} = $flags1.$flags2; - - # Some of the flags must be processed after the rest of the uinst - # has been assembled; save them into $uinst->{flags} for later. - - if($flag_str =~ /#ld_al/){ - $uinst->{flags} = $uinst->{flags}." #ld_al"; - } - if($flag_str =~ /#ld_addr/){ - $uinst->{flags} = $uinst->{flags}." #ld_addr"; - } - if($flag_str =~ /#fp_c/){ - $uinst->{flags} = $uinst->{flags}." #fp_c"; - } - if($flag_str =~ /#fp_r/){ - $uinst->{flags} = $uinst->{flags}." #fp_r"; - } - if($flag_str =~ /#fp_rc/){ - $uinst->{flags} = $uinst->{flags}." #fp_rc"; - } - - if($error ne ''){ - $num_errors++; - $uinst->{error} = $error; - }; - - return $line_without_flags; - } - - return $line; -} - - -sub process_field2 { - my $field = shift(@_).";"; - - $field =~ s/^\s*//g; - $field =~ s/\s*;//g; - $field =~ s/\s+/ /g; - - $field =~ s/A-Z/a-z/g; - - - # check for special field2 formats: nop - if($field =~ /(nop)/){ - # field2 is nop by default - return 0; - } - - - if($field =~ /(_\w+|{p}0|{p}1|{d}|{s}|do) = (\w+|t1)/){ - - #check that dst address is the same as field1's src address - #(since they end up being the same physical bits) - @parts = split /=/, $field; - $dst = $parts[0]; - $dst =~ s/\s//g; - if(($dst ne $uinst->{src}) - && ($dst ne 'do') - && ($uinst->{src} ne 'di') - && ($uinst->{src} ne '')){ - # field mismatch - $num_errors++; - $uinst->{error} = "field source/destination address mismatch"; - return 1; - } - else{ - # build bitfield for field2, including those bits that overlap - # bits from field 1 - - if($dst eq 'do'){ - substr($uinst->{field1}, 24, 1) = '1'; #ld_do - } - else{ - substr($uinst->{field1}, 25, 1) = '1'; #ld_reg - - if($dst eq '{p}0'){ - substr($uinst->{field1}, 11, 2) = '11'; - substr($uinst->{field1}, 13, 4) = '0000'; - } - elsif($dst eq '{p}1'){ - substr($uinst->{field1}, 11, 2) = '11'; - substr($uinst->{field1}, 13, 4) = '0001'; - } - elsif($dst eq '{d}'){ - substr($uinst->{field1}, 11, 2) = '10'; - substr($uinst->{field1}, 13, 4) = '0000'; - } - elsif($dst eq '{s}'){ - substr($uinst->{field1}, 11, 2) = '01'; - substr($uinst->{field1}, 13, 4) = '0000'; - } - else{ - %regs = ( '_b',0, '_c',1, '_d',2, '_e',3, - '_h',4, '_l',5, '_f',6, '_a',7, - '_ph',8, '_pl',9, '_x',10, '_y',11, - '_z',12, '_w',13, '_sh',14, '_sl',15); - - $val_reg = to_bin($regs{$dst},4); - substr($uinst->{field1}, 11, 2) = '00'; - substr($uinst->{field1}, 13, 4) = $val_reg; # RD address; same as WR - } - - } - - # TODO deal with flag pattern - $parts[1] =~ s/\s//g; - $src = $field2_ops{$parts[1]}.''; - if($src eq ''){ - $num_errors++; - $uinst->{error} = "field 2 operation unknown: [".$parts[1]."]"; - return 1; - } - else{ - substr($uinst->{field1},26,6) = $src; - return 0; - } - } - - } - elsif($field =~ /(sec|cpc)/){ - substr($uinst->{field1},26,6) = $field2_ops{$1}; - } - else{ - # field2 empty or invalid - $num_errors++; - $uinst->{error} = "field 2 empty or invalid: ".$re_field2; - return 1; - } - -} - - - -# return !=0 when uinst is finished except for flags, -# 0 when field2 has to be processed - -sub process_field1 { - - my $field = shift(@_).";"; - - $field =~ s/^\s*//g; - $field =~ s/\s*;//g; - $field =~ s/\s+/ /g; - - # look for special format uinsts: jsr, tjsr, nop - if($field =~ /(jsr|tjsr)\s+([_\w]+)/){ - $opcode = $1; - $target = $2; - # set flag - $uinst->{flags} = $uinst->{flags}." #".$opcode." "; - - # check that target is defined, otherwise tag it for 2nd pass - $target_addr = $labels{$target}; - - tag_label_use($target, $addr); - - if($target_addr eq ''){ - push @undefined_targets, [$target, $addr]; - $code = $field1_ops{$opcode}; - $uinst->{field1} = $code; - } - else{ - # set up bitfield so we can fill the address in in 2nd pass - $code = $field1_ops{$opcode}; - $a = to_bin($target_addr+0, 8); - substr($code, 20,2, substr($a, 0,2)); - substr($code, 26,6, substr($a, 2,6)); - $uinst->{field1} = $code; - } - return 1; - } - - if($field =~ /nop/){ - # TODO encode NOP as 1st field - $uinst->{field1} = $field1_ops{'nop'}; - return 0; - } - - # process regular field1 (register load): dst = src - - if($field =~ /$re_field1/){ - @parts = split /=/, $field; - - # if a src reg address literal is specified, it has to be the same - # address as for field2 dest; save it for later comparison. - - $src = $parts[1]; - $src =~ s/\s//g; - - $d = $field1_ops{$field}.''; - - if($d eq ''){ - # unrecognized source that somehow matches pattern (e.g. _pl0) - $error = "invalid source in uinst field 1"; - $uinst->{field1} = $field1_ops{'nop'}; - $uinst->{error} = $error; - $num_errors++; - $uinst->{src} = '?'; - return 1; - } - else{ - $uinst->{src} = $src; - $uinst->{field1} = $d; - } - return 0; - } - else{ - # field1 not recognized. - $error = "uinst field 1 not recognized: '".$field."'"; - $uinst->{field1} = $field1_ops{'nop'}; - $uinst->{error} = $error; - $num_errors++; - return 1; - } - -} - -sub tag_label_use { - - my $label = shift(@_); - my $address = shift(@_); - - push(@label_uses, $label); - -} - -sub to_bin { - my $number = shift(@_) * 1; - my $length = shift(@_); - - $n = $number; - $r = ''; - for( my $i=$length-1;$i>=0;$i--){ - $d = 2 ** $i; - - if($n >= $d){ - $r = $r.'1'; - $n = $n - $d; - } - else{ - $r = $r.'0'; - } - } - - return $r; -} - -# End of file \ No newline at end of file Index: light8080/trunk/util/uasm.pl =================================================================== --- light8080/trunk/util/uasm.pl (nonexistent) +++ light8080/trunk/util/uasm.pl (revision 31) @@ -0,0 +1,892 @@ +################################################################################ +# uasm.pl : light8080 core microcode assembler +################################################################################ +# Usage: perl uasm.pl +# +# The command list is a space-separated sequence of the following: +# +# -lst : Shows a listing of the assembled microinstructions next to their +# assembler source lines. Not very useful because it does not show +# assembler pragma, label or comment lines. +# -labels : Shows a list of all defined labels with their address and the +# number of times they are used. +# -bitfields: Shows a list of all the different microinstructions generated, +# plus the number of times they are used. Might be useful to encode +# the microinstructions and save rom bits. +# -instructions: Shows a list of all defined instructions with the address their +# microcode starts at. +# -rom_bin : Shows a raw list of all the binary microinstructions. +# -rom_vhdl : Shows a vhdl block containing the microcode rom declaration. +# +# If none of the above commands is given, the program just exits silently. Any +# unrecognized command is silently ignored. +################################################################################ +# Assembler format (informal definition, source is the ultimate reference!): +# +# := +# [] | (*1) +# ; [; []] | +# JSR |TJSR +# +# := {':' immediately followed by a common identifier} +# := {an identifier defined as label anywhere in the file} +# := = | NOP +# := T1 | T2 +# := | DI | +# := {s}|{d}|{p}0|{p}1 (*3) +# := _a|_b|_c|_d|_e|_h|_l|_f|_a|_ph|_pl|_x|_y|_z|_w|_sh|_sl| +# := = | NOP +# := | DO +# := add|adc|sub|sbb| and|orl|not|xrl| rla|rra|rlca|rrca| aaa| +# t1|rst|daa|cpc|sec|psw +# := [, ...] +# := #decode|#di|#ei|#io|#auxcy|#clrt1|#halt|#end|#ret|#rd|#wr|#setacy +# #ld_al|#ld_addr|#fp_c|#fp_r|#fp_rc (*2) +# +# *1 Labels appear alone by themselves in a line +# *2 There are some restrictions on the flags that can be used together +# *3 Registers are specified by IR field +# +################################################################################ +# ALU operations +# +#Operation Encoding ALU result +#=============================================================================== +#ADD 001100 T2 + T1 +#ADC 001101 T2 + T1 + CY +#SUB 001110 T2 - T1 +#SBB 001111 T2 � T1 - CY +#AND 000100 T1 AND T2 +#ORL 000101 T1 OR T2 +#NOT 000110 NOT T1 +#XRL 000111 T1 XOR T2 +#RLA 000000 8080 RLC +#RRA 000001 8080 RRC +#RLCA 000010 8080 RAL +#RRCA 000011 8080 RAR +#T1 010111 T1 +#RST 011111 8*IR(5..3), as per RST instruction +#DAA 101000 DAA T1 (but only after executing 2 in a row) +#CPC 101100 UNDEFINED (CY complemented) +#SEC 101101 UNDEFINED (CY set) +################################################################################ +# Flags : +# --- Flags from group 1: use only one of these +# #decode : Load address counter and IR with contents of data input lines, +# thus starting opcode decoging. +# #ei : Set interrupt enable register. +# #di : Reset interrupt enable register. +# #io : Activate io signal for 1st cycle. +# #auxcy : Use aux carry instead of regular carry for this operation. +# #clrt1 : Clear T1 at the end of 1st cycle. +# #halt : Jump to microcode address 0x07 without saving return value. +# +# --- Flags from group 2: use only one of these +# #setacy : Set aux carry at the start of 1st cycle (used for ++). +# #end : Jump to microinstruction address 3 after the present m.i. +# #ret : Jump to address saved by the last JST or TJSR m.i. +# #rd : Activate rd signal for the 2nd cycle. +# #wr : Activate wr signal for the 2nd cycle. +# --- Independent flags: no restrictions +# #ld_al : Load AL register with register bank output as read by operation 1. +# (used in memory and io access). +# #ld_addr : Load address register (H byte = register bank output as read by +# operation 1, L byte = AL). +# Activate vma signal for 1st cycle. +# --- PSW update flags: use only one of these +# #fp_r : This instruction updates all PSW flags except for C. +# #fp_c : This instruction updates only the C flag in the PSW. +# #fp_rc : This instruction updates all the flags in the PSW. +################################################################################ +# Read the design notes for a brief reference to the micromachine internal +# behavior, including implicit loads/erases. +################################################################################ + +$file = shift(@ARGV); + +open(INFO, $file) or die "unable to open file '$file'\n"; +@lines = ; +close(INFO); + +$field2_nop = '0'.'0000'.'00'.'0'.'0'.'000000'; +$field2_jsr = '0'.'0000'.'00'.'0'.'0'.'000000'; + +%field1_ops = + ( 'nop', '000'.'000'.'00000'.'00'.'0000'.$field2_nop, + 'jsr', '000'.'010'.'00000'.'00'.'0000'.$field2_jsr, + 'tjsr', '000'.'100'.'00000'.'00'.'0000'.$field2_jsr, + + 't1 = {s}', '000'.'000'.'00101'.'01'.'0000'.$field2_nop, + 't1 = {d}', '000'.'000'.'00101'.'10'.'0000'.$field2_nop, + 't1 = {p}0', '000'.'000'.'00101'.'11'.'0000'.$field2_nop, + 't1 = {p}1', '000'.'000'.'00101'.'11'.'0001'.$field2_nop, + 't1 = di', '000'.'000'.'00100'.'00'.'0000'.$field2_nop, + 't1 = _b', '000'.'000'.'00101'.'00'.'0000'.$field2_nop, + 't1 = _c', '000'.'000'.'00101'.'00'.'0001'.$field2_nop, + 't1 = _d', '000'.'000'.'00101'.'00'.'0010'.$field2_nop, + 't1 = _e', '000'.'000'.'00101'.'00'.'0011'.$field2_nop, + 't1 = _h', '000'.'000'.'00101'.'00'.'0100'.$field2_nop, + 't1 = _l', '000'.'000'.'00101'.'00'.'0101'.$field2_nop, + 't1 = _a', '000'.'000'.'00101'.'00'.'0111'.$field2_nop, + 't1 = _f', '000'.'000'.'00101'.'00'.'0110'.$field2_nop, + 't1 = _ph', '000'.'000'.'00101'.'00'.'1000'.$field2_nop, + 't1 = _pl', '000'.'000'.'00101'.'00'.'1001'.$field2_nop, + 't1 = _x', '000'.'000'.'00101'.'00'.'1010'.$field2_nop, + 't1 = _y', '000'.'000'.'00101'.'00'.'1011'.$field2_nop, + 't1 = _z', '000'.'000'.'00101'.'00'.'1100'.$field2_nop, + 't1 = _w', '000'.'000'.'00101'.'00'.'1101'.$field2_nop, + 't1 = _sh', '000'.'000'.'00101'.'00'.'1110'.$field2_nop, + 't1 = _sl', '000'.'000'.'00101'.'00'.'1111'.$field2_nop, + + 't2 = {s}', '000'.'000'.'00011'.'01'.'0000'.$field2_nop, + 't2 = {d}', '000'.'000'.'00011'.'10'.'0000'.$field2_nop, + 't2 = {p}0', '000'.'000'.'00011'.'11'.'0000'.$field2_nop, + 't2 = {p}1', '000'.'000'.'00011'.'11'.'0001'.$field2_nop, + 't2 = di', '000'.'000'.'00010'.'00'.'0000'.$field2_nop, + 't2 = _b', '000'.'000'.'00011'.'00'.'0000'.$field2_nop, + 't2 = _c', '000'.'000'.'00011'.'00'.'0001'.$field2_nop, + 't2 = _d', '000'.'000'.'00011'.'00'.'0010'.$field2_nop, + 't2 = _e', '000'.'000'.'00011'.'00'.'0011'.$field2_nop, + 't2 = _h', '000'.'000'.'00011'.'00'.'0100'.$field2_nop, + 't2 = _l', '000'.'000'.'00011'.'00'.'0101'.$field2_nop, + 't2 = _a', '000'.'000'.'00011'.'00'.'0111'.$field2_nop, + 't2 = _f', '000'.'000'.'00011'.'00'.'0110'.$field2_nop, + 't2 = _ph', '000'.'000'.'00011'.'00'.'1000'.$field2_nop, + 't2 = _pl', '000'.'000'.'00011'.'00'.'1001'.$field2_nop, + 't2 = _x', '000'.'000'.'00011'.'00'.'1010'.$field2_nop, + 't2 = _y', '000'.'000'.'00011'.'00'.'1011'.$field2_nop, + 't2 = _z', '000'.'000'.'00011'.'00'.'1100'.$field2_nop, + 't2 = _w', '000'.'000'.'00011'.'00'.'1101'.$field2_nop, + 't2 = _sh', '000'.'000'.'00011'.'00'.'1110'.$field2_nop, + 't2 = _sl', '000'.'000'.'00011'.'00'.'1111'.$field2_nop + + ); + + +$re_field1 = "(".join('|',keys %field1_ops).")"; +$re_field1 =~ s/\[/\\\[/g; +$re_field1 =~ s/\]/\\\]/g; + +%field2_ops = + ( 'add', '001100', + 'adc', '001101', + 'sub', '001110', + 'sbb', '001111', + + 'and', '000100', + 'orl', '000110', + 'not', '000111', + 'xrl', '000101', + + 'rla', '000000', + 'rra', '000001', + 'rlca', '000010', + 'rrca', '000011', + + 'aaa', '111000', + + 't1', '010111', + 'rst', '011111', + 'daa', '101000', + 'cpc', '101100', + 'sec', '101101', + 'psw', '110000' + ); + + +$re_f2_ops = "(".join('|',keys %field2_ops).")"; +$re_f2_ops =~ s/\[/\\\[/g; +$re_f2_ops =~ s/\]/\\\]/g; + +# 'parse' command line flags into a string +$cmdline = join ':', @ARGV; + +$num_line = 0; +$addr = 0; + +%labels = (); # +@label_uses = (); # +@undefined_targets = (); # array of +$num_errors = 0; + +@bitfields = (); + +@rom = (); +@asm = (); +@errors = (); +@num_lines = (); + +%asm_to_uaddr = (); # opcode asm -> uaddress +%uaddr_to_asm = (); # uaddress -> opcode asm + +%uaddr_to_pattern = (); # uaddress -> pattern +%pattern_to_uaddr = (); # pattern -> uaddress -- simulation, decoder + +LINE: foreach $line (@lines) { + + $num_line++; + + $line =~ tr/A-Z/a-z/; + $line =~ s/(--|\/\/).*//; + $line =~ s/^\s*//g; + $line =~ s/\s*\$//g; + chomp($line); + + $uinst = { + field_1 => '', + src => '', + special => '', + field_2 => '', + field_0 => '000000', + flags => '', + error => '', + asm => $line + }; + + + # if line is whitespace or comment (which has been changed to whitespace) + # then skip to next line + if($line eq ''){ + next; + } + + # if $line is a label declaration, get it and skip to next line + # note labels come alone in the line, unlike other assemblers + # TODO it'd be simple to change this... + if($line =~ /^\s*:(\w+)/){ + # subroutine label (labels are only used for jsrs) + $labels{$1} = $addr; + next; + } + + # if line is a pragma, process it + if($line =~ /^\s*__/){ + # TODO process pragmas __reset, __fetch, __int + + #if($line =~ /^\s*__code\s+"([0|1|s|d|p|a|r]+)"/){ + # we do nothing with the opcode byte; it's for reference only + #printf "%04d # %s\n",$addr,$1; + #} + if($line =~ /^\s*__asm\s+(.*)/){ + # save the start address for the CPU instruction + # it will be used in the design of the decoder + $asm_to_uaddr{$1} = $addr; + $uaddr_to_asm{$addr} = $1; + } + + if($line =~ /^\s*__code\s+"(.*)".*/){ + # save the start address for the CPU instruction + # it will be used in the design of the decoder + $pattern_to_uaddr{$1} = $addr; + $uaddr_to_pattern{$addr} = $1; + } + + + next; + } + + # get flags field (all text following 1st '#' included) + # remove it so we're left with 'field1 ; field2 [;]' + $line = process_flags($line); + + # break line in 1 or 2 fields + @fields = split /;/, $line; + + # process 1st field... + $done = process_field1($fields[0]); + + # ...and process 2nd field if there is one (depends on field1 format) + # TODO check that there's no field2 when there shouldn't + if($done != 1){ + $done = process_field2($fields[1]); + } + + # finally, process extra flags produced by field1 assembly (jsr/tjsr) + process_extra_flags(); + + # complete bitfield with flags... + substr($uinst->{field1}, 0, 6) = $uinst->{field_0}; + + # Now, we already have the bitfields. + + push(@rom, $uinst->{field1}); + push(@asm, substr($line,0,40)); + push(@num_lines, $num_line); + if($uinst->{error} eq ''){ + push(@errors, ''); + } + else{ + push(@errors, $uinst->{error}); + } + + $addr++; #addr++ even for error uinsts + +} +continue { +} + +# Line processing finished (1st pass). Start 2nd pass and do listings +# if requested + +# 2nd pass + +# now we know the value of all labels, fill in address field of forward jumps +foreach $target (@undefined_targets){ + @item = @{$target}; + $value = to_bin($labels{$item[0]}, 8); + $adr = $item[1]*1; + + substr($rom[$adr], 20,2, substr($value, 0,2)); + substr($rom[$adr], 26,6, substr($value, 2,6)); +} + +foreach $bf (@rom){ + push(@bitfields, $bf); +} + +# listings + +if($cmdline =~ /-lst/){ + $do_lst = 1; +} + +$i = 0; +foreach $bf (@rom){ + if($do_lst){ + printf "%02x %32s :: %s\n", $i, $bf, $asm[$i]; + if($errors[$i] ne ''){ + printf " ERROR (%d): %s\n", $num_lines[$i], $errors[$i]; + } + } + + $i++; +} + +if($do_lst){ + # completion message + printf "\nDone. %d uinsts, %d errors.\n", $addr, $num_errors; +} + +# label listing +if($cmdline =~ /\-labels/){ + label_list(); +} + +# bitfield histogram +if($cmdline =~ /\-bitfields/){ + bitfield_histogram(); +} + +# show cpu instruction microcode addresses +if($cmdline =~ /\-instructions/){ + foreach $asm (sort {$asm_to_uaddr{$a} <=> $asm_to_uaddr{$b}}(keys %asm_to_uaddr)){ + $uaddress = $asm_to_uaddr{$asm}; + printf "%02x %s %s\n", $uaddress, $uaddr_to_pattern{$uaddress}, $asm; + } +} + +if($cmdline =~ /\-rom_vhdl/){ + show_decoder_table('vhdl'); +} + +if($cmdline =~ /\-rom_bin/){ + show_decoder_table('bin'); +} + +# end of main program + + +################################################################################ + + +sub show_decoder_table { + + my $fmat = shift(@_); + + # show decoder rom contents + %decoder_hash = (); + foreach $pat (keys %pattern_to_uaddr){ + $add = $pattern_to_uaddr{$pat}; + $pat =~ s/[a-z]/\[01\]/g; + $decoder_hash{$pat} = $add; + } + + @decoder_rom = (); + for($i = 0; $i<256; $i++){ + $b = to_bin($i, 8); + $val = 0; + # We'll match the opcode to the pattern with the shortest length; that is, + # the one with the less wildcards in it. Crude but effective in this case. + $len_matched_pat = 1000; + foreach $pat (keys %decoder_hash){ + if($b =~ /$pat/){ + if(length($pat) < $len_matched_pat){ + $val = $decoder_hash{$pat}; + $len_matched_pat = length($pat); + } + #last; + } + } + push @decoder_rom, $val; + } + + if($fmat eq 'vhdl'){ + # print rom vhdl header... + print "type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);\n"; + print "signal rom : t_rom := (\n"; + } + + # The 1st half of the uinst rom holds 256 uinstructions + my $i=0; + foreach $bf (@rom){ + if($fmat eq 'vhdl'){ + printf "\"%s\", -- %03x\n", $bf, $i; + } + else{ + printf "%s\n", $bf; + } + $i++; + } + # Fill remaining slots with ENDs + for(;$i<256;$i++){ + my $val = '00000100000000000000000000000000'; + if($fmat eq 'vhdl'){ + printf "\"%s\", -- %03x\n", $val, $i; + } + else{ + printf "%s\n", $val; + } + } + + # The 2nd half (upper 256 entries) of the ucode rom contains a jump table + # with a jsr for each of the 256 opcodes, serving as cheap decoder: + foreach $entry (@decoder_rom){ + my $val = to_bin($entry, 8); + $val = '00001000000000000000'.substr($val,0,2).'0000'.substr($val,2,6); + $i++; + if($fmat eq 'vhdl'){ + printf "\"%s\"", $val; + if($i<512){ + print ","; + } + else{ + print " "; + } + printf " -- %03x\n", ($i - 1); + } + else{ + printf "%s\n", $val; + } + } + + if($fmat eq 'vhdl'){ + # close vhdl declaration + print "\n);\n"; + } + +} + +sub label_list { + # label table listing + print "\nlabels:\n"; + print "---------------------------------\n"; + print "label addr uses\n"; + print "---------------------------------\n"; + + %hist_labels; + $hist_labels{$_}++ for @label_uses; + + foreach $label (keys %hist_labels){ + printf "%-20s %04x %d\n", $label, $labels{$label}, $hist_labels{$label}; + } +} + +sub bitfield_histogram { + + %hist_bitfields; + $hist_bitfields{$_}++ for @bitfields; + @unique_bitfields = keys %hist_bitfields; + + printf "\nbitfield usage (total: %d)\n", $#unique_bitfields; + print "------------------------------------------------\n"; + print "bitfield uses\n"; + print "------------------------------------------------\n"; + + foreach $bfield (sort sortFieldsByFrequency(keys %hist_bitfields)){ + printf "%-32s %d\n", $bfield, $hist_bitfields{$bfield}; + } +} + +sub sortFieldsByFrequency { + $hist_bitfields{$b} <=> $hist_bitfields{$a}; +} + +sub process_extra_flags { + + $flags1 = ''; + $flags2 = ''; + + + # first, process flags produced by 1st field processing + if($uinst->{flags} =~ /#jsr/){ + if($flags2 ne ''){$error = 'incompatible flags'}; + $flags2 = '010'; + } + if($uinst->{flags} =~ /#tjsr/){ + if($flags2 ne ''){$error = 'incompatible flags'}; + $flags2 = '100'; + } + + $provisional_flags2 = substr($uinst->{field_0},3,3); + if($flags2 ne ''){ + if($provisional_flags2 ne '000'){ + $error = "flags incompatible with jsr/tjsr operation: " + .$provisional_flags2; + $num_errors++; + $uinst->{error} = $error; + } + else{ + substr($uinst->{field_0},3,3) = $flags2; + } + } + + if($uinst->{flags} =~ /#ld_al/){ + substr($uinst->{field1},7,1) = '1'; + } + if($uinst->{flags} =~ /#ld_addr/){ + substr($uinst->{field1},6,1) = '1'; + } + + if($uinst->{flags} =~ /#fp_c/){ + substr($uinst->{field1},22,2) = '01'; + } + if($uinst->{flags} =~ /#fp_r/){ + substr($uinst->{field1},22,2) = '10'; + } + if($uinst->{flags} =~ /#fp_rc/){ + substr($uinst->{field1},22,2) = '11'; + } + + +} + +sub process_flags { + + my $line = shift(@_); + + $line =~ s/#/##/; + $line =~ /(.*)#(#.*)/; + + $flags1 = ''; + $flags2 = ''; + + + if($1 ne ''){ + $line_without_flags = $1; + $flag_str = $2; + + @flags = split /,/, $flag_str; + $error = ''; + + if($flag_str =~ /#end/){ + if($flags2 ne ''){$error = 'incompatible flags'}; + $flags2 = '001'; + } + if($flag_str =~ /#ret/){ + if($flags2 ne ''){$error = 'incompatible flags'}; + $flags2 = '011'; + } + if($flag_str =~ /#rd/){ + if($flags2 ne ''){$error = 'incompatible flags'}; + $flags2 = '101'; + } + if($flag_str =~ /#wr/){ + if($flags2 ne ''){$error = 'incompatible flags'}; + $flags2 = '110'; + } + if($flag_str =~ /#auxcy/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '101'; + } + + if($flag_str =~ /#decode/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '001'; + } + if($flag_str =~ /#clrt1/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '110'; + } + if($flag_str =~ /#halt/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '111'; + } + if($flag_str =~ /#di/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '010'; + } + if($flag_str =~ /#ei/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '011'; + } + if($flag_str =~ /#io/){ + if($flags1 ne ''){$error = 'incompatible flags'}; + $flags1 = '100'; + } + if($flag_str =~ /#setacy/){ + if($flags2 ne ''){$error = 'incompatible flags:'.$flags2}; + $flags2 = '111'; + } + + if($flags2 eq ''){ $flags2 = '000';}; + if($flags1 eq ''){ $flags1 = '000';}; + + $uinst->{field_0} = $flags1.$flags2; + + # Some of the flags must be processed after the rest of the uinst + # has been assembled; save them into $uinst->{flags} for later. + + if($flag_str =~ /#ld_al/){ + $uinst->{flags} = $uinst->{flags}." #ld_al"; + } + if($flag_str =~ /#ld_addr/){ + $uinst->{flags} = $uinst->{flags}." #ld_addr"; + } + if($flag_str =~ /#fp_c/){ + $uinst->{flags} = $uinst->{flags}." #fp_c"; + } + if($flag_str =~ /#fp_r/){ + $uinst->{flags} = $uinst->{flags}." #fp_r"; + } + if($flag_str =~ /#fp_rc/){ + $uinst->{flags} = $uinst->{flags}." #fp_rc"; + } + + if($error ne ''){ + $num_errors++; + $uinst->{error} = $error; + }; + + return $line_without_flags; + } + + return $line; +} + + +sub process_field2 { + my $field = shift(@_).";"; + + $field =~ s/^\s*//g; + $field =~ s/\s*;//g; + $field =~ s/\s+/ /g; + + $field =~ s/A-Z/a-z/g; + + + # check for special field2 formats: nop + if($field =~ /(nop)/){ + # field2 is nop by default + return 0; + } + + + if($field =~ /(_\w+|{p}0|{p}1|{d}|{s}|do) = (\w+|t1)/){ + + #check that dst address is the same as field1's src address + #(since they end up being the same physical bits) + @parts = split /=/, $field; + $dst = $parts[0]; + $dst =~ s/\s//g; + if(($dst ne $uinst->{src}) + && ($dst ne 'do') + && ($uinst->{src} ne 'di') + && ($uinst->{src} ne '')){ + # field mismatch + $num_errors++; + $uinst->{error} = "field source/destination address mismatch"; + return 1; + } + else{ + # build bitfield for field2, including those bits that overlap + # bits from field 1 + + if($dst eq 'do'){ + substr($uinst->{field1}, 24, 1) = '1'; #ld_do + } + else{ + substr($uinst->{field1}, 25, 1) = '1'; #ld_reg + + if($dst eq '{p}0'){ + substr($uinst->{field1}, 11, 2) = '11'; + substr($uinst->{field1}, 13, 4) = '0000'; + } + elsif($dst eq '{p}1'){ + substr($uinst->{field1}, 11, 2) = '11'; + substr($uinst->{field1}, 13, 4) = '0001'; + } + elsif($dst eq '{d}'){ + substr($uinst->{field1}, 11, 2) = '10'; + substr($uinst->{field1}, 13, 4) = '0000'; + } + elsif($dst eq '{s}'){ + substr($uinst->{field1}, 11, 2) = '01'; + substr($uinst->{field1}, 13, 4) = '0000'; + } + else{ + %regs = ( '_b',0, '_c',1, '_d',2, '_e',3, + '_h',4, '_l',5, '_f',6, '_a',7, + '_ph',8, '_pl',9, '_x',10, '_y',11, + '_z',12, '_w',13, '_sh',14, '_sl',15); + + $val_reg = to_bin($regs{$dst},4); + substr($uinst->{field1}, 11, 2) = '00'; + substr($uinst->{field1}, 13, 4) = $val_reg; # RD address; same as WR + } + + } + + # TODO deal with flag pattern + $parts[1] =~ s/\s//g; + $src = $field2_ops{$parts[1]}.''; + if($src eq ''){ + $num_errors++; + $uinst->{error} = "field 2 operation unknown: [".$parts[1]."]"; + return 1; + } + else{ + substr($uinst->{field1},26,6) = $src; + return 0; + } + } + + } + elsif($field =~ /(sec|cpc)/){ + substr($uinst->{field1},26,6) = $field2_ops{$1}; + } + else{ + # field2 empty or invalid + $num_errors++; + $uinst->{error} = "field 2 empty or invalid: ".$re_field2; + return 1; + } + +} + + + +# return !=0 when uinst is finished except for flags, +# 0 when field2 has to be processed + +sub process_field1 { + + my $field = shift(@_).";"; + + $field =~ s/^\s*//g; + $field =~ s/\s*;//g; + $field =~ s/\s+/ /g; + + # look for special format uinsts: jsr, tjsr, nop + if($field =~ /(jsr|tjsr)\s+([_\w]+)/){ + $opcode = $1; + $target = $2; + # set flag + $uinst->{flags} = $uinst->{flags}." #".$opcode." "; + + # check that target is defined, otherwise tag it for 2nd pass + $target_addr = $labels{$target}; + + tag_label_use($target, $addr); + + if($target_addr eq ''){ + push @undefined_targets, [$target, $addr]; + $code = $field1_ops{$opcode}; + $uinst->{field1} = $code; + } + else{ + # set up bitfield so we can fill the address in in 2nd pass + $code = $field1_ops{$opcode}; + $a = to_bin($target_addr+0, 8); + substr($code, 20,2, substr($a, 0,2)); + substr($code, 26,6, substr($a, 2,6)); + $uinst->{field1} = $code; + } + return 1; + } + + if($field =~ /nop/){ + # TODO encode NOP as 1st field + $uinst->{field1} = $field1_ops{'nop'}; + return 0; + } + + # process regular field1 (register load): dst = src + + if($field =~ /$re_field1/){ + @parts = split /=/, $field; + + # if a src reg address literal is specified, it has to be the same + # address as for field2 dest; save it for later comparison. + + $src = $parts[1]; + $src =~ s/\s//g; + + $d = $field1_ops{$field}.''; + + if($d eq ''){ + # unrecognized source that somehow matches pattern (e.g. _pl0) + $error = "invalid source in uinst field 1"; + $uinst->{field1} = $field1_ops{'nop'}; + $uinst->{error} = $error; + $num_errors++; + $uinst->{src} = '?'; + return 1; + } + else{ + $uinst->{src} = $src; + $uinst->{field1} = $d; + } + return 0; + } + else{ + # field1 not recognized. + $error = "uinst field 1 not recognized: '".$field."'"; + $uinst->{field1} = $field1_ops{'nop'}; + $uinst->{error} = $error; + $num_errors++; + return 1; + } + +} + +sub tag_label_use { + + my $label = shift(@_); + my $address = shift(@_); + + push(@label_uses, $label); + +} + +sub to_bin { + my $number = shift(@_) * 1; + my $length = shift(@_); + + $n = $number; + $r = ''; + for( my $i=$length-1;$i>=0;$i--){ + $d = 2 ** $i; + + if($n >= $d){ + $r = $r.'1'; + $n = $n - $d; + } + else{ + $r = $r.'0'; + } + } + + return $r; +} + +# End of file \ No newline at end of file Index: light8080/trunk/util/microrom.bat =================================================================== --- light8080/trunk/util/microrom.bat (nonexistent) +++ light8080/trunk/util/microrom.bat (revision 31) @@ -0,0 +1 @@ +perl uasm.pl ..\ucode\light8080.m80 -rom_vhdl > ..\ucode\rom.txt \ No newline at end of file Index: light8080/trunk/readme.txt =================================================================== --- light8080/trunk/readme.txt (nonexistent) +++ light8080/trunk/readme.txt (revision 31) @@ -0,0 +1,35 @@ + +The test programs have been assembled with TASM (Telemark Cross Assembler), +a free assembler available for DOS and Linux. + + +FILE LIST +========== + +vhdl\light8080.vhdl Core source (single file) + +vhdl\test\light8080_tb0.vhdl Test bench 0 (Kelly test) +vhdl\test\light8080_tb1.vhdl Test bench 1 (Interrupts) + +vhdl\demo\cs2b_light8080_demo.vhd Demo for Cyclone 2 starter board +vhdl\demo\rs232_tx.vhdl Serial tx code for demo +vhdl\demo\rs232_rx.vhdl Serial rx code for demo +vhdl\demo\cs2b_demo.csv Pin assignment file for Quartus II + +util\uasm.pl Microcode assembler +util\microrom.bat Sample DOS bat file for assembler + +ucode\light8080.m80 Microcode source file + +synthesis\tb0_modelsim_wave.do Modelsim macro for test bench 0 +synthesis\tb1_modelsim_wave.do Modelsim macro for test bench 1 + +doc\designNotes.tex Core documentation in LaTeX format +doc\designNotes.pdf Core documentation in PDF format +doc\IMSAI SCS-1 Manual.pdf IMSAI SCS-1 original documentation + +asm\tb0.asm Test bench 0 program assembler source +asm\tb1.asm Test bench 1 program assembler source +asm\hexconv.pl Intel HEX to VHDL converter +asm\tasmtb.bat BATCH script to build the test benches +asm\readme.txt How to assemble the sources \ No newline at end of file Index: light8080/trunk/asm/readme.txt =================================================================== --- light8080/trunk/asm/readme.txt (nonexistent) +++ light8080/trunk/asm/readme.txt (revision 31) @@ -0,0 +1,23 @@ +The batch script tasmtb.bat will assemble the test bench source and then build a +VHDL test bench from the template tb_template.vhdl, with the assembled program +encoded in a simulated ROM. + +For example, to build the test bench 0 do: + +tasmtb tb0 + +The script assumes you have installed TASM in local/TASM. You may need to edit +the path to TASM in the script. +Besides, it uses the perl script hexconv.pl, so you need to have Perl installed +too. You can find them here: + +Telemark cross assembler (TASM): +http://home.comcast.net/~tasm/ + +Perl for windows (ActivePerl): +http://www.activestate.com/activeperl/ + +There are other versions of Perl for windows, this is the one I worked with. + +See more details about these test benches in the design notes and in the +sources. Index: light8080/trunk/asm/tasmtb.bat =================================================================== --- light8080/trunk/asm/tasmtb.bat (nonexistent) +++ light8080/trunk/asm/tasmtb.bat (revision 31) @@ -0,0 +1,14 @@ +@rem The only parameter is the file name of the assembly source file without +@rem extension or path (file has to be on the same dir as this script). +@set PROG=%1 +@rem Edit to point to the directory you installed TASM in +@set TASM_DIR=..\local\tasm +@rem remove output from previous assembly +@del %PROG%.hex +@del %PROG%.lst +@rem bring TASM 8080 table file to current directory or TASM will fail +@copy %TASM_DIR%\tasm85.tab . +%TASM_DIR%\tasm -85 -a %PROG%.asm %PROG%.hex %PROG%.lst +@rem +@rem FIXME template needs an overhaul +@perl hexconv.pl .\%PROG%.hex ..\vhdl\test\tb_template.vhdl 000 800 > ..\vhdl\test\light8080_%PROG%.vhdl \ No newline at end of file Index: light8080/trunk/asm/hexconv.pl =================================================================== --- light8080/trunk/asm/hexconv.pl (nonexistent) +++ light8080/trunk/asm/hexconv.pl (revision 31) @@ -0,0 +1,172 @@ +################################################################################ +# hexconv.pl -- inserts object code in HEX format into an VHDL template. +# +# This program reads an Intel HEX file with 8-bit object code and inserts it +# into a VHDL template, in the form of a VHDL std_logic_vector array +# initializer. This is meant to initialize FPGA ROM/RAM blocks with object code. +# When the program finds a template line which begins with "--@rom_data", it +# replaces the whole line with the VHDL table. +# When it finds the text @PROGNAME@ in a line, it replaces that text with the +# file name (without path or extension) of the hex file. +# Otherwise, it just copies the template to stdout verbatim. +# +# See usage details below, and examples in the BAT file in the asm directory. +################################################################################ + +$usage = "Use: hexconv.pl

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