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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/opencpu32/trunk/hdl/opencpu32/openCpu.vhd
54,6 → 54,7
clk : in STD_LOGIC; --! Main system clock
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
111,6 → 112,7
clk => clk,
FlagsDp => dataPathFlags,
DataDp => dataPathOutput,
outEnDp => enableOutputDp,
MuxDp => InputDataPathSelector,
MuxRegDp => InputDataPathAluASelector,
ImmDp => InputImediate,
/opencpu32/trunk/hdl/opencpu32/ControlUnit.vhd
22,6 → 22,7
clk : in STD_LOGIC; --! Main system clock
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
113,7 → 114,7
-- The high attribute points to the highes bit position
case opcodeIR is
when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg =>
when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg | ld_reg | ld_val | stom_reg | stom_val =>
nextCpuState <= execute;
cyclesExecute := 3; -- Wait 3 cycles for mov operation
currInstruction <= IR;
131,10 → 132,23
when execute =>
-- On the case of jump instructions, it's execution will be handled on this process
case opcodeIR is
when jmp_val =>
PC <= "0000000000" & operand_imm;
when jmpr_val =>
PC <= PC + ("0000000000" & operand_imm);
when ld_val =>
MemoryDataRdAddr <= "0000000000" & operand_imm;
MemoryDataReadEn <= '1';
-- STORE r1,10 (Store the value on r1 in the main memory located at address 10)
when stom_val =>
MemoryDataWrAddr <= "0000000000" & operand_imm;
MemoryDataWriteEn <= '1';
MemoryDataOut <= DataDp;
when others =>
null;
end case;
156,7 → 170,7
end case;
end process;
-- Process that handles the execution of each instruction (Excluding the call and jump instructions)
-- Process that handles the execution of each instruction (Excluding the call,jump,load,store instructions)
process (currentExState)
--variable operando1_reg : std_logic_vector(generalRegisters'range);
variable opcodeIR : std_logic_vector(5 downto 0);
182,6 → 196,22
DpRegFileReadEnB <= '1';
nextExState <= writeRegister;
-- LOAD r1,10 (Load into r1, the value in the main memory located at address 10)
when ld_val =>
MuxDp <= muxPos(fromMemory);
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
-- The part that interface with the memory is located on the first process
nextExState <= writeRegister;
-- STORE r1,10 (Store the value on r1 in the main memory located at address 10)
when stom_val =>
MuxDp <= muxPos(fromRegFileB);
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
DpRegFileReadEnB <= '1';
nextExState <= readRegisterB;
-- The part that interface with the memory is located on the first process
nextExState <= readRegisterB;
-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
MuxDp <= muxPos(fromAlu);
221,11 → 251,22
DpRegFileWriteEn <= '1';
nextExState <= releaseWriteRead;
when readRegisterB =>
DpRegFileReadEnB <= '1';
outEnDp <= enable;
nextExState <= releaseWriteRead;
when readRegisterA =>
DpRegFileReadEnA <= '1';
outEnDp <= enable;
nextExState <= releaseWriteRead;
-- Release lines (Reset Datapath lines to something that does nothing...)
when releaseWriteRead =>
DpRegFileReadEnB <= '0';
DpRegFileReadEnA <= '0';
DpRegFileWriteEn <= '0';
DpRegFileWriteEn <= '0';
outEnDp <= disable;
when others =>
null;
/opencpu32/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,32 → 8,8
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/Alu.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/ControlUnit.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/DataPath.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/Multiplexer3_1.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/Multiplexer4_1.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/RegisterFile.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/TriStateBuffer.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/openCpu.vhd&quot; into library work</arg>
</msg>
 
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/pkgOpenCPU32.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/opencpu32/trunk/hdl/opencpu32/pkgOpenCPU32.vhd
27,7 → 27,7
type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
type controlUnitStates is (initial, fetch, decode, execute, executing);
type executionStates is (initInstructionExecution, writeRegister, releaseWriteRead, s3, s4);
type executionStates is (initInstructionExecution, writeRegister, releaseWriteRead, readRegisterA, readRegisterB, releaseRead);
 
--! Flags positions
constant flag_sign : integer := 2;
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
223,31 → 223,31
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333971566">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6268642977942111103" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6268642977942111103" xil_pn:start_ts="1333982866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1333982866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333982866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5126426351813824259" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5126426351813824259" xil_pn:start_ts="1333982866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333982866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4767545221551224753" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4767545221551224753" xil_pn:start_ts="1333982866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333971575" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1333971566">
<transform xil_pn:end_ts="1333983326" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1333983316">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>

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