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Rev 30 → Rev 31

/raptor64/trunk/rtl/verilog/Raptor64_shift.v
0,0 → 1,75
`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
// __
// \\__/ o\ (C) 2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// Raptor64_shift.v
// - shift operations
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//=============================================================================
//
module Raptor64_shift(xIR, a, b, mask, o);
input [41:0] xIR;
input [63:0] a;
input [63:0] b;
input [63:0] mask;
output [63:0] o;
reg [63:0] o;
 
wire [6:0] xOpcode = xIR[41:35];
wire [6:0] xFunc = xIR[6:0];
wire [4:0] xFunc5 = xIR[4:0];
 
wire [127:0] shlxo = {64'd0,a} << b[5:0];
wire [127:0] shruxo = {a,64'd0} >> b[5:0];
wire [63:0] shlo = shlxo[63:0];
wire [63:0] shruo = shruxo[127:64];
wire [63:0] rolo = {shlxo[127:64]|shlxo[63:0]};
wire [63:0] roro = {shruxo[127:64]|shruxo[63:0]};
wire [63:0] shro = ~(~a >> b[5:0]);
 
always @(xOpcode,xFunc,xFunc5,shlo,shruo,rolo,roro,shro,mask)
case(xOpcode)
`RR:
case(xFunc)
`SHL: o = shlo;
`SHRU: o = shruo;
`ROL: o = rolo;
`ROR: o = roro;
`SHR: o = shro;
`ROLAM: o = rolo & mask;
default: o = 64'd0;
endcase
`SHFTI:
case(xFunc5)
`SHLI: o = shlo;
`SHRUI: o = shruo;
`ROLI: o = rolo;
`RORI: o = roro;
`SHRI: o = shro;
`ROLAMI: o = rolo & mask;
default: o = 64'd0;
endcase
default: o = 64'd0;
endcase
 
endmodule
/raptor64/trunk/rtl/verilog/Raptor64_bitfield.v
0,0 → 1,70
`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
// __
// \\__/ o\ (C) 2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// Raptor64_bitfield.v
// - bitfield datapath operations
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//=============================================================================
//
module Raptor64_bitfield(xIR, rolo, b, o, masko);
input [41:0] xIR;
input [63:0] rolo;
input [63:0] b;
output [63:0] o;
reg [63:0] o;
output [63:0] masko;
 
reg [63:0] o1;
wire [6:0] xOpcode = xIR[41:35];
wire [4:0] xFunc5 = xIR[4:0];
 
// generate mask
reg [63:0] mask;
assign masko = mask;
wire [5:0] mb = xIR[12:7];
wire [5:0] me = xIR[18:13];
integer nn,n;
always @(mb or me or nn)
for (nn = 0; nn < 64; nn = nn + 1)
mask[nn] <= (nn >= mb) ^ (nn <= me) ^ (me >= mb);
 
always @(xOpcode,xFunc5,mask,b,rolo,mb)
case (xOpcode)
`SHFTI:
case(xFunc5)
`BFINS: begin for (n = 0; n < 64; n = n + 1) o[n] = mask[n] ? rolo[n] : b[n]; end
`BFSET: begin for (n = 0; n < 64; n = n + 1) o[n] = mask[n] ? 1'b1 : b[n]; end
`BFCLR: begin for (n = 0; n < 64; n = n + 1) o[n] = mask[n] ? 1'b0 : b[n]; end
`BFCHG: begin for (n = 0; n < 64; n = n + 1) o[n] = mask[n] ? ~b[n] : b[n]; end
`BFEXT: begin
for (n = 0; n < 64; n = n + 1)
o1[n] = mask[n] ? b[n] : 1'b0;
o = o1 >> mb;
end
default: o = 64'd0;
endcase
default: o = 64'd0;
endcase
 
endmodule
/raptor64/trunk/rtl/verilog/Raptor64_set.v
0,0 → 1,77
`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
// __
// \\__/ o\ (C) 2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// Raptor64_set.v
// - set datapath operations
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//=============================================================================
//
module Raptor64_set(xIR, a, b, imm, o);
input [41:0] xIR;
input [63:0] a;
input [63:0] b;
input [63:0] imm;
output [63:0] o;
reg [63:0] o;
 
wire [6:0] xOpcode = xIR[41:35];
wire [6:0] xFunc = xIR[6:0];
 
wire eqi = a==imm;
wire lti = $signed(a) < $signed(imm);
wire ltui = a < imm;
wire eq = a==b;
wire lt = $signed(a) < $signed(b);
wire ltu = a < b;
 
always @(xOpcode,xFunc,eq,lt,ltu,eqi,lti,ltui)
case (xOpcode)
`RR:
case(xFunc)
`SEQ: o = eq;
`SNE: o = !eq;
`SLT: o = lt;
`SLE: o = lt|eq;
`SGT: o = !(lt|eq);
`SGE: o = !lt;
`SLTU: o = ltu;
`SLEU: o = ltu|eq;
`SGTU: o = !(ltu|eq);
`SGEU: o = !ltu;
default: o = 64'd0;
endcase
`SEQI: o = eqi;
`SNEI: o = !eqi;
`SLTI: o = lti;
`SLEI: o = lti|eqi;
`SGTI: o = !(lti|eqi);
`SGEI: o = !lti;
`SLTUI: o = ltui;
`SLEUI: o = ltui|eqi;
`SGTUI: o = !(ltui|eqi);
`SGEUI: o = !ltui;
default: o = 64'd0;
endcase
 
endmodule
/raptor64/trunk/rtl/verilog/Raptor64_opcodes.v
0,0 → 1,403
// ============================================================================
// __
// \\__/ o\ (C) 2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// Raptor64_opcodes.v
// - 64 bit CPU
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
// ============================================================================
 
`define MISC 7'd0
`define BRK 7'd0
`define IRQ 7'd1
`define ICACHE_ON 7'd10
`define ICACHE_OFF 7'd11
`define DCACHE_ON 7'd12
`define DCACHE_OFF 7'd13
`define FIP 7'd20
`define SYSJMP 7'd22
`define SYSCALL 7'd23
`define IRET 7'd32
`define ERET 7'd33
`define WAIT 7'd40
`define TLBP 7'd49
`define TLBR 7'd50
`define TLBWI 7'd51
`define TLBWR 7'd52
`define CLI 7'd64
`define SEI 7'd65
`define GRAN 7'd80
`define GRAFD 7'd82
`define R 7'd1
`define COM 7'd4
`define NOT 7'd5
`define NEG 7'd6
`define ABS 7'd7
`define SGN 7'd8
`define MOV 7'd9
`define SWAP 7'd13
`define CTLZ 7'd16
`define CTLO 7'd17
`define CTPOP 7'd18
`define SEXT8 7'd19
`define SEXT16 7'd20
`define SEXT32 7'd21
`define SQRT 7'd24
`define REDOR 7'd30
`define REDAND 7'd31
`define MFSPR 7'd40
`define MTSPR 7'd41
`define SR 6'd00
`define TLBIndex 6'd01
`define TLBRandom 6'd02
`define PageTableAddr 6'd04
`define BadVAddr 6'd08
`define TLBPhysPage0 6'd10
`define TLBPhysPage1 6'd11
`define TLBVirtPage 6'd12
`define TLBPageMask 6'd13
`define TLBASID 6'd14
`define ASID 6'd15
`define TLBWired 6'd16
`define EP0 6'd17
`define EP1 6'd18
`define EP2 6'd19
`define EP3 6'd20
`define AXC 6'd21
`define Tick 6'd22
`define EPC 6'd23
`define CauseCode 6'd24
`define TBA 6'd25
`define NON_ICACHE_SEG 6'd26
`define FPCR 6'd32
`define IPC 6'd33
`define RAND 6'd34
`define SRAND1 6'd35
`define SRAND2 6'd36
`define INSNKEY 6'd37
`define OMG 7'd50
`define CMG 7'd51
`define OMGI 7'd52
`define CMGI 7'd53
`define EXEC 7'd58
`define MYST 7'd59
`define RR 7'd2
`define ADD 7'd2
`define ADDU 7'd3
`define SUB 7'd4
`define SUBU 7'd5
`define CMP 7'd6
`define CMPU 7'd7
`define AND 7'd8
`define OR 7'd9
`define XOR 7'd10
`define ANDC 7'd11
`define NAND 7'd12
`define NOR 7'd13
`define XNOR 7'd14
`define ORC 7'd15
`define MIN 7'd20
`define MAX 7'd21
`define MULU 7'd24
`define MULS 7'd25
`define DIVU 7'd26
`define DIVS 7'd27
`define MOD 7'd28
`define MOVZ 7'd30
`define MOVNZ 7'd31
 
`define SHL 7'd40
`define SHRU 7'd41
`define ROL 7'd42
`define ROR 7'd43
`define SHR 7'd44
`define ROLAM 7'd45
 
`define NOP 7'd60
 
`define SLT 7'd96
`define SLE 7'd97
`define SGT 7'd98
`define SGE 7'd99
`define SLTU 7'd100
`define SLEU 7'd101
`define SGTU 7'd102
`define SGEU 7'd103
`define SEQ 7'd104
`define SNE 7'd105
 
`define BCD_ADD 7'd110
`define BCD_SUB 7'd111
 
`define SHFTI 7'd3
`define SHLI 5'd0
`define SHRUI 5'd1
`define ROLI 5'd2
`define SHRI 5'd3
`define RORI 5'd4
`define ROLAMI 5'd5
`define BFINS 5'd8
`define BFSET 5'd9
`define BFCLR 5'd10
`define BFCHG 5'd11
`define BFEXT 5'd12
`define ADDI 7'd4
`define ADDUI 7'd5
`define SUBI 7'd6
`define SUBUI 7'd7
`define CMPI 7'd8
`define CMPUI 7'd9
`define ANDI 7'd10
`define ORI 7'd11
`define XORI 7'd12
 
`define MULUI 7'd13
`define MULSI 7'd14
`define DIVUI 7'd15
`define DIVSI 7'd16
 
`define TRAPcc 7'd17
`define TEQ 5'd0
`define TNE 5'd1
`define TLT 5'd2
`define TGE 5'd3
`define TLE 5'd4
`define TGT 5'd5
`define TLTU 5'd6
`define TGEU 5'd7
`define TLEU 5'd8
`define TGTU 5'd9
`define TRAP 5'd10
`define TRN 5'd11
`define TRAPcci 7'd18
`define TEQI 5'd0
`define TNEI 5'd1
`define TLTI 5'd2
`define TGEI 5'd3
`define TLEI 5'd4
`define TGTI 5'd5
`define TLTUI 5'd6
`define TGEUI 5'd7
`define TLEUI 5'd8
`define TGTUI 5'd9
`define TRAI 5'd10
`define TRNI 5'd11
// SETLO=20 to 23
`define SETLO 7'b00101xx
`define CALL 7'd24
`define JMP 7'd25
`define JAL 7'd26
`define RET 7'd27
// SETLO=28 to 31
`define SETHI 7'b00111xx
`define LB 7'd32
`define LC 7'd33
`define LH 7'd34
`define LW 7'd35
`define LP 7'd36
`define LBU 7'd37
`define LCU 7'd38
`define LHU 7'd39
`define LSH 7'd40
`define LSW 7'd41
`define LF 7'd42
`define LFD 7'd43
`define LFP 7'd44
`define LFDP 7'd45
`define LWR 7'd46
`define LDONE 7'd47
 
`define SB 7'd48
`define SC 7'd49
`define SH 7'd50
`define SW 7'd51
`define SP 7'd52
`define MEMNDX 7'd53
`define LBX 6'd0
`define LCX 6'd1
`define LHX 6'd2
`define LWX 6'd3
`define LPX 6'd4
`define LBUX 6'd5
`define LCUX 6'd6
`define LHUX 6'd7
`define LSHX 6'd8
`define LSWX 6'd9
`define LFX 6'd10
`define LFDX 6'd11
`define LFPX 6'd12
`define LFDPX 6'd13
`define LWRX 6'd14
 
`define SBX 6'd16
`define SCX 6'd17
`define SHX 6'd18
`define SWX 6'd19
`define SPX 6'd20
`define SSHX 6'd24
`define SSWX 6'd25
`define SFX 6'd26
`define SFDX 6'd27
`define SFPX 6'd28
`define SFDPX 6'd29
`define SWCX 6'd30
 
`define INBX 6'd32
`define INCX 6'd33
`define INHX 6'd34
`define INWX 6'd35
`define INBUX 6'd36
`define INCUX 6'd37
`define INHUX 6'd38
`define OUTBX 6'd40
`define OUTCX 6'd41
`define OUTHX 6'd42
`define OUTWX 6'd43
`define CACHEX 6'd44
`define LEAX 6'd45
`define LMX 6'd46
`define SMX 6'd47
 
`define SSH 7'd56
`define SSW 7'd57
`define SF 7'd58
`define SFD 7'd59
`define SFP 7'd60
`define SFDP 7'd61
`define SWC 7'd62
 
`define INB 7'd64
`define INCH 7'd65
`define INH 7'd66
`define INW 7'd67
`define INBU 7'd68
`define INCU 7'd69
`define INHU 7'd70
`define OUTB 7'd72
`define OUTC 7'd73
`define OUTH 7'd74
`define OUTW 7'd75
`define CACHE 7'd76
`define INVIL 5'd0
`define INVIALL 5'd1
`define LEA 7'd77
`define LM 7'd78
`define SM 7'd79
 
`define BLTI 7'd80
`define BGEI 7'd81
`define BLEI 7'd82
`define BGTI 7'd83
`define BLTUI 7'd84
`define BGEUI 7'd85
`define BLEUI 7'd86
`define BGTUI 7'd87
`define BEQI 7'd88
`define BNEI 7'd89
 
`define BTRI 7'd94
`define BLTRI 5'd0
`define BGERI 5'd1
`define BLERI 5'd2
`define BGTRI 5'd3
`define BLTURI 5'd4
`define BGEURI 5'd5
`define BLEURI 5'd6
`define BGTURI 5'd7
`define BEQRI 5'd8
`define BNERI 5'd9
`define BRARI 5'd10
`define BRNRI 5'd11
`define BANDRI 5'd12
`define BORRI 5'd13
`define BTRR 7'd95
`define BLT 5'd0
`define BGE 5'd1
`define BLE 5'd2
`define BGT 5'd3
`define BLTU 5'd4
`define BGEU 5'd5
`define BLEU 5'd6
`define BGTU 5'd7
`define BEQ 5'd8
`define BNE 5'd9
`define BRA 5'd10
`define BRN 5'd11
`define BAND 5'd12
`define BOR 5'd13
`define BNR 5'd14
`define LOOP 5'd15
`define BLTR 5'd16
`define BGER 5'd17
`define BLER 5'd18
`define BGTR 5'd19
`define BLTUR 5'd20
`define BGEUR 5'd21
`define BLEUR 5'd22
`define BGTUR 5'd23
`define BEQR 5'd24
`define BNER 5'd25
`define BRAR 5'd26
`define BRNR 5'd27
 
 
`define SLTI 7'd96
`define SLEI 7'd97
`define SGTI 7'd98
`define SGEI 7'd99
`define SLTUI 7'd100
`define SLEUI 7'd101
`define SGTUI 7'd102
`define SGEUI 7'd103
`define SEQI 7'd104
`define SNEI 7'd105
 
`define FP 7'd108
`define FDADD 6'd0
`define FDSUB 6'd1
`define FDMUL 6'd2
`define FDDIV 6'd3
`define FDCUN 6'd4
`define FDI2F 6'd5
`define FDF2I 6'd6
`define FDF2D 6'd7
`define FDD2F 6'd8
`define FDCLT 6'b001100
`define FDCEQ 6'b010100
`define FDCLE 6'b011100
`define FDCGT 6'b100100
`define FDCNE 6'b101100
`define FDCGE 6'b110100
`define FPLOO 7'd109
`define FPZL 7'd110
`define NOPI 7'd111
 
`define IMM 3'd7
 
`define NOP_INSN 42'b1101111_000_00000000_00000000_00000000_00000000
 
/raptor64/trunk/rtl/verilog/Raptor64_logic.v
0,0 → 1,61
`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
// __
// \\__/ o\ (C) 2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// Raptor64_logic.v
// - logical datapath operations
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//=============================================================================
//
module Raptor64_logic(xIR, a, b, imm, o);
input [41:0] xIR;
input [63:0] a;
input [63:0] b;
input [63:0] imm;
output [63:0] o;
reg [63:0] o;
 
wire [6:0] xOpcode = xIR[41:35];
wire [6:0] xFunc = xIR[6:0];
 
always @(xOpcode or xFunc or a or b or imm)
case (xOpcode)
`RR:
case(xFunc)
`AND: o = a & b;
`OR: o = a | b;
`XOR: o = a ^ b;
`ANDC: o = a & ~b;
`NAND: o = ~(a & b);
`NOR: o = ~(a | b);
`XNOR: o = ~(a ^ b);
`ORC: o = a | ~b;
default: o = 64'd0;
endcase
`ANDI: o = a & imm;
`ORI: o = a | imm;
`XORI: o = a ^ imm;
default: o = 64'd0;
endcase
 
endmodule
/raptor64/trunk/rtl/verilog/Raptor64_addsub.v
0,0 → 1,64
`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
// __
// \\__/ o\ (C) 2011,2012 Robert Finch
// \ __ / All rights reserved.
// \/_// robfinch<remove>@opencores.org
// ||
//
// Raptor64_addsub.v
// - addsub datapath operations
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//=============================================================================
//
module Raptor64_addsub(xIR, a, b, imm, o);
input [41:0] xIR;
input [63:0] a;
input [63:0] b;
input [63:0] imm;
output [63:0] o;
reg [63:0] o;
 
wire [6:0] xOpcode = xIR[41:35];
wire [6:0] xFunc = xIR[6:0];
wire [7:0] bcdaddo,bcdsubo;
 
BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
BCDSub u2(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
 
always @(xOpcode,xFunc,a,b,imm,bcdaddo,bcdsubo)
case (xOpcode)
`RR:
case(xFunc)
`ADD: o = a + b;
`ADDU: o = a + b;
`SUB: o = a - b;
`SUBU: o = a - b;
`BCD_ADD: o = bcdaddo;
`BCD_SUB: o = bcdsubo;
default: o = 64'd0;
endcase
`ADDI: o = a + imm;
`ADDUI: o = a + imm;
`SUBI: o = a - imm;
`SUBUI: o = a - imm;
default: o = 64'd0;
endcase
 
endmodule

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