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    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/tinycpu/trunk/testbench/alu_tb.vhd
236,12 → 236,6
wait for 10 ns;
assert (DataOut=x"FE") report "subtract underflow operation error" severity error;
 
Op <= "10000"; --set TR
wait for 10 ns;
Op <= "10011"; --decrement
DataIn1 <= x"12";
wait for 10 ns;
assert (TR='1') report "TR persistence error" severity error;
 
 
 
/tinycpu/trunk/testbench/core_tb.vhd
142,7 → 142,10
assert(DebugTR ='0') report "ALU compare is not correct for greater than" severity error;
MemIn <= "0011000000010010"; --TR=r0 < r1
wait for 10 ns;
MemIn <= x"0F20"; --jmp to 0x20 if TR=1
assert(DebugTR='1') report "ALU compare is not correct for less than" severity error;
wait for 10 ns;
assert(DebugIP=x"20") report "conditional TR is not correct after ALU compare" severity error;
 
--now test bitwise
MemIn <= x"0E50"; --mov IP, 0x50 -- do this just so we can count IP easily
/tinycpu/trunk/src/alu.vhd
23,12 → 23,10
end alu;
 
architecture Behavioral of alu is
signal TRData: std_logic;
begin
TR <= TRData;
process(DataIn1, DataIn2, Op)
begin
--TRData <='0'; --default
TR <= '0';
case Op is
--bitwise operations
when "00000" => --and
51,66 → 49,66
when "01000" => --greater than
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) > to_integer(unsigned(DataIn2))) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01001" => --greater than or equal
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) >= to_integer(unsigned(DataIn2))) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01010" => --less than
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) < to_integer(unsigned(DataIn2))) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01011" => --less than or equal
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) <= to_integer(unsigned(DataIn2))) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01100" => --equals to
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) = to_integer(unsigned(DataIn2))) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01101" => --not equal
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) /= to_integer(unsigned(DataIn2))) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01110" => --equal to 0
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) = 0) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
when "01111" => --not equal to 0
DataOut <= "00000000";
if(to_integer(unsigned(DataIn1)) /= 0) then
TRData <= '1';
TR <= '1';
else
TRData <= '0';
TR <= '0';
end if;
--other operations
when "10000" => --set TR
DataOut <= "00000000";
TRData <= '1';
TR <= '1';
when "10001" => --reset TR
DataOut <= "00000000";
TRData <= '0';
TR <= '0';
when "10010" => --increment
DataOut <= std_logic_vector(unsigned(DataIn1) + 1);
when "10011" => --decrement
122,7 → 120,7
 
when others =>
DataOut <= "00000000";
TRData <= '1';
TR <= '1';
end case;
end process;
end Behavioral;
/tinycpu/trunk/src/core.vhd
115,7 → 115,10
signal AluIn1: std_logic_vector(7 downto 0);
signal AluIn2: std_logic_vector(7 downto 0);
signal AluOut: std_logic_vector(7 downto 0);
signal AluTR: std_logic;
signal TR: std_logic;
signal TRData: std_logic;
signal UseAluTR: std_logic;
--control signals
signal InReset: std_logic;
185,7 → 188,7
DataIn1 => AluIn1,
DataIn2 => AluIn2,
DataOut => AluOut,
TR => TR
TR => AluTR
);
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
215,8 → 218,8
--UsuallySegment shortcuts (only used when not an immediate
UsuallyDS <= "1101" when opseges='0' else "1110";
UsuallySS <= "1111" when opseges='0' else "1110";
TR <= TRData when UseAluTR='0' else AluTR;
foo: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
begin
if rising_edge(Clock) then
240,6 → 243,8
OpAddress <= x"0000";
OpWE <= '0';
opWW <= '0';
TRData <= '0';
UseAluTR <= '0';
--finish up
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
InReset <= '0';
304,7 → 309,9
regWE(REGSP) <= '1';
regWE(REGSS) <= '1';
OpAddress <= "ZZZZZZZZZZZZZZZZ";
if UseAluTR='1' then
UseAluTR<='0';
end if;
--actual decoding
if opcond1='0' or (opcond1='1' and TR='1') then
case opmain is
320,6 → 327,8
IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
FetchEN <= '0';
when "0011" => --group 3 comparisons
TRData <= AluTR;
UseAluTR <= '1';
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));

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