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Rev 30 → Rev 31

/trunk/rtl-model/alu.v
61,7 → 61,7
.x (x),
.y (y),
.o (mul),
.f (func[1:0]),
.f (func),
.word_op (word_op),
.cfo (cf_mul),
.ofo (of_mul),
208,7 → 208,7
input [31:0] x, // 16 MSb for division
input [15:0] y,
output [31:0] o,
input [ 1:0] f,
input [ 2:0] f,
input word_op,
output cfo,
output ofo,
253,21 → 253,23
: { {9{as}}, x[7:0] };
assign b = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
 
assign zi = word_op ? (f[0] ? { {2{x[31]}}, x }
assign zi = f[2] ? { 26'h0, x[7:0] }
: (word_op ? (f[0] ? { {2{x[31]}}, x }
: { 2'b0, x })
: (f[0] ? { {18{x[15]}}, x[15:0] }
: { 18'b0, x[15:0] });
: { 18'b0, x[15:0] }));
 
assign di = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
: (f[0] ? { {9{y[7]}}, y[7:0] }
: { 9'h000, y[7:0] });
 
assign o = f[1] ? ( word_op ? {s[15:0], q[15:0]}
assign o = f[2] ? { 16'h0, q[7:0], s[7:0] }
: (f[1] ? ( word_op ? {s[15:0], q[15:0]}
: {16'h0, s[7:0], q[7:0]})
: p[31:0];
: p[31:0]);
 
assign ofo = cfo;
assign cfo = !(f[0] ? cfs : cfu);
assign ofo = f[1] ? 1'b0 : cfo;
assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
assign cfu = word_op ? (o[31:16] == 16'h0)
: (o[15:8] == 8'h0);
assign cfs = word_op ? (o[31:16] == {16{o[15]}})
274,13 → 276,14
: (o[15:8] == {8{o[7]}});
 
// Exceptions
assign over = word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
assign over = f[2] ? 1'b0
: (word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
: (q[17:16]!=2'b0) )
: (f[0] ? (q[17:8]!={10{q[7]}})
: (q[17:8]!=10'h000) );
: (q[17:8]!=10'h000)));
assign mint = f[0] & (word_op ? (x==32'h80000000)
: (x==16'h8000));
assign exc = div0 | ovf | over | mint;
assign exc = div0 | (!f[2] & ovf) | over | mint;
endmodule
 
module bitlog(x, y, out, func, cfo, ofo);
/trunk/rtl-model/fetch.v
1318,7 → 1318,7
src <= rm;
dst <= rm;
end
/*
 
8'b1101_0100: // aam
begin
seq_addr <= `AAM;
1330,7 → 1330,7
src <= 4'b0;
dst <= 4'b0;
end
*/
 
8'b1101_0101: // aad
begin
seq_addr <= `AAD;
/trunk/rtl-model/util/primitives.v
65,29 → 65,6
endmodule
*/
//
// Multiplexor 8:1 de 17 bits d'amplada
//
module mux8_17(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [16:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [16:0] out;
 
reg [16:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
 
//
// Multiplexor 8:1 d'1 bit d'amplada
//
module mux8_1(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
111,15 → 88,14
endmodule
 
//
// Multiplexor 4:1 de 32 bits d'amplada
// Multiplexor 4:1 de 16 bits d'amplada
//
 
module mux4_32(sel, in0, in1, in2, in3, out);
module mux4_16(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input [31:0] in0, in1, in2, in3;
output [31:0] out;
input [15:0] in0, in1, in2, in3;
output [15:0] out;
 
reg [31:0] out;
reg [15:0] out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
130,16 → 106,15
endcase
endmodule
 
 
//
// Multiplexor 4:1 de 16 bits d'amplada
// Multiplexor 4:1 de 1 bits d'amplada
//
module mux4_16(sel, in0, in1, in2, in3, out);
module mux4_1(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input [15:0] in0, in1, in2, in3;
output [15:0] out;
input in0, in1, in2, in3;
output out;
 
reg [15:0] out;
reg out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
150,6 → 125,7
endcase
endmodule
 
/*
//
// Multiplexor 2:1 de 8 bits d'amplada
//
168,14 → 144,15
endmodule
 
//
// Multiplexor 4:1 de 1 bits d'amplada
// Multiplexor 4:1 de 32 bits d'amplada
//
module mux4_1(sel, in0, in1, in2, in3, out);
 
module mux4_32(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input in0, in1, in2, in3;
output out;
input [31:0] in0, in1, in2, in3;
output [31:0] out;
 
reg out;
reg [31:0] out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
186,6 → 163,30
endcase
endmodule
 
//
// Multiplexor 8:1 de 17 bits d'amplada
//
module mux8_17(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [16:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [16:0] out;
 
reg [16:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
*/
 
/*
//
// 1 bit cell divider by 10
/trunk/tests/i86/18_div.s
1,12 → 1,12
.code16
start:
movw $256, %sp
movw $208, %sp
 
# Exception 0 handler
movw $0x1000, (0)
movw $0xf000, (2)
 
movw $256, %bp
movw $208, %bp
 
# div word tests
# easy test
315,6 → 315,50
movw %ax, (124)
movw %dx, (126)
pushf
 
 
# AAM tests
movw $0xffff, %ax
 
movw $0x2, (%bp)
aam $0
addw $0x2, %bp
movw %ax, (132)
pushf
 
movw $0x2, (%bp)
aam $1
addw $0x2, %bp
movw %ax, (134)
pushf
 
movw $0xffff, %ax
movw $0x2, (%bp)
aam
addw $0x2, %bp
movw %ax, (136)
pushf
 
movw $0xff00, %ax
movw $0x2, (%bp)
aam $0
addw $0x2, %bp
movw %ax, (138)
pushf
 
movw $0x2, (%bp)
aam $1
addw $0x2, %bp
movw %ax, (140)
pushf
 
movw $0x3ffb, %ax
movw $0x2, (%bp)
aam
addw $0x2, %bp
movw %ax, (142)
pushf
 
hlt
 
# Exception handler (int 0)

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