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    from Rev 305 to Rev 306
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Rev 305 → Rev 306

/t48/trunk/bench/vhdl/tb_t8041-c.vhd
0,0 → 1,24
-------------------------------------------------------------------------------
--
-- The testbench for t8041.
--
-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
configuration tb_t8041_behav_c0 of tb_t8041 is
 
for behav
 
for t8041_b : t8041
use configuration work.t8041_struct_c0;
end for;
for upi_stim_b : upi_stim
use configuration work.upi_stim_behav_c0;
end for;
 
end for;
 
end tb_t8041_behav_c0;
/t48/trunk/bench/vhdl/tb_t8041.vhd
0,0 → 1,208
-------------------------------------------------------------------------------
--
-- The testbench for t8041.
--
-- Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_t8041 is
 
end tb_t8041;
 
 
use work.t48_system_comp_pack.t8041;
 
use work.t48_tb_pack.all;
 
architecture behav of tb_t8041 is
 
-- clock period, 11 MHz
constant period_c : time := 90 ns;
 
signal xtal_s : std_logic;
signal res_n_s : std_logic;
signal prog_n_s : std_logic;
 
signal p1_b : std_logic_vector( 7 downto 0);
signal p2_b : std_logic_vector( 7 downto 0);
 
signal db_b : std_logic_vector( 7 downto 0);
signal cs_n_s : std_logic;
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal a0_s : std_logic;
 
signal fail_s : boolean;
 
signal zero_s : std_logic;
signal one_s : std_logic;
 
component upi_stim
port (
cs_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
a0_o : out std_logic;
db_b : inout std_logic_vector(7 downto 0);
p1_b : inout std_logic_vector(7 downto 0);
p2_b : inout std_logic_vector(7 downto 0);
fail_o : out boolean
);
end component;
 
begin
 
zero_s <= '0';
one_s <= '1';
 
p2_b <= (others => 'H');
p1_b <= (others => 'H');
 
t8041_b : t8041
port map (
xtal_i => xtal_s,
reset_n_i => res_n_s,
cs_n_i => cs_n_s,
rd_n_i => rd_n_s,
a0_i => a0_s,
wr_n_i => wr_n_s,
t0_i => p1_b(0),
db_b => db_b,
t1_i => p1_b(1),
p2_b => p2_b,
p1_b => p1_b,
prog_n_o => prog_n_s
);
 
 
-----------------------------------------------------------------------------
-- Generic UPI stimulus generator
--
upi_stim_b: upi_stim
port map (
cs_n_o => cs_n_s,
rd_n_o => rd_n_s,
wr_n_o => wr_n_s,
a0_o => a0_s,
db_b => db_b,
p1_b => p1_b,
p2_b => p2_b,
fail_o => fail_s
);
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
 
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
 
if not fail_s then
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL from TB."
severity note;
end if;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
 
assert false
report "End of simulation reached."
severity failure;
 
end if;
end if;
end loop;
 
end process eos;
--
-----------------------------------------------------------------------------
 
end behav;
/t48/trunk/bench/vhdl/tb_t8041a-c.vhd
15,6 → 15,9
for t8041a_b : t8041a
use configuration work.t8041a_struct_c0;
end for;
for upi_stim_b : upi_stim
use configuration work.upi_stim_behav_c0;
end for;
 
end for;
 
/t48/trunk/bench/vhdl/tb_t8041a.vhd
71,17 → 71,26
signal wr_n_s : std_logic;
signal a0_s : std_logic;
 
signal fail_s : boolean;
 
signal zero_s : std_logic;
signal one_s : std_logic;
 
component upi_stim
port (
cs_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
a0_o : out std_logic;
db_b : inout std_logic_vector(7 downto 0);
p1_b : inout std_logic_vector(7 downto 0);
p2_b : inout std_logic_vector(7 downto 0);
fail_o : out boolean
);
end component;
 
begin
 
-- TODO
cs_n_s <= '1';
rd_n_s <= '1';
wr_n_s <= '1';
a0_s <= '0';
 
zero_s <= '0';
one_s <= '1';
 
106,6 → 115,24
 
 
-----------------------------------------------------------------------------
-- Generic UPI stimulus generator
--
upi_stim_b: upi_stim
port map (
cs_n_o => cs_n_s,
rd_n_o => rd_n_s,
wr_n_o => wr_n_s,
a0_o => a0_s,
db_b => db_b,
p1_b => p1_b,
p2_b => p2_b,
fail_o => fail_s
);
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
150,9 → 177,16
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
 
if not fail_s then
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL from TB."
severity note;
end if;
else
assert false
report "Simulation Result: FAIL."
/t48/trunk/bench/vhdl/upi_stim-c.vhd
0,0 → 1,7
 
configuration upi_stim_behav_c0 of upi_stim is
 
for behav
end for;
 
end upi_stim_behav_c0;
/t48/trunk/bench/vhdl/upi_stim.vhd
0,0 → 1,128
 
library ieee;
use ieee.std_logic_1164.all;
 
entity upi_stim is
 
port (
cs_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
a0_o : out std_logic;
db_b : inout std_logic_vector(7 downto 0);
p1_b : inout std_logic_vector(7 downto 0);
p2_b : inout std_logic_vector(7 downto 0);
fail_o : out boolean
);
 
end upi_stim;
 
 
architecture behav of upi_stim is
 
begin
 
stim: process
 
constant del_seq_c : time := 5 us;
constant del_dat_c : time := 10 us;
constant del_step_c : time := 20 us;
 
variable rdata : std_logic_vector(db_b'range);
 
procedure write_dbbin(data : in std_logic_vector(7 downto 0);
a0 : in std_logic) is
begin
cs_n_o <= '0';
wait for del_seq_c;
wr_n_o <= '0';
wait for del_seq_c;
a0_o <= a0;
db_b <= data;
wait for del_dat_c;
wr_n_o <= '1';
wait for del_seq_c;
cs_n_o <= '1';
wait for del_seq_c;
db_b <= (others => 'Z');
wait for del_step_c;
end;
 
procedure read_dbbout(a0 : in std_logic) is
begin
cs_n_o <= '0';
wait for del_seq_c;
rd_n_o <= '0';
wait for del_seq_c;
a0_o <= a0;
wait for del_dat_c;
rdata := db_b;
rd_n_o <= '1';
wait for del_seq_c;
cs_n_o <= '1';
wait for del_seq_c;
wait for del_step_c;
end;
 
procedure poll_obf is
begin
-- poll for OBF
rdata := (others => '0');
while rdata(0) = '0' loop
read_dbbout(a0 => '1');
end loop;
end;
 
procedure echo_test is
begin
-- write data
write_dbbin(data => "01010101", a0 => '0');
 
poll_obf;
 
read_dbbout(a0 => '0');
if rdata /= "10101010" then
-- error
fail_o <= true;
end if;
 
-- send ok to dut
write_dbbin(data => "00000001", a0 => '1');
end;
 
procedure flags_test is
begin
end;
 
begin
 
fail_o <= false;
cs_n_o <= '1';
rd_n_o <= '1';
wr_n_o <= '1';
a0_o <= '0';
db_b <= (others => 'Z');
 
wait until falling_edge(p1_b(2));
wait for 100 us;
 
while true loop
poll_obf;
 
-- read and interpret request
read_dbbout(a0 => '0');
case rdata is
when "00000001" =>
echo_test;
when others =>
null;
end case;
 
end loop;
 
 
wait;
 
end process stim;
 
end;
/t48/trunk/sim/rtl_sim/Makefile.ghdl
5,7 → 5,7
# It sets all variables needed for VHDL code compilation with Makefile.hier.
#
#
# Copyright (c) 2004-2006 Arnim Laeuger (arniml@opencores.org)
# Copyright (c) 2004-2022 Arnim Laeuger (arniml@opencores.org)
#
# All rights reserved
#
38,6 → 38,14
upi41_db_bus = $(LIB_WORK)/upi41_db_bus.o
upi41_core_struct_c0 = $(LIB_WORK)/upi41_core-c.o
upi41_core = $(LIB_WORK)/upi41_core.o
t8041_notri_struct_c0 = $(LIB_WORK)/t8041_notri-c.o
t8041_notri = $(LIB_WORK)/t8041_notri.o
t8041_struct_c0 = $(LIB_WORK)/t8041-c.o
t8041 = $(LIB_WORK)/t8041.o
upi_stim_behav_c0 = $(LIB_WORK)/upi_stim-c.o
upi_stim = $(LIB_WORK)/upi_stim.o
tb_t8041_behav_c0 = $(LIB_WORK)/tb_t8041-c.o
tb_t8041 = $(LIB_WORK)/tb_t8041.o
t8041a_notri_struct_c0 = $(LIB_WORK)/t8041a_notri-c.o
t8041a_notri = $(LIB_WORK)/t8041a_notri.o
t8041a_struct_c0 = $(LIB_WORK)/t8041a-c.o
143,6 → 151,7
tb_t8039_elab = tb_t8039_behav_c0
tb_t8048_t8243_elab = tb_t8048_t8243_behav_c0
tb_t8243_elab = tb_t8243_behav_c0
tb_t8041_elab = tb_t8041_behav_c0
tb_t8041a_elab = tb_t8041a_behav_c0
#
##############################################################################
166,6 → 175,9
$(tb_t8243_elab) : $(tb_t8243_behav_c0)
$(ELABORATE) tb_t8243_behav_c0
 
$(tb_t8041_elab) : $(tb_t8041_behav_c0)
$(ELABORATE) tb_t8041_behav_c0
 
$(tb_t8041a_elab) : $(tb_t8041a_behav_c0)
$(ELABORATE) tb_t8041a_behav_c0
 
172,7 → 184,7
.PHONY: elaborate
elaborate: $(LIB_WORK) $(tb_elab) $(tb_t8048_elab) $(tb_t8039_elab) \
$(tb_t8048_t8243_elab) $(tb_t8243_elab) \
$(tb_t8041a_elab)
$(tb_t8041_elab) $(tb_t8041a_elab)
#
##############################################################################
 
/t48/trunk/sim/rtl_sim/Makefile.hier
25,7 → 25,7
# Various VHDL design units.
#
#
# Copyright (c) 2004-2006, Arnim Laeuger (arniml@opencores.org)
# Copyright (c) 2004-2022, Arnim Laeuger (arniml@opencores.org)
#
# All rights reserved
#
474,6 → 474,47
$(upi41_core)
$(ANALYZE) $<
 
$(t8041_notri) : $(RTL_DIR)/system/t8041_notri.vhd \
$(t48_core_comp_pack)
$(ANALYZE) $<
 
$(t8041_notri_struct_c0) : $(RTL_DIR)/system/t8041_notri-c.vhd \
$(upi41_core_struct_c0) \
$(generic_ram_ena_rtl_c0) \
$(t48_rom_lpm_c0) \
$(t48_core_comp_pack) \
$(t8041_notri)
$(ANALYZE) $<
 
$(t8041) : $(RTL_DIR)/system/t8041.vhd \
$(t48_system_comp_pack)
$(ANALYZE) $<
 
$(t8041_struct_c0) : $(RTL_DIR)/system/t8041-c.vhd \
$(t8041_notri_struct_c0) \
$(t8041)
$(ANALYZE) $<
 
$(upi_stim) : $(BENCH_DIR)/upi_stim.vhd
$(ANALYZE) $<
 
$(upi_stim_behav_c0) : $(BENCH_DIR)/upi_stim-c.vhd \
$(upi_stim)
$(ANALYZE) $<
 
$(tb_t8041) : $(BENCH_DIR)/tb_t8041.vhd \
$(t48_tb_pack) \
$(t48_core_comp_pack) \
$(t48_system_comp_pack)
$(ANALYZE) $<
 
$(tb_t8041_behav_c0) : $(BENCH_DIR)/tb_t8041-c.vhd \
$(t8041_struct_c0) \
$(upi_stim_behav_c0) \
$(t48_tb_pack) \
$(tb_t8041)
$(ANALYZE) $<
 
$(t8041a_notri) : $(RTL_DIR)/system/t8041a_notri.vhd \
$(t48_core_comp_pack)
$(ANALYZE) $<
503,6 → 544,7
 
$(tb_t8041a_behav_c0) : $(BENCH_DIR)/tb_t8041a-c.vhd \
$(t8041a_struct_c0) \
$(upi_stim_behav_c0) \
$(t48_tb_pack) \
$(tb_t8041a)
$(ANALYZE) $<
/t48/trunk/sw/run_regression.pl
26,9 → 26,11
# is started.
#
# Exceptions for a testcell are defined by additional files.
# no_gen : don't execute the generic/default testbench tb_behav_c0
# no_t48 : don't execute the t8048 testbench tb_t8048_behav_c0
# no_t39 : don't execute the t8039 testbench tb_t8039_behav_c0
# no_gen : don't execute the generic/default testbench tb_behav_c0
# no_t48 : don't execute the t8048 testbench tb_t8048_behav_c0
# no_t39 : don't execute the t8039 testbench tb_t8039_behav_c0
# no_t41 : don't execute the t8041 testbench tb_t8041_behav_c0
# no_t41a : don't execute the t8041a testbench tb_t8041a_behav_c0
# no_dump_compare : don't include testcell when running dump compares
# io_exp : use the testbenches containing the t8243 IO expander
# tb_t8243_behav_c0
67,6 → 69,7
my %ghdl_simulators = ('gen' => './tb_behav_c0',
't48' => './tb_t8048_behav_c0',
't39' => './tb_t8039_behav_c0',
't41' => './tb_t8041_behav_c0',
't41a'=> './tb_t8041a_behav_c0');
my %ghdl_io_expanders = ('gen' => './tb_t8243_behav_c0',
't48' => './tb_t8048_t8243_behav_c0');
/t48/trunk/sw/verif/black_box/anl/bus/no_t41
/t48/trunk/sw/verif/black_box/int/jni/no_t41
/t48/trunk/sw/verif/black_box/int/simple_jump_to/no_t41
/t48/trunk/sw/verif/black_box/mb/int/no_t41
/t48/trunk/sw/verif/black_box/movx/no_t41
/t48/trunk/sw/verif/black_box/rb/int/no_t41
/t48/trunk/sw/verif/black_box/upi41/basic_echo/no_gen
/t48/trunk/sw/verif/black_box/upi41/basic_echo/no_t48 --- t48/trunk/sw/verif/black_box/upi41/basic_echo/test.asm (nonexistent) +++ t48/trunk/sw/verif/black_box/upi41/basic_echo/test.asm (revision 306) @@ -0,0 +1,53 @@ + ;; ******************************************************************* + ;; Test UPI41 read and write. + ;; ******************************************************************* + + INCLUDE "cpu.inc" + INCLUDE "pass_fail.inc" + INCLUDE "upi41_opcodes.inc" + + ORG 0 + + ;; Start of test + + ;; test IBF empty + ujnibf ibfempty + jmp fail + +ibfempty: + ;; test OBF empty + ujobf fail + + ;; signal test start + anl P1, #~004H + + ;; request echo test + mov a, #001H + uout dbb, a + + ;; read input as data +inp1: ujnibf inp1 + jf1 fail + + uin a, dbb + + ;; invert and output + xrl a, #0FFH + + uout dbb, a + +out1: ujobf out1 + + ;; read next input as command +inp2: ujnibf inp2 + jf1 inp2_2 + jmp fail + +inp2_2: uin a, dbb + xrl a, #001H + jz pass + + +fail: FAIL + +pass: PASS
/t48/trunk/sw/verif/include/upi41_opcodes.inc
0,0 → 1,17
ujnibf MACRO target
db 0D6H
db target
ENDM
 
ujobf MACRO target
db 086H
db target
ENDM
 
uin MACRO a, dbb
db 022H
ENDM
 
uout MACRO dbb, a
db 002H
ENDM
/t48/trunk/sw/verif/white_box/int_on_call/no_t41
/t48/trunk/sw/verif/white_box/int_on_mb1/no_t41
/t48/trunk/sw/verif/white_box/p2_io_exp/no_t41
/t48/trunk/sw/verif/white_box/psen_rd_wr_timing/no_t41

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