URL
https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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Rev 31 → Rev 32
/async_sdm_noc/branches/init/sdm/tb/netnode.v
0,0 → 1,70
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The SystemC module of network node including the processing element and the network interface. |
Currently the transmission FIFO is 500 frame deep. |
|
History: |
27/02/2011 Initial version. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
`include "define.v" |
|
module NetNode ( |
dia, do4, doa, di4, |
do0, do1, do2, do3, |
di0, di1, di2, di3, |
rst_n) |
// |
// The foreign attribute string value must be a SystemC value. |
// |
(* integer foreign = "SystemC"; |
*); |
// |
// Verilog port names must match port names exactly as they appear in the |
// sc_module class in SystemC; they must also match in order, mode, and type. |
// |
parameter DW = 32; |
parameter VCN = 1; |
parameter x = 2; |
parameter y = 2; |
parameter SCN = DW/2; |
|
`ifdef ENABLE_CHANNEL_SLICING |
input [VCN*SCN-1:0] dia; |
input [VCN*SCN-1:0] do4; |
output [VCN*SCN-1:0] doa; |
output [VCN*SCN-1:0] di4; |
`else |
input [VCN-1:0] dia; |
input [VCN-1:0] do4; |
output [VCN-1:0] doa; |
output [VCN-1:0] di4; |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
input [VCN*SCN-1:0] do0; |
input [VCN*SCN-1:0] do1; |
input [VCN*SCN-1:0] do2; |
input [VCN*SCN-1:0] do3; |
|
output [VCN*SCN-1:0] di0; |
output [VCN*SCN-1:0] di1; |
output [VCN*SCN-1:0] di2; |
output [VCN*SCN-1:0] di3; |
|
input rst_n; |
|
|
endmodule // NetNode |
|
|
/async_sdm_noc/branches/init/sdm/tb/netnode.h
14,7 → 14,7
|
History: |
26/02/2011 Initial version. <wsong83@gmail.com> |
29/05/2011 Clean up for opensource. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
21,7 → 21,7
#ifndef NETNODE_H_ |
#define NETNODE_H_ |
|
#include "noc_define.h" |
#include "define.h" |
#include <systemc.h> |
#include "ni.h" |
#include "procelem.h" |
/async_sdm_noc/branches/init/sdm/tb/rtdriver.cpp
0,0 → 1,286
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The port driver between NI and router. |
|
History: |
27/04/2010 Initial version. <wsong83@gmail.com> |
16/10/2010 Support SDM. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
#include "rtdriver.h" |
|
RTDriver::RTDriver(sc_module_name mname) |
: sc_module(mname), |
NI2P("NI2P"), |
P2NI("P2NI") |
{ |
SC_METHOD(IPdetect); |
sensitive << rtia; |
|
SC_METHOD(OPdetect); |
sensitive << rtod[0] << rtod[1] << rtod[2] << rtod[3] << rtod4; |
|
SC_THREAD(send); |
SC_THREAD(recv); |
|
rtinp_sig = false; |
rtoutp_sig = false; |
} |
|
void RTDriver::IPdetect() { |
sc_logic ack_lv_high, ack_lv_low; // the sc_logic ack |
|
// read the ack |
#ifdef ENABLE_CHANNEL_CLISING |
ack_lv_high = rtia.read().and_reduce(); |
ack_lv_high = rtia.read().or_reduce(); |
#else |
ack_lv_high = rtia.read(); |
ack_lv_high = rtia.read(); |
#endif |
|
if(ack_lv_high.is_01() && ack_lv_high.to_bool()) |
rtinp_sig = true; |
|
if(ack_lv_low.is_01() && (!ack_lv_low.to_bool())) |
rtinp_sig = false; |
} |
|
void RTDriver::OPdetect() { |
sc_lv<ChBW*4> data_lv; // the ORed data |
sc_logic data_lv_high, data_lv_low; |
|
#ifdef ENABLE_CHANNEL_CLISING |
data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read() | rtod4.read(); |
data_lv_high = data_lv.and_reduce(); |
data_lv_low = data_lv.or_reduce(); |
#else |
data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read(); |
data_lv_high = data_lv.and_reduce() & rtod4.read(); |
data_lv_low = data_lv.or_reduce() | rtod4.read(); |
#endif |
|
if(data_lv_high.is_01() && data_lv_high.to_bool()) |
rtoutp_sig = true; |
|
if(data_lv_high.is_01() && (!data_lv_low.to_bool())) |
rtoutp_sig = false; |
} |
|
void RTDriver::send() { |
FLIT mflit; // the local flit buffer |
unsigned int i, j; // local loop index |
sc_lv<ChBW*4> mdata[4]; // local data copy |
#ifdef ENABLE_CHANNEL_CLISING |
sc_lv<ChBW*4> mdata4; // local copy of eof |
#else |
sc_logic mdata4; // local copy of eof |
#endif |
|
// initialize the output ports |
mdata[0] = 0; |
mdata[1] = 0; |
mdata[2] = 0; |
mdata[3] = 0; |
#ifdef ENABLE_CHANNEL_CLISING |
mdata4 = 0; |
#else |
mdata4 = false; |
#endif |
|
rtid[0].write(mdata[0]); |
rtid[1].write(mdata[1]); |
rtid[2].write(mdata[2]); |
rtid[3].write(mdata[3]); |
rtid4.write(mdata4); |
|
while(true) { |
mflit = NI2P->read(); // read in the flit |
|
// write the flit |
if(mflit.ftype == F_HD) { |
// the target address |
mdata[mflit.addrx&0x3][0] = SC_LOGIC_1; |
mdata[(mflit.addrx&0xc)>>2][1] = SC_LOGIC_1; |
mdata[mflit.addry&0x3][2] = SC_LOGIC_1; |
mdata[(mflit.addry&0xc)>>2][3] = SC_LOGIC_1; |
|
for(i=0,j=4; i<(ChBW-1)*4; i++, j++) { |
switch((mflit[i/4] >> ((i%4)*2)) & 0x3) { |
case 0: mdata[0][j] = SC_LOGIC_1; break; |
case 1: mdata[1][j] = SC_LOGIC_1; break; |
case 2: mdata[2][j] = SC_LOGIC_1; break; |
case 3: mdata[3][j] = SC_LOGIC_1; break; |
} |
} |
} else { |
for(i=0; i<ChBW*4; i++) { |
switch((mflit[i/4] >> ((i%4)*2)) & 0x3) { |
case 0: mdata[0][i] = SC_LOGIC_1; break; |
case 1: mdata[1][i] = SC_LOGIC_1; break; |
case 2: mdata[2][i] = SC_LOGIC_1; break; |
case 3: mdata[3][i] = SC_LOGIC_1; break; |
} |
} |
} |
|
// write to the port |
rtid[0].write(mdata[0]); |
rtid[1].write(mdata[1]); |
rtid[2].write(mdata[2]); |
rtid[3].write(mdata[3]); |
|
// wait for the router to capture the data |
wait(rtinp_sig.posedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
|
// clear the data |
mdata[0] = 0; |
mdata[1] = 0; |
mdata[2] = 0; |
mdata[3] = 0; |
|
rtid[0].write(mdata[0]); |
rtid[1].write(mdata[1]); |
rtid[2].write(mdata[2]); |
rtid[3].write(mdata[3]); |
|
// wait for the input port be ready again |
wait(rtinp_sig.negedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
|
// check whether a tailf flit is needed |
if(mflit.ftype == F_TL) { |
// write the eof |
rtid4.write(~mdata4); |
|
// wait for the router to capture the data |
wait(rtinp_sig.posedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
|
// clear the eof |
rtid4.write(~mdata4); |
|
// wait for the input port be ready again |
wait(rtinp_sig.negedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
} |
} |
} |
|
void RTDriver::recv() { |
FLIT mflit; // the local flit buffer |
sc_lv<ChBW*4> mdata[4]; // local data copy |
#ifdef ENABLE_CHANNEL_CLISING |
sc_lv<ChBW*4> mdata4; // local copy of eof |
sc_lv<ChBW*4> mack = 0; // local copy of ack |
#else |
sc_logic mdata4; // local copy of eof |
sc_logic mack = SC_LOGIC_0; // local copy of ack |
#endif |
sc_lv<4> dd; // the current 1-of-4 data under process |
unsigned int i, j; // local loop index |
|
bool is_hd = true; // the current flit is a header flit |
|
while(true) { |
// clear the flit |
mflit.clear(); |
|
// wait for an incoming flit |
wait(rtoutp_sig.posedge_event()); |
|
// analyse the flit |
mdata[0] = rtod[0].read(); |
mdata[1] = rtod[1].read(); |
mdata[2] = rtod[2].read(); |
mdata[3] = rtod[3].read(); |
mdata4 = rtod4.read(); |
|
if(is_hd) { |
mflit.ftype = F_HD; |
is_hd = false; |
} |
#ifdef ENABLE_CHANNEL_CLISING |
else if(mdata4[0].to_bool()) { |
mflit.ftype = F_TL; |
is_hd = true; |
} |
#else |
else if(mdata4.to_bool()) { |
mflit.ftype = F_TL; |
is_hd = true; |
} |
#endif |
else { |
mflit.ftype = F_DAT; |
} |
|
if(mflit.ftype == F_HD) { |
// fetch the address |
dd[0] = mdata[0][0]; dd[1] = mdata[1][0]; dd[2] = mdata[2][0]; dd[3] = mdata[3][0]; |
mflit.addrx |= (c1o42b(dd.to_uint()) << 0); |
dd[0] = mdata[0][1]; dd[1] = mdata[1][1]; dd[2] = mdata[2][1]; dd[3] = mdata[3][1]; |
mflit.addrx |= (c1o42b(dd.to_uint()) << 2); |
dd[0] = mdata[0][2]; dd[1] = mdata[1][2]; dd[2] = mdata[2][2]; dd[3] = mdata[3][2]; |
mflit.addry |= (c1o42b(dd.to_uint()) << 0); |
dd[0] = mdata[0][3]; dd[1] = mdata[1][3]; dd[2] = mdata[2][3]; dd[3] = mdata[3][3]; |
mflit.addry |= (c1o42b(dd.to_uint()) << 2); |
|
// fill in data |
for(i=1; i<ChBW; i++) { |
for(j=0; j<4; j++) { |
dd[0] = mdata[0][i*4+j]; |
dd[1] = mdata[1][i*4+j]; |
dd[2] = mdata[2][i*4+j]; |
dd[3] = mdata[3][i*4+j]; |
mflit[i-1] |= c1o42b(dd.to_uint()) << j; |
} |
} |
} else if (mflit.ftype != F_TL) { |
// fill in data |
for(i=0; i<ChBW; i++) { |
for(j=0; j<4; j++) { |
dd[0] = mdata[0][i*4+j]; |
dd[1] = mdata[1][i*4+j]; |
dd[2] = mdata[2][i*4+j]; |
dd[3] = mdata[3][i*4+j]; |
mflit[i] |= c1o42b(dd.to_uint()) << j; |
} |
} |
} |
|
// send the flit to the NI |
P2NI->write(mflit); |
|
wait(0.2, SC_NS); // a delay to avoid data override |
rtoa.write(~mack); // notify that data is captured |
|
// wait for the data withdrawal |
wait(rtoutp_sig.negedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
rtoa.write(mack); // notify that data is captured |
|
} |
} |
|
unsigned int RTDriver::c1o42b(unsigned int dd) { |
switch(dd) { |
case 1: return 0; |
case 2: return 1; |
case 4: return 2; |
case 8: return 3; |
default: return 0xff; |
} |
} |
/async_sdm_noc/branches/init/sdm/tb/noc_top.v
0,0 → 1,136
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The mesh network for simulation. |
|
History: |
03/03/2011 Initial version. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module noc_top(/*AUTOARG*/ |
// Inputs |
rst_n |
); |
input rst_n; |
|
|
parameter DW = 32; |
parameter VCN = 1; |
parameter DIMX = 8; |
parameter DIMY = 8; |
parameter SCN = DW/2; |
|
wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] di0, di1, di2, di3; |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] do0, do1, do2, do3; |
`ifdef ENABLE_CHANNEL_SLICING |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] di4, dia; |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN*SCN-1:0] do4, doa; |
`else |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] di4, dia; |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] do4, doa; |
`endif |
|
genvar x, y; |
|
generate for(x=0; x<DIMX; x++) begin: DX |
for(y=0; y<DIMY; y++) begin: DY |
|
node_top #(.DW(DW), .VCN(VCN), .x(x), .y(y)) |
NN ( |
.si0 (di0[x][y][0]), .si1 (di1[x][y][0]), .si2 (di2[x][y][0]), .si3 (di3[x][y][0]), .si4 (di4[x][y][0]), .sia (dia[x][y][0]), |
.wi0 (di0[x][y][1]), .wi1 (di1[x][y][1]), .wi2 (di2[x][y][1]), .wi3 (di3[x][y][1]), .wi4 (di4[x][y][1]), .wia (dia[x][y][1]), |
.ni0 (di0[x][y][2]), .ni1 (di1[x][y][2]), .ni2 (di2[x][y][2]), .ni3 (di3[x][y][2]), .ni4 (di4[x][y][2]), .nia (dia[x][y][2]), |
.ei0 (di0[x][y][3]), .ei1 (di1[x][y][3]), .ei2 (di2[x][y][3]), .ei3 (di3[x][y][3]), .ei4 (di4[x][y][3]), .eia (dia[x][y][3]), |
.so0 (do0[x][y][0]), .so1 (do1[x][y][0]), .so2 (do2[x][y][0]), .so3 (do3[x][y][0]), .so4 (do4[x][y][0]), .soa (doa[x][y][0]), |
.wo0 (do0[x][y][1]), .wo1 (do1[x][y][1]), .wo2 (do2[x][y][1]), .wo3 (do3[x][y][1]), .wo4 (do4[x][y][1]), .woa (doa[x][y][1]), |
.no0 (do0[x][y][2]), .no1 (do1[x][y][2]), .no2 (do2[x][y][2]), .no3 (do3[x][y][2]), .no4 (do4[x][y][2]), .noa (doa[x][y][2]), |
.eo0 (do0[x][y][3]), .eo1 (do1[x][y][3]), .eo2 (do2[x][y][3]), .eo3 (do3[x][y][3]), .eo4 (do4[x][y][3]), .eoa (doa[x][y][3]), |
.rst_n(rst_n) |
); |
|
// north link |
if(x==0) begin |
assign di0[x][y][2] = do0[x][y][2]; |
assign di1[x][y][2] = do1[x][y][2]; |
assign di2[x][y][2] = do2[x][y][2]; |
assign di3[x][y][2] = do3[x][y][2]; |
assign di4[x][y][2] = do4[x][y][2]; |
assign doa[x][y][2] = dia[x][y][2]; |
end else begin |
assign di0[x][y][2] = do0[x-1][y][0]; |
assign di1[x][y][2] = do1[x-1][y][0]; |
assign di2[x][y][2] = do2[x-1][y][0]; |
assign di3[x][y][2] = do3[x-1][y][0]; |
assign di4[x][y][2] = do4[x-1][y][0]; |
assign doa[x-1][y][0] = dia[x][y][2]; |
end |
|
// south link |
if(x==DIMX-1) begin |
assign di0[x][y][0] = do0[x][y][0]; |
assign di1[x][y][0] = do1[x][y][0]; |
assign di2[x][y][0] = do2[x][y][0]; |
assign di3[x][y][0] = do3[x][y][0]; |
assign di4[x][y][0] = do4[x][y][0]; |
assign doa[x][y][0] = dia[x][y][0]; |
end else begin |
assign di0[x][y][0] = do0[x+1][y][2]; |
assign di1[x][y][0] = do1[x+1][y][2]; |
assign di2[x][y][0] = do2[x+1][y][2]; |
assign di3[x][y][0] = do3[x+1][y][2]; |
assign di4[x][y][0] = do4[x+1][y][2]; |
assign doa[x+1][y][2] = dia[x][y][0]; |
end |
|
// west link |
if(y==0) begin |
assign di0[x][y][1] = do0[x][y][1]; |
assign di1[x][y][1] = do1[x][y][1]; |
assign di2[x][y][1] = do2[x][y][1]; |
assign di3[x][y][1] = do3[x][y][1]; |
assign di4[x][y][1] = do4[x][y][1]; |
assign doa[x][y][1] = dia[x][y][1]; |
end else begin |
assign di0[x][y][1] = do0[x][y-1][3]; |
assign di1[x][y][1] = do1[x][y-1][3]; |
assign di2[x][y][1] = do2[x][y-1][3]; |
assign di3[x][y][1] = do3[x][y-1][3]; |
assign di4[x][y][1] = do4[x][y-1][3]; |
assign doa[x][y-1][3] = dia[x][y][1]; |
end // else: !if(y==0) |
|
// east link |
if(y==DIMY-1) begin |
assign di0[x][y][3] = do0[x][y][3]; |
assign di1[x][y][3] = do1[x][y][3]; |
assign di2[x][y][3] = do2[x][y][3]; |
assign di3[x][y][3] = do3[x][y][3]; |
assign di4[x][y][3] = do4[x][y][3]; |
assign doa[x][y][3] = dia[x][y][3]; |
end else begin |
assign di0[x][y][3] = do0[x][y+1][1]; |
assign di1[x][y][3] = do1[x][y+1][1]; |
assign di2[x][y][3] = do2[x][y+1][1]; |
assign di3[x][y][3] = do3[x][y+1][1]; |
assign di4[x][y][3] = do4[x][y+1][1]; |
assign doa[x][y+1][1] = dia[x][y][3]; |
end // else: !if(y==DIMY-1) |
|
end // block: DY |
end // block: DX |
endgenerate |
|
endmodule // noc_top |
/async_sdm_noc/branches/init/sdm/tb/rtdriver.h
0,0 → 1,66
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The port driver between NI and router. |
|
History: |
27/04/2010 Initial version. <wsong83@gmail.com> |
16/10/2010 Support SDM. <wsong83@gmail.com> |
30/05/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com> |
|
*/ |
|
#ifndef RT_DRIVER_H_ |
#define RT_DRIVER_H_ |
|
#include "define.h" |
#include <systemc.h> |
#include "pdu_def.h" |
|
SC_MODULE(RTDriver) { |
|
public: |
// port with network interface |
sc_port<sc_fifo_in_if<FLIT> > NI2P; |
sc_port<sc_fifo_out_if<FLIT> > P2NI; |
|
// signals from interface to router |
sc_out<sc_lv<ChBW*4> > rtid [4]; |
sc_in<sc_lv<ChBW*4> > rtod [4]; |
|
#ifdef ENABLE_CHANNEL_CLISING |
sc_out<sc_lv<ChBW*4> > rtid4; |
sc_in<sc_lv<ChBW*4> > rtod4; |
sc_in<sc_lv<ChBW*4> > rtia; |
sc_out<sc_lv<ChBW*4> > rtoa; |
#else |
sc_out<sc_logic > rtid4; |
sc_in<sc_logic > rtod4; |
sc_in<sc_logic> rtia; |
sc_out<sc_logic> rtoa; |
#endif |
|
SC_HAS_PROCESS(RTDriver); |
RTDriver(sc_module_name name); |
|
void IPdetect(); // Method to detect the router input port |
void OPdetect(); // Method to detect the router output port |
void send(); // thread of sending a flit |
void recv(); // thread to recveive a flit |
|
sc_signal<bool> rtinp_sig; // fire when the router input port is ready for a new flit |
sc_signal<bool> rtoutp_sig; // fire when the router output port has a new flit |
|
unsigned int c1o42b(unsigned int); // convert 1-of-4 to binary |
}; |
|
|
#endif |
/async_sdm_noc/branches/init/sdm/tb/noctb.v
0,0 → 1,48
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Test bench. |
|
History: |
03/03/2011 Initial version. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
`timescale 1ns/1ps |
|
module noctb; |
parameter DW = 16; // the data width of a single virtual circuit |
parameter VCN = 2; // the number of virtual circuits per direction |
parameter DIMX = 4; // the X dimension |
parameter DIMY = 3; // the Y dimension |
|
reg rst_n; |
|
noc_top #(.DW(DW), .VCN(VCN), .DIMX(DIMX), .DIMY(DIMY)) |
NoC (.rst_n(rst_n)); // the mesh network |
|
AnaProc ANAM(); // the global performance analyser |
|
initial begin |
rst_n = 0; |
|
# 133; |
|
rst_n = 1; |
|
end |
|
endmodule // noctb |
|
|
|
|
/async_sdm_noc/branches/init/sdm/tb/rtwrapper.v
0,0 → 1,222
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The wrapper for the synthesized router. |
|
History: |
28/05/2009 Initial version. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module router_hdl(/*AUTOARG*/ |
// Outputs |
so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, |
eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia, |
wia, nia, eia, lia, |
// Inputs |
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, |
ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa, |
woa, noa, eoa, loa, addrx, addry, rst_n |
); |
|
parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router |
parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN |
parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit |
|
input [VCN*SCN-1:0] si0, si1, si2, si3; |
input [VCN*SCN-1:0] wi0, wi1, wi2, wi3; |
input [VCN*SCN-1:0] ni0, ni1, ni2, ni3; |
input [VCN*SCN-1:0] ei0, ei1, ei2, ei3; |
input [VCN*SCN-1:0] li0, li1, li2, li3; |
output [VCN*SCN-1:0] so0, so1, so2, so3; |
output [VCN*SCN-1:0] wo0, wo1, wo2, wo3; |
output [VCN*SCN-1:0] no0, no1, no2, no3; |
output [VCN*SCN-1:0] eo0, eo1, eo2, eo3; |
output [VCN*SCN-1:0] lo0, lo1, lo2, lo3; |
// eof bits and ack lines |
`ifdef ENABLE_CHANNEL_SLICING |
input [VCN*SCN-1:0] si4, wi4, ni4, ei4, li4; |
output [VCN*SCN-1:0] so4, wo4, no4, eo4, lo4; |
output [VCN*SCN-1:0] sia, wia, nia, eia, lia; |
input [VCN*SCN-1:0] soa, woa, noa, eoa, loa; |
`else |
input [VCN-1:0] si4, wi4, ni4, ei4, li4; |
output [VCN-1:0] so4, wo4, no4, eo4, lo4; |
output [VCN-1:0] sia, wia, nia, eia, lia; |
input [VCN-1:0] soa, woa, noa, eoa, loa; |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
input [7:0] addrx, addry; |
input rst_n; |
|
wire [VCN*SCN-1:0] psi0, psi1, psi2, psi3; |
wire [VCN*SCN-1:0] pwi0, pwi1, pwi2, pwi3; |
wire [VCN*SCN-1:0] pni0, pni1, pni2, pni3; |
wire [VCN*SCN-1:0] pei0, pei1, pei2, pei3; |
wire [VCN*SCN-1:0] pli0, pli1, pli2, pli3; |
wire [VCN*SCN-1:0] pso0, pso1, pso2, pso3; |
wire [VCN*SCN-1:0] pwo0, pwo1, pwo2, pwo3; |
wire [VCN*SCN-1:0] pno0, pno1, pno2, pno3; |
wire [VCN*SCN-1:0] peo0, peo1, peo2, peo3; |
wire [VCN*SCN-1:0] plo0, plo1, plo2, plo3; |
// eof bits and ack lines |
`ifdef ENABLE_CHANNEL_SLICING |
wire [VCN*SCN-1:0] psi4, pwi4, pni4, pei4, pli4; |
wire [VCN*SCN-1:0] pso4, pwo4, pno4, peo4, plo4; |
wire [VCN*SCN-1:0] psia, pwia, pnia, peia, plia; |
wire [VCN*SCN-1:0] psoa, pwoa, pnoa, peoa, ploa; |
`else |
wire [VCN-1:0] psi4, pwi4, pni4, pei4, pli4; |
wire [VCN-1:0] pso4, pwo4, pno4, peo4, plo4; |
wire [VCN-1:0] psia, pwia, pnia, peia, plia; |
wire [VCN-1:0] psoa, pwoa, pnoa, peoa, ploa; |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
wire [7:0] paddrx, paddry; |
wire prst_n; |
|
router_syn RT ( |
.sia ( psia ), |
.wia ( pwia ), |
.nia ( pnia ), |
.eia ( peia ), |
.lia ( plia ), |
.so0 ( pso0 ), |
.so1 ( pso1 ), |
.so2 ( pso2 ), |
.so3 ( pso3 ), |
.wo0 ( pwo0 ), |
.wo1 ( pwo1 ), |
.wo2 ( pwo2 ), |
.wo3 ( pwo3 ), |
.no0 ( pno0 ), |
.no1 ( pno1 ), |
.no2 ( pno2 ), |
.no3 ( pno3 ), |
.eo0 ( peo0 ), |
.eo1 ( peo1 ), |
.eo2 ( peo2 ), |
.eo3 ( peo3 ), |
.lo0 ( plo0 ), |
.lo1 ( plo1 ), |
.lo2 ( plo2 ), |
.lo3 ( plo3 ), |
.so4 ( pso4 ), |
.wo4 ( pwo4 ), |
.no4 ( pno4 ), |
.eo4 ( peo4 ), |
.lo4 ( plo4 ), |
.si0 ( psi0 ), |
.si1 ( psi1 ), |
.si2 ( psi2 ), |
.si3 ( psi3 ), |
.wi0 ( pwi0 ), |
.wi1 ( pwi1 ), |
.wi2 ( pwi2 ), |
.wi3 ( pwi3 ), |
.ni0 ( pni0 ), |
.ni1 ( pni1 ), |
.ni2 ( pni2 ), |
.ni3 ( pni3 ), |
.ei0 ( pei0 ), |
.ei1 ( pei1 ), |
.ei2 ( pei2 ), |
.ei3 ( pei3 ), |
.li0 ( pli0 ), |
.li1 ( pli1 ), |
.li2 ( pli2 ), |
.li3 ( pli3 ), |
.si4 ( psi4 ), |
.wi4 ( pwi4 ), |
.ni4 ( pni4 ), |
.ei4 ( pei4 ), |
.li4 ( pli4 ), |
.soa ( psoa ), |
.woa ( pwoa ), |
.noa ( pnoa ), |
.eoa ( peoa ), |
.loa ( ploa ), |
.addrx ( paddrx ), |
.addry ( paddry ), |
.rst_n ( prst_n ) |
); |
|
assign sia = psia ; |
assign wia = pwia ; |
assign nia = pnia ; |
assign eia = peia ; |
assign lia = plia ; |
assign so0 = pso0 ; |
assign so1 = pso1 ; |
assign so2 = pso2 ; |
assign so3 = pso3 ; |
assign wo0 = pwo0 ; |
assign wo1 = pwo1 ; |
assign wo2 = pwo2 ; |
assign wo3 = pwo3 ; |
assign no0 = pno0 ; |
assign no1 = pno1 ; |
assign no2 = pno2 ; |
assign no3 = pno3 ; |
assign eo0 = peo0 ; |
assign eo1 = peo1 ; |
assign eo2 = peo2 ; |
assign eo3 = peo3 ; |
assign lo0 = plo0 ; |
assign lo1 = plo1 ; |
assign lo2 = plo2 ; |
assign lo3 = plo3 ; |
assign so4 = pso4 ; |
assign wo4 = pwo4 ; |
assign no4 = pno4 ; |
assign eo4 = peo4 ; |
assign lo4 = plo4 ; |
assign psi0 = si0 ; |
assign psi1 = si1 ; |
assign psi2 = si2 ; |
assign psi3 = si3 ; |
assign pwi0 = wi0 ; |
assign pwi1 = wi1 ; |
assign pwi2 = wi2 ; |
assign pwi3 = wi3 ; |
assign pni0 = ni0 ; |
assign pni1 = ni1 ; |
assign pni2 = ni2 ; |
assign pni3 = ni3 ; |
assign pei0 = ei0 ; |
assign pei1 = ei1 ; |
assign pei2 = ei2 ; |
assign pei3 = ei3 ; |
assign pli0 = li0 ; |
assign pli1 = li1 ; |
assign pli2 = li2 ; |
assign pli3 = li3 ; |
assign psi4 = si4 ; |
assign pwi4 = wi4 ; |
assign pni4 = ni4 ; |
assign pei4 = ei4 ; |
assign pli4 = li4 ; |
assign psoa = soa ; |
assign pwoa = woa ; |
assign pnoa = noa ; |
assign peoa = eoa ; |
assign ploa = loa ; |
assign paddrx = addrx ; |
assign paddry = addry ; |
assign prst_n = rst_n ; |
|
initial $sdf_annotate("../syn/file/router.sdf", RT); |
|
endmodule |
async_sdm_noc/branches/init/sdm/tb/rtwrapper.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: async_sdm_noc/branches/init/sdm/tb/node_top.v
===================================================================
--- async_sdm_noc/branches/init/sdm/tb/node_top.v (nonexistent)
+++ async_sdm_noc/branches/init/sdm/tb/node_top.v (revision 32)
@@ -0,0 +1,117 @@
+/*
+ Asynchronous SDM NoC
+ (C)2011 Wei Song
+ Advanced Processor Technologies Group
+ Computer Science, the Univ. of Manchester, UK
+
+ Authors:
+ Wei Song wsong83@gmail.com
+
+ License: LGPL 3.0 or later
+
+ A network node including a router, a NI and a processing element.
+
+ History:
+ 03/03/2011 Initial version.
+ 30/05/2011 Clean up for opensource.
+
+*/
+
+// the router structure definitions
+`include "define.v"
+
+module node_top(/*AUTOARG*/
+ // Outputs
+ so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
+ eo1, eo2, eo3, sia, wia, nia, eia, so4, wo4, no4, eo4,
+ // Inputs
+ si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
+ ei1, ei2, ei3, si4, wi4, ni4, ei4, soa, woa, noa, eoa, rst_n
+ );
+ parameter DW = 32;
+ parameter VCN = 1;
+ parameter x = 0;
+ parameter y = 0;
+ parameter SCN = DW/2;
+
+ input [VCN*SCN-1:0] si0, si1, si2, si3;
+ input [VCN*SCN-1:0] wi0, wi1, wi2, wi3;
+ input [VCN*SCN-1:0] ni0, ni1, ni2, ni3;
+ input [VCN*SCN-1:0] ei0, ei1, ei2, ei3;
+ output [VCN*SCN-1:0] so0, so1, so2, so3;
+ output [VCN*SCN-1:0] wo0, wo1, wo2, wo3;
+ output [VCN*SCN-1:0] no0, no1, no2, no3;
+ output [VCN*SCN-1:0] eo0, eo1, eo2, eo3;
+ wire [VCN*SCN-1:0] li0, li1, li2, li3;
+ wire [VCN*SCN-1:0] lo0, lo1, lo2, lo3;
+`ifdef ENABLE_CHANNEL_SLICING
+ input [VCN*SCN-1:0] si4, wi4, ni4, ei4;
+ output [VCN*SCN-1:0] sia, wia, nia, eia;
+ output [VCN*SCN-1:0] so4, wo4, no4, eo4;
+ input [VCN*SCN-1:0] soa, woa, noa, eoa;
+ wire [VCN*SCN-1:0] li4, lia, lo4, loa;
+`else
+ input [VCN-1:0] si4, wi4, ni4, ei4;
+ output [VCN-1:0] sia, wia, nia, eia;
+ output [VCN-1:0] so4, wo4, no4, eo4;
+ input [VCN-1:0] soa, woa, noa, eoa;
+ wire [VCN-1:0] li4, lia, lo4, loa;
+`endif // !`ifdef ENABLE_CHANNEL_SLICING
+
+ input rst_n;
+
+
+ // the network node
+ NetNode #(.DW(DW), .VCN(VCN), .x(x), .y(y))
+ Node (
+ .dia ( lia ),
+ .do4 ( lo4 ),
+ .doa ( loa ),
+ .di4 ( li4 ),
+ .do0 ( lo0 ),
+ .do1 ( lo1 ),
+ .do2 ( lo2 ),
+ .do3 ( lo3 ),
+ .di0 ( li0 ),
+ .di1 ( li1 ),
+ .di2 ( li2 ),
+ .di3 ( li3 ),
+ .rst_n ( rst_n )
+ );
+
+
+ // router wrapper
+ router_hdl #(.DW(DW), .VCN(VCN))
+ RTN (
+ .so0(so0), .so1(so1), .so2(so2), .so3(so3), .so4(so4), .soa(soa),
+ .wo0(wo0), .wo1(wo1), .wo2(wo2), .wo3(wo3), .wo4(wo4), .woa(woa),
+ .no0(no0), .no1(no1), .no2(no2), .no3(no3), .no4(no4), .noa(noa),
+ .eo0(eo0), .eo1(eo1), .eo2(eo2), .eo3(eo3), .eo4(eo4), .eoa(eoa),
+ .lo0(lo0), .lo1(lo1), .lo2(lo2), .lo3(lo3), .lo4(lo4), .loa(loa),
+ .si0(si0), .si1(si1), .si2(si2), .si3(si3), .si4(si4), .sia(sia),
+ .wi0(wi0), .wi1(wi1), .wi2(wi2), .wi3(wi3), .wi4(wi4), .wia(wia),
+ .ni0(ni0), .ni1(ni1), .ni2(ni2), .ni3(ni3), .ni4(ni4), .nia(nia),
+ .ei0(ei0), .ei1(ei1), .ei2(ei2), .ei3(ei3), .ei4(ei4), .eia(eia),
+ .li0(li0), .li1(li1), .li2(li2), .li3(li3), .li4(li4), .lia(lia),
+ .addrx (b2chain(x)),
+ .addry (b2chain(y)),
+ .rst_n (rst_n)
+ );
+
+
+ // binary to 1-of-4 (Chain) converter
+ function [7:0] b2chain;
+ input [3:0] data;
+ begin
+ b2chain[0] = (data[1:0] == 2'b00);
+ b2chain[1] = (data[1:0] == 2'b01);
+ b2chain[2] = (data[1:0] == 2'b10);
+ b2chain[3] = (data[1:0] == 2'b11);
+ b2chain[4] = (data[3:2] == 2'b00);
+ b2chain[5] = (data[3:2] == 2'b01);
+ b2chain[6] = (data[3:2] == 2'b10);
+ b2chain[7] = (data[3:2] == 2'b11);
+ end
+ endfunction
+
+endmodule // node_top
Index: async_sdm_noc/branches/init/sdm/tb/ni.h
===================================================================
--- async_sdm_noc/branches/init/sdm/tb/ni.h (revision 31)
+++ async_sdm_noc/branches/init/sdm/tb/ni.h (revision 32)
@@ -15,7 +15,7 @@
20/08/2008 Initial version.
30/09/2010 Use template style packet definition.
16/10/2010 Support SDM.
- 29/05/2011 CLean up for opensource.
+ 30/05/2011 CLean up for opensource.
*/
@@ -22,7 +22,7 @@
#ifndef NETWORK_ADAPTER_H_
#define NETWORK_ADAPTER_H_
-#include "noc_define.h"
+#include "define.h"
#include
SC_MODULE(Network_Adapter)
/async_sdm_noc/branches/init/sdm/sim/compile.sh
0,0 → 1,57
#!/bin/bash |
# |
# Asynchronous SDM NoC |
# (C)2011 Wei Song |
# Advanced Processor Technologies Group |
# Computer Science, the Univ. of Manchester, UK |
# |
# Authors: |
# Wei Song wsong83@gmail.com |
# |
# License: LGPL 3.0 or later |
# |
# The script to compile the SystemC/Verilog mixed NoC simulation |
# |
# History: |
# 29/05/2011 CLean up for opensource. <wsong83@gmail.com> |
# |
|
# make sure the LDVHOME environment is ready for NC-Simulator, IUS/LDV, Cadence |
export NCSC_GCC=${LDVHOME}/tools/systemc/gcc/bin/g++ |
|
CXXFLAG="-c -g -Wall -I../../common/tb -I../tb -I../" |
|
# remove the files from last run |
rm -fr INCA_libs |
rm *.o |
|
# compile verilog files |
# cell library |
ncvlog -nowarn RECOMP ../../lib/NangateOpenCellLibrary_typical_conditional.v |
# synthesized design |
ncvlog ../syn/file/router_syn.v |
# other verilog test bench files |
ncvlog -incdir ../ ../../common/tb/anaproc.v |
ncvlog -sv -incdir ../ ../tb/rtwrapper.v |
ncvlog -incdir ../ ../tb/netnode.v |
ncvlog -sv -incdir ../ ../tb/noc_top.v |
ncvlog -sv -incdir ../ ../tb/node_top.v |
ncvlog ../tb/noctb.v |
|
#compile SystemC files |
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../../common/tb/sim_ana.cpp |
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../../common/tb/anaproc.cpp |
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/netnode.cpp |
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/ni.cpp |
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/rtdriver.cpp |
|
# build the run time link library |
${NCSC_GCC} -Wl -shared -o sysc.so -L${CDS_LNX86_ROOT}/ldv_2009_sc/tools/lib \ |
sim_ana.o anaproc.o netnode.o ni.o rtdriver.o \ |
${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libncscCoSim_sh.so \ |
${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libncscCoroutines_sh.so \ |
${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libsystemc_sh.so |
|
# elaborate the simulation |
ncelab -timescale 1ns/1ps -access +rwc -loadsc sysc.so worklib.noctb |
|
async_sdm_noc/branches/init/sdm/sim/compile.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: async_sdm_noc/branches/init/sdm/syn/script/compile.tcl
===================================================================
--- async_sdm_noc/branches/init/sdm/syn/script/compile.tcl (revision 31)
+++ async_sdm_noc/branches/init/sdm/syn/script/compile.tcl (revision 32)
@@ -56,9 +56,8 @@
define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
change_name -rules verilog -hierarchy
-write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design
-write_sdf -significant_digits 5 file/${current_design}.sdf
-write_sdc file/${current_design}.sdc
+write -format verilog -hierarchy -out file/router_syn.v $current_design
+write_sdf -significant_digits 5 file/router.sdf
report_constraints -verbose
/async_sdm_noc/branches/init/common/tb/anaproc.v
0,0 → 1,32
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The SystemC to keep a module of the simulation analysis object. |
|
History: |
27/02/2011 Initial version. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module AnaProc () |
// |
// The foreign attribute string value must be a SystemC value. |
// |
(* integer foreign = "SystemC"; |
*); |
// |
// Verilog port names must match port names exactly as they appear in the |
// sc_module class in SystemC; they must also match in order, mode, and type. |
// |
|
endmodule |
|
/async_sdm_noc/branches/init/common/tb/pdu_def.h
18,6 → 18,7
21/09/2010 Support VC and use templates. <wsong83@gmail.com> |
19/11/2010 Fixed to support the minimal 8bit VC. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
30/05/2011 Clear the addresses field when clear a flit. <wsong83@gmail.com> |
|
*/ |
|
99,6 → 100,8
vcn = 0; |
prio = 0; |
ftype = F_IDLE; |
addrx = 0; |
addry = 0; |
for(unsigned int i=0; i<BW; i++) data[i] = 0; |
} |
|
/async_sdm_noc/branches/init/common/tb/procelem.h
13,7 → 13,7
|
History: |
26/02/2011 Initial version. <wsong83@gmail.com> |
28/05/2011 Clean up for opensource. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
20,13 → 20,13
#ifndef PROCELEM_H_ |
#define PROCELEM_H_ |
|
#include "noc_define.h" |
#include "define.h" |
#include <systemc.h> |
|
|
// a function to generate random numbers comply with an exponential distribution with expection exp |
double rand_exp(double exp) { |
unsigned int rint = rand()%1e6; |
double rand_exponential(double exp) { |
unsigned int rint = rand() % (unsigned int)(1e6); |
double rdat = rint * 1.0 / 1e6; |
return (-1 * exp * log(rint)); |
} |