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/trunk/implement/results/lq057q3dc02_top_map.twr
0,0 → 1,87
--------------------------------------------------------------------------------
Release 9.2.04i Trace
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
 
trce -e 10 lq057q3dc02_top.ncd -o lq057q3dc02_top_map.twr lq057q3dc02_top.pcf
 
Design file: lq057q3dc02_top.ncd
Physical constraint file: lq057q3dc02_top.pcf
Device,package,speed: xc2vp30,ff896,-7 (PRODUCTION 1.94 2007-10-19)
Report level: error report, limited to 10 items per constraint
 
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
 
================================================================================
Timing constraint: NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%;
 
0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: PERIOD analysis for net "DCM_LCD_CLK/CLKDV_BUF" derived from
NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%; multiplied by
16.00 and duty cycle corrected to 160 nS HIGH 80 nS
 
3903 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 6.871ns.
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: NET "CLK_LCD" PERIOD = 160 ns HIGH 50%;
 
0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
All constraints were met.
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Clock to Setup on destination clock CLK_100M_PAD
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_100M_PAD | 6.871| | | |
---------------+---------+---------+---------+---------+
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0
 
Constraints cover 3903 paths, 0 nets, and 2359 connections
 
Design statistics:
Minimum period: 6.871ns (Maximum frequency: 145.539MHz)
 
 
Analysis completed Thu Nov 06 13:56:36 2008
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 154 MB
 
 
 
/trunk/implement/results/lq057q3dc02_top_part.srp
0,0 → 1,689
Release 9.2.04i - xst J.40
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> -->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input Format : MIXED
Input File Name : "../xst.prj"
 
---- Target Parameters
Target Device : xc2vp30-ff896-7
Output File Name : "lq057q3dc02_top_part"
 
---- Source Options
Top Module Name : lq057q3dc02_top
 
---- Target Options
Equivalent register Removal : no
Global Maximum Fanout : 65535
 
---- General Options
Optimization Goal : SPEED
Optimization Effort : 1
Keep Hierarchy : soft
 
=========================================================================
 
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/components.vhd" in Library work_vhsic.
Package <components> compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/hsyncx_control.vhd" in Library work_vhsic.
Entity <hsyncx_control> compiled.
Entity <hsyncx_control> (Architecture <hsyncx_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/vsyncx_control.vhd" in Library work_vhsic.
Entity <vsyncx_control> compiled.
Entity <vsyncx_control> (Architecture <vsyncx_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/clk_lcd_cyc_cntr.vhd" in Library work_vhsic.
Entity <clk_lcd_cyc_cntr> compiled.
Entity <clk_lcd_cyc_cntr> (Architecture <clk_lcd_cyc_cntr_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/enab_control.vhd" in Library work_vhsic.
Entity <enab_control> compiled.
Entity <enab_control> (Architecture <enab_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/dcm_sys_to_lcd.vhd" in Library work_vhsic.
Entity <dcm_sys_to_lcd> compiled.
Entity <dcm_sys_to_lcd> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/video_controller.vhd" in Library work_vhsic.
Entity <video_controller> compiled.
Entity <video_controller> (Architecture <video_controller_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/image_gen_bram.vhd" in Library work_vhsic.
Entity <image_gen_bram> compiled.
Entity <image_gen_bram> (Architecture <image_gen_bram_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" in Library work_vhsic.
Entity <lq057q3dc02_top> compiled.
Entity <lq057q3dc02_top> (Architecture <lq057q3dc02_top_arch>) compiled.
 
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <lq057q3dc02_top> in library <work_vhsic> (architecture <lq057q3dc02_top_arch>) with generics.
C_BIT_DEPTH = 18
C_BRAM_ADDR_WIDTH = 17
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_HSYNC_TH = 400
C_HSYNC_THP = 10
C_IMAGE_HEIGHT = 240
C_IMAGE_WIDTH = 320
C_LINE_NUM_WIDTH = 9
C_NUM_CLKS_WIDTH = 9
C_RL_STATUS = '0'
C_UD_STATUS = '1'
C_VQ_STATUS = '0'
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
C_VSYNC_TVS = 7
 
Analyzing hierarchy for entity <dcm_sys_to_lcd> in library <work_vhsic> (architecture <BEHAVIORAL>).
 
Analyzing hierarchy for entity <video_controller> in library <work_vhsic> (architecture <video_controller_arch>) with generics.
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_HSYNC_TH = 400
C_HSYNC_THP = 10
C_LINE_NUM_WIDTH = 9
C_NUM_CLKS_WIDTH = 9
C_RL_STATUS = '0'
C_UD_STATUS = '1'
C_VQ_STATUS = '0'
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
C_VSYNC_TVS = 7
 
Analyzing hierarchy for entity <image_gen_bram> in library <work_vhsic> (architecture <image_gen_bram_arch>) with generics.
C_BIT_DEPTH = 18
C_BRAM_ADDR_WIDTH = 17
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_IMAGE_HEIGHT = 240
C_IMAGE_WIDTH = 320
C_LINE_NUM_WIDTH = 9
C_VSYNC_TVS = 7
 
Analyzing hierarchy for entity <hsyncx_control> in library <work_vhsic> (architecture <hsyncx_control_arch>) with generics.
C_HSYNC_TH = 400
C_HSYNC_THP = 10
C_NUM_CLKS_WIDTH = 9
 
Analyzing hierarchy for entity <vsyncx_control> in library <work_vhsic> (architecture <vsyncx_control_arch>) with generics.
C_LINE_NUM_WIDTH = 9
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
 
Analyzing hierarchy for entity <clk_lcd_cyc_cntr> in library <work_vhsic> (architecture <clk_lcd_cyc_cntr_arch>) with generics.
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_LINE_NUM_WIDTH = 9
C_VSYNC_TVS = 7
 
Analyzing hierarchy for entity <enab_control> in library <work_vhsic> (architecture <enab_control_arch>) with generics.
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_VSYNC_TVS = 7
 
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing generic Entity <lq057q3dc02_top> in library <work_vhsic> (Architecture <lq057q3dc02_top_arch>).
C_BIT_DEPTH = 18
C_BRAM_ADDR_WIDTH = 17
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_HSYNC_TH = 400
C_HSYNC_THP = 10
C_IMAGE_HEIGHT = 240
C_IMAGE_WIDTH = 320
C_LINE_NUM_WIDTH = 9
C_NUM_CLKS_WIDTH = 9
C_RL_STATUS = '0'
C_UD_STATUS = '1'
C_VQ_STATUS = '0'
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
C_VSYNC_TVS = 7
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLK0_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKFX_OUT' of component 'dcm_sys_to_lcd'.
Entity <lq057q3dc02_top> analyzed. Unit <lq057q3dc02_top> generated.
 
Analyzing Entity <dcm_sys_to_lcd> in library <work_vhsic> (Architecture <BEHAVIORAL>).
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <CLKIN_IBUFG_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "FACTORY_JF = C080" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLKFX_DIVIDE = 4" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLKIN_DIVIDE_BY_2 = TRUE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLKDV_DIVIDE = 8.0000000000000000" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLK_FEEDBACK = 1X" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLKFX_MULTIPLY = 2" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLKIN_PERIOD = 20.0000000000000000" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "DSS_MODE = NONE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "PHASE_SHIFT = 0" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Set user-defined property "STARTUP_WAIT = TRUE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Entity <dcm_sys_to_lcd> analyzed. Unit <dcm_sys_to_lcd> generated.
 
Analyzing generic Entity <video_controller> in library <work_vhsic> (Architecture <video_controller_arch>).
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_HSYNC_TH = 400
C_HSYNC_THP = 10
C_LINE_NUM_WIDTH = 9
C_NUM_CLKS_WIDTH = 9
C_RL_STATUS = '0'
C_UD_STATUS = '1'
C_VQ_STATUS = '0'
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
C_VSYNC_TVS = 7
Entity <video_controller> analyzed. Unit <video_controller> generated.
 
Analyzing generic Entity <hsyncx_control> in library <work_vhsic> (Architecture <hsyncx_control_arch>).
C_HSYNC_TH = 400
C_HSYNC_THP = 10
C_NUM_CLKS_WIDTH = 9
Entity <hsyncx_control> analyzed. Unit <hsyncx_control> generated.
 
Analyzing generic Entity <vsyncx_control> in library <work_vhsic> (Architecture <vsyncx_control_arch>).
C_LINE_NUM_WIDTH = 9
C_VSYNC_TV = 255
C_VSYNC_TVP = 3
Entity <vsyncx_control> analyzed. Unit <vsyncx_control> generated.
 
Analyzing generic Entity <clk_lcd_cyc_cntr> in library <work_vhsic> (Architecture <clk_lcd_cyc_cntr_arch>).
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_LINE_NUM_WIDTH = 9
C_VSYNC_TVS = 7
Entity <clk_lcd_cyc_cntr> analyzed. Unit <clk_lcd_cyc_cntr> generated.
 
Analyzing generic Entity <enab_control> in library <work_vhsic> (Architecture <enab_control_arch>).
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_VSYNC_TVS = 7
Entity <enab_control> analyzed. Unit <enab_control> generated.
 
Analyzing generic Entity <image_gen_bram> in library <work_vhsic> (Architecture <image_gen_bram_arch>).
C_BIT_DEPTH = 18
C_BRAM_ADDR_WIDTH = 17
C_CLK_LCD_CYC_NUM_WIDTH = 9
C_ENAB_TEP = 320
C_ENAB_THE = 8
C_IMAGE_HEIGHT = 240
C_IMAGE_WIDTH = 320
C_LINE_NUM_WIDTH = 9
C_VSYNC_TVS = 7
Entity <image_gen_bram> analyzed. Unit <image_gen_bram> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit <hsyncx_control>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/hsyncx_control.vhd".
Found 1-bit register for signal <HSYNCx>.
Found 10-bit comparator less for signal <HSYNCx$cmp_lt0000> created at line 136.
Found 9-bit up counter for signal <num_hsyncx_clks_reg>.
Summary:
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <hsyncx_control> synthesized.
 
 
Synthesizing Unit <vsyncx_control>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/vsyncx_control.vhd".
Found finite state machine <FSM_0> for signal <Line_Cntr_cs>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 8 |
| Inputs | 2 |
| Outputs | 2 |
| Clock | CLK_LCD (rising_edge) |
| Reset | RSTx (negative) |
| Reset type | asynchronous |
| Reset State | ready |
| Power Up State | frame_start |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <VSYNCx>.
Found 9-bit up counter for signal <line_num_reg>.
Found 10-bit comparator less for signal <VSYNCx$cmp_lt0000> created at line 382.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <vsyncx_control> synthesized.
 
 
Synthesizing Unit <clk_lcd_cyc_cntr>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/clk_lcd_cyc_cntr.vhd".
Found finite state machine <FSM_1> for signal <CLK_Cntr_cs>.
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 12 |
| Inputs | 6 |
| Outputs | 1 |
| Clock | CLK_LCD (rising_edge) |
| Reset | RSTx (negative) |
| Reset type | asynchronous |
| Reset State | inactive_wait_1 |
| Power Up State | inactive_wait_1 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 10-bit comparator less for signal <CLK_Cntr_cs$cmp_lt0000> created at line 205.
Found 9-bit up counter for signal <clk_cyc_num_reg>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 1 Comparator(s).
Unit <clk_lcd_cyc_cntr> synthesized.
 
 
Synthesizing Unit <enab_control>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/enab_control.vhd".
Found 1-bit register for signal <ENAB>.
Found 10-bit comparator greatequal for signal <ENAB$cmp_ge0000> created at line 131.
Found 10-bit comparator less for signal <ENAB$cmp_lt0000> created at line 131.
Summary:
inferred 1 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <enab_control> synthesized.
 
 
Synthesizing Unit <dcm_sys_to_lcd>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/dcm_sys_to_lcd.vhd".
Unit <dcm_sys_to_lcd> synthesized.
 
 
Synthesizing Unit <video_controller>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/video_controller.vhd".
Unit <video_controller> synthesized.
 
 
Synthesizing Unit <image_gen_bram>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/image_gen_bram.vhd".
Found 17-bit up counter for signal <ADDR_wire>.
Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0000> created at line 235.
Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0001> created at line 241.
Found 10-bit comparator less for signal <ADDR_wire$cmp_lt0000> created at line 235.
Found 1-bit register for signal <SINIT_wire>.
Found 10-bit comparator greatequal for signal <SINIT_wire$cmp_ge0000> created at line 186.
Found 10-bit comparator less for signal <SINIT_wire$cmp_lt0000> created at line 186.
Found 10-bit comparator less for signal <SINIT_wire$cmp_lt0001> created at line 186.
Summary:
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 6 Comparator(s).
Unit <image_gen_bram> synthesized.
 
 
Synthesizing Unit <lq057q3dc02_top>.
Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/design/lq057q3dc02_top.vhd".
Unit <lq057q3dc02_top> synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Counters : 4
17-bit up counter : 1
9-bit up counter : 3
# Registers : 4
1-bit register : 4
# Comparators : 11
10-bit comparator greatequal : 4
10-bit comparator less : 7
 
=========================================================================
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs> on signal <CLK_Cntr_cs[1:3]> with sequential encoding.
-------------------------------
State | Encoding
-------------------------------
inactive_wait_1 | 000
inactive_wait_2 | 010
inactive_wait_tvs | 001
inactive_wait_the | 011
active | 100
-------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <V_C/VSYNCx_C/Line_Cntr_cs> on signal <Line_Cntr_cs[1:2]> with gray encoding.
-------------------------
State | Encoding
-------------------------
frame_start | 00
add | 10
add_wait | 11
ready | 01
-------------------------
Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2.
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# FSMs : 2
# Counters : 4
17-bit up counter : 1
9-bit up counter : 3
# Registers : 9
Flip-Flops : 9
# Comparators : 11
10-bit comparator greatequal : 4
10-bit comparator less : 7
 
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
 
Optimizing unit <lq057q3dc02_top> ...
 
Optimizing unit <hsyncx_control> ...
 
Optimizing unit <vsyncx_control> ...
 
Optimizing unit <clk_lcd_cyc_cntr> ...
 
Optimizing unit <enab_control> ...
 
Optimizing unit <dcm_sys_to_lcd> ...
 
Optimizing unit <image_gen_bram> ...
 
Optimizing unit <video_controller> ...
 
Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <B<5>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<4>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<3>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<2>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<1>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<0>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<5>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<4>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<3>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<2>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<1>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<0>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<5>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<4>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<3>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<2>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<1>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<0>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
Building and optimizing final netlist ...
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers : 53
Flip-Flops : 53
 
=========================================================================
 
=========================================================================
* Partition Report *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
* Final Report *
=========================================================================
Final Results
Top Level Output File Name : lq057q3dc02_top_part
Output Format : ngc
Optimization Goal : SPEED
Keep Hierarchy : soft
 
Design Statistics
# IOs : 27
 
Cell Usage :
# BELS : 212
# GND : 6
# INV : 9
# LUT1 : 8
# LUT2 : 7
# LUT2_L : 4
# LUT3 : 26
# LUT3_D : 2
# LUT3_L : 1
# LUT4 : 55
# LUT4_L : 7
# MUXCY : 40
# MUXF5 : 2
# VCC : 2
# XORCY : 43
# FlipFlops/Latches : 53
# FDC : 24
# FDCE : 26
# FDP : 3
# Clock Buffers : 3
# BUFG : 3
# IO Buffers : 27
# IBUF : 1
# IBUFG : 1
# OBUF : 25
# DCMs : 1
# DCM : 1
# Others : 3
# image_gen_bram_blue : 1
# image_gen_bram_green : 1
# image_gen_bram_red : 1
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2vp30ff896-7
 
Number of Slices: 60 out of 13696 0%
Number of Slice Flip Flops: 53 out of 27392 0%
Number of 4 input LUTs: 119 out of 27392 0%
Number of IOs: 27
Number of bonded IOBs: 26 out of 556 4%
Number of GCLKs: 3 out of 16 18%
Number of DCMs: 1 out of 8 12%
 
---------------------------
Partition Resource Summary:
---------------------------
 
No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK_100M_PAD | DCM_INST:CLKDV | 53 |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------+----------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------+----------------------------------------------+-------+
V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv1_INV_0:O)| NONE(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_FFd3)| 12 |
V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv(V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv1_INV_0:O) | NONE(V_C/VSYNCx_C/line_num_reg_7) | 12 |
IMAGE/RSTx_inv(IMAGE/RSTx_inv1_INV_0:O) | NONE(IMAGE/ADDR_wire_15) | 18 |
V_C/HSYNCx_C/RSTx_inv(V_C/HSYNCx_C/RSTx_inv1_INV_0:O) | NONE(V_C/HSYNCx_C/num_hsyncx_clks_reg_2) | 10 |
V_C/ENAB_C/RSTx_inv(V_C/ENAB_C/RSTx_inv1_INV_0:O) | NONE(V_C/ENAB_C/ENAB) | 1 |
-----------------------------------------------------------------------------------------------+----------------------------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -7
 
Minimum period: 0.500ns (Maximum Frequency: 2000.475MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 3.390ns
Maximum combinational path delay: 2.924ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK_100M_PAD'
Clock period: 0.500ns (frequency: 2000.475MHz)
Total number of paths / destination ports: 2304 / 79
-------------------------------------------------------------------------
Delay: 3.999ns (Levels of Logic = 21)
Source: V_C/VSYNCx_C/line_num_reg_6 (FF)
Destination: IMAGE/ADDR_wire_16 (FF)
Source Clock: CLK_100M_PAD rising 0.1X
Destination Clock: CLK_100M_PAD rising 0.1X
 
Data Path: V_C/VSYNCx_C/line_num_reg_6 to IMAGE/ADDR_wire_16
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 8 0.370 0.614 line_num_reg_6 (LINE_NUM<6>)
end scope: 'VSYNCx_C'
end scope: 'V_C'
begin scope: 'IMAGE'
LUT4:I0->O 16 0.275 0.668 Mcount_ADDR_wire_lut<0>_SW0 (N146)
LUT4:I3->O 1 0.275 0.000 Mcount_ADDR_wire_lut<0> (N2)
MUXCY:S->O 1 0.334 0.000 Mcount_ADDR_wire_cy<0> (Mcount_ADDR_wire_cy<0>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<1> (Mcount_ADDR_wire_cy<1>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<2> (Mcount_ADDR_wire_cy<2>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<3> (Mcount_ADDR_wire_cy<3>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<4> (Mcount_ADDR_wire_cy<4>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<5> (Mcount_ADDR_wire_cy<5>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<6> (Mcount_ADDR_wire_cy<6>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<7> (Mcount_ADDR_wire_cy<7>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<8> (Mcount_ADDR_wire_cy<8>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<9> (Mcount_ADDR_wire_cy<9>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<10> (Mcount_ADDR_wire_cy<10>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<11> (Mcount_ADDR_wire_cy<11>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<12> (Mcount_ADDR_wire_cy<12>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<13> (Mcount_ADDR_wire_cy<13>)
MUXCY:CI->O 1 0.036 0.000 Mcount_ADDR_wire_cy<14> (Mcount_ADDR_wire_cy<14>)
MUXCY:CI->O 0 0.036 0.000 Mcount_ADDR_wire_cy<15> (Mcount_ADDR_wire_cy<15>)
XORCY:CI->O 1 0.708 0.000 Mcount_ADDR_wire_xor<16> (Mcount_ADDR_wire16)
FDCE:D 0.208 ADDR_wire_16
----------------------------------------
Total 3.999ns (2.717ns logic, 1.282ns route)
(68.0% logic, 32.0% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_100M_PAD'
Total number of paths / destination ports: 57 / 57
-------------------------------------------------------------------------
Offset: 3.390ns (Levels of Logic = 2)
Source: V_C/HSYNCx_C/HSYNCx (FF)
Destination: HSYNCx (PAD)
Source Clock: CLK_100M_PAD rising 0.1X
 
Data Path: V_C/HSYNCx_C/HSYNCx to HSYNCx
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDP:C->Q 5 0.370 0.428 HSYNCx (HSYNCx)
end scope: 'HSYNCx_C'
end scope: 'V_C'
OBUF:I->O 2.592 HSYNCx_OBUF (HSYNCx)
----------------------------------------
Total 3.390ns (2.962ns logic, 0.428ns route)
(87.4% logic, 12.6% route)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Delay: 2.924ns (Levels of Logic = 2)
Source: IMAGE/image_BLUE_data:DOUT<5> (PAD)
Destination: B<5> (PAD)
 
Data Path: IMAGE/image_BLUE_data:DOUT<5> to B<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
image_gen_bram_blue:DOUT<5> 1 0.000 0.000 image_BLUE_data (B<5>)
end scope: 'IMAGE'
OBUF:I->O 2.592 B_5_OBUF (B<5>)
----------------------------------------
Total 2.924ns (2.924ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
 
=========================================================================
CPU : 13.19 / 13.31 s | Elapsed : 13.00 / 14.00 s
-->
 
Total memory usage is 206148 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 21 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
/trunk/implement/results/lq057q3dc02_top.twr
0,0 → 1,84
--------------------------------------------------------------------------------
Release 9.2.04i Trace
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
 
trce -e 10 lq057q3dc02_top.ncd -o lq057q3dc02_top.twr lq057q3dc02_top.pcf
 
Design file: lq057q3dc02_top.ncd
Physical constraint file: lq057q3dc02_top.pcf
Device,package,speed: xc2vp30,ff896,-7 (PRODUCTION 1.94 2007-10-19)
Report level: error report, limited to 10 items per constraint
 
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
 
================================================================================
Timing constraint: NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%;
 
0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: PERIOD analysis for net "DCM_LCD_CLK/CLKDV_BUF" derived from
NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%; multiplied by
16.00 and duty cycle corrected to 160 nS HIGH 80 nS
 
3903 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 10.079ns.
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: NET "CLK_LCD" PERIOD = 160 ns HIGH 50%;
 
0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
All constraints were met.
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Clock to Setup on destination clock CLK_100M_PAD
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_100M_PAD | 10.079| | | |
---------------+---------+---------+---------+---------+
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0
 
Constraints cover 3903 paths, 0 nets, and 2359 connections
 
Design statistics:
Minimum period: 10.079ns (Maximum frequency: 99.216MHz)
 
 
Analysis completed Thu Nov 06 13:57:08 2008
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 148 MB
 
 
 
/trunk/implement/results/lq057q3dc02_top.map
0,0 → 1,112
Release 9.2.04i Map J.40
Xilinx Map Application Log File for Design 'lq057q3dc02_top'
 
Design Information
------------------
Command Line : map -ol high -timing -pr b lq057q3dc02_top.ngd -o
lq057q3dc02_top.ncd lq057q3dc02_top.pcf
Target Device : xc2vp30
Target Package : ff896
Target Speed : -7
Mapper Version : virtex2p -- $Revision: 1.1 $
Mapped Date : Thu Nov 06 13:56:04 2008
 
Mapping design into LUTs...
Writing file lq057q3dc02_top.ngm...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...
 
Phase 1.1
Phase 1.1 (Checksum:98abc4) REAL time: 2 secs
 
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 2 secs
 
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 2 secs
 
Phase 4.2
.
Phase 4.2 (Checksum:26259fc) REAL time: 2 secs
 
Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 2 secs
 
Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 3 secs
 
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs
 
Phase 8.4
.....................
Phase 8.4 (Checksum:4c4b3f8) REAL time: 7 secs
 
Phase 9.28
Phase 9.28 (Checksum:55d4a77) REAL time: 8 secs
 
Phase 10.8
.......................................
..
..........................................................
...............
...............
...............
Phase 10.8 (Checksum:f0addd) REAL time: 11 secs
 
Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 11 secs
 
Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 11 secs
 
Phase 13.18
Phase 13.18 (Checksum:7bfa473) REAL time: 13 secs
 
Phase 14.5
Phase 14.5 (Checksum:8583af2) REAL time: 13 secs
 
Phase 15.27
Phase 15.27 (Checksum:8f0d171) REAL time: 13 secs
 
Phase 16.24
Phase 16.24 (Checksum:98967f0) REAL time: 13 secs
 
REAL time consumed by placer: 14 secs
CPU time consumed by placer: 13 secs
Inspecting route info ...
Route info done.
 
Design Summary
--------------
 
Design Summary:
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 85 out of 27,392 1%
Number of 4 input LUTs: 385 out of 27,392 1%
Logic Distribution:
Number of occupied Slices: 250 out of 13,696 1%
Total Number of 4 input LUTs: 405 out of 27,392 1%
Number used as logic: 385
Number used as a route-thru: 20
 
Number of bonded IOBs: 27 out of 556 4%
IOB Flip Flops: 1
Number of PPC405s: 0 out of 2 0%
Number of Block RAMs: 87 out of 136 63%
Number of GCLKs: 2 out of 16 12%
Number of DCMs: 1 out of 8 12%
Number of GTs: 0 out of 8 0%
Number of GT10s: 0 out of 0 0%
 
Total equivalent gate count for design: 5,712,197
Additional JTAG gate count for IOBs: 1,296
Peak Memory Usage: 238 MB
Total REAL time to MAP completion: 23 secs
Total CPU time to MAP completion: 22 secs
 
Mapping completed.
See MAP report file "lq057q3dc02_top.mrp" for details.
/trunk/implement/results/lq057q3dc02_top.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/implement/results/lq057q3dc02_top.bit
trunk/implement/results/lq057q3dc02_top.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implement/results/lq057q3dc02_top.mrp =================================================================== --- trunk/implement/results/lq057q3dc02_top.mrp (nonexistent) +++ trunk/implement/results/lq057q3dc02_top.mrp (revision 32) @@ -0,0 +1,257 @@ +Release 9.2.04i Map J.40 +Xilinx Mapping Report File for Design 'lq057q3dc02_top' + +Design Information +------------------ +Command Line : map -ol high -timing -pr b lq057q3dc02_top.ngd -o +lq057q3dc02_top.ncd lq057q3dc02_top.pcf +Target Device : xc2vp30 +Target Package : ff896 +Target Speed : -7 +Mapper Version : virtex2p -- $Revision: 1.1 $ +Mapped Date : Thu Nov 06 13:56:04 2008 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 2 +Logic Utilization: + Number of Slice Flip Flops: 85 out of 27,392 1% + Number of 4 input LUTs: 385 out of 27,392 1% +Logic Distribution: + Number of occupied Slices: 250 out of 13,696 1% +Total Number of 4 input LUTs: 405 out of 27,392 1% + Number used as logic: 385 + Number used as a route-thru: 20 + + Number of bonded IOBs: 27 out of 556 4% + IOB Flip Flops: 1 + Number of PPC405s: 0 out of 2 0% + Number of Block RAMs: 87 out of 136 63% + Number of GCLKs: 2 out of 16 12% + Number of DCMs: 1 out of 8 12% + Number of GTs: 0 out of 8 0% + Number of GT10s: 0 out of 0 0% + +Total equivalent gate count for design: 5,712,197 +Additional JTAG gate count for IOBs: 1,296 +Peak Memory Usage: 238 MB +Total REAL time to MAP completion: 23 secs +Total CPU time to MAP completion: 22 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Modular Design Summary +Section 11 - Timing Report +Section 12 - Configuration String Information +Section 13 - Control Set Information + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT:243 - Logical network N1 has no load. +WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 8 + more times for the following (max. 5 shown): + N2, + DCM_LCD_CLK/CLKFX_OUT, + DCM_LCD_CLK/N0, + IMAGE/N196, + V_C/VSYNCx_C/N42 + To see the details of these warning messages, please use the -detail switch. + +Section 3 - Informational +------------------------- +INFO:MapLib:562 - No environment variables are currently set. +INFO:MapLib:863 - The following Virtex BUFG(s) is/are being retargeted to + Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: + BUFG symbol "DCM_LCD_CLK/CLK0_BUFG_INST" (output + signal=DCM_LCD_CLK/CLK0_OUT), + BUFG symbol "DCM_LCD_CLK/CLKDV_BUFG_INST" (output signal=CLK_LCD_OBUF), + BUFG symbol "DCM_LCD_CLK/CLKFX_BUFG_INST" (output + signal=DCM_LCD_CLK/CLKFX_OUT) +INFO:MapLib:159 - Net Timing constraints on signal CLK_100M_PAD are pushed + forward through input buffer. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs in the + schematic. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + -40.000 to 100.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 1.400 Volts. (default - Range: 1.400 to + 1.600 Volts) +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 9 block(s) removed + 14 block(s) optimized away + 10 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +The signal "N1" is loadless and has been removed. + Loadless block "XST_GND" (ZERO) removed. +The signal "N2" is loadless and has been removed. + Loadless block "XST_VCC" (ONE) removed. +The signal "DCM_LCD_CLK/CLKFX_OUT" is sourceless and has been removed. +The signal "DCM_LCD_CLK/CLKFX_BUF" is sourceless and has been removed. + Sourceless block "DCM_LCD_CLK/CLKFX_BUFG_INST" (CKBUF) removed. +The signal "DCM_LCD_CLK/N0" is sourceless and has been removed. +The signal "IMAGE/N196" is sourceless and has been removed. +The signal "V_C/VSYNCx_C/N42" is sourceless and has been removed. +The signal "V_C/CLK_LCD_CYCLE_Cntr/N119" is sourceless and has been removed. +The signal "V_C/ENAB_C/N65" is sourceless and has been removed. +The signal "V_C/ENAB_C/N66" is sourceless and has been removed. +Unused block "DCM_LCD_CLK/XST_VCC" (ONE) removed. +Unused block "IMAGE/XST_VCC" (ONE) removed. +Unused block "V_C/CLK_LCD_CYCLE_Cntr/XST_VCC" (ONE) removed. +Unused block "V_C/ENAB_C/XST_GND" (ZERO) removed. +Unused block "V_C/ENAB_C/XST_VCC" (ONE) removed. +Unused block "V_C/VSYNCx_C/XST_VCC" (ONE) removed. + +Optimized Block(s): +TYPE BLOCK +GND DCM_LCD_CLK/XST_GND +GND IMAGE/XST_GND +GND IMAGE/image_BLUE_data/GND +VCC IMAGE/image_BLUE_data/VCC +GND IMAGE/image_GREEN_data/GND +VCC IMAGE/image_GREEN_data/VCC +GND IMAGE/image_RED_data/GND +VCC IMAGE/image_RED_data/VCC +GND V_C/CLK_LCD_CYCLE_Cntr/XST_GND +GND V_C/HSYNCx_C/XST_GND +VCC V_C/HSYNCx_C/XST_VCC +GND V_C/VSYNCx_C/XST_GND +GND V_C/XST_GND +VCC V_C/XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Strength | Rate | | | Delay | ++------------------------------------------------------------------------------------------------------------------------+ +| B<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| B<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| B<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| B<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| B<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| B<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| CLK_100M_PAD | IOB | INPUT | LVCMOS25 | | | | | | +| CLK_LCD | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| ENAB | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | +| G<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| G<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| G<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| G<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| G<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| G<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| HSYNCx | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| R<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| R<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| R<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| R<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| R<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| R<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| RL | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| RSTx | IOB | INPUT | LVCMOS25 | | | | | | +| UD | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| VQ | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| VSYNCx | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | ++------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Modular Design Summary +----------------------------------- +Modular Design not used for this design. + +Section 11 - Timing Report +-------------------------- +INFO:Timing:3284 - This timing report was generated using estimated delay + information. For accurate numbers, please refer to the post Place and Route + timing report. +Number of Timing Constraints that were not applied: 2 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +------------------------------------------------------------------------------------------------------ + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +------------------------------------------------------------------------------------------------------ + PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP | 153.129ns| 6.871ns| 0| 0 + V_BUF" derived from NET "DCM_LCD_CLK/CLK | HOLD | 0.622ns| | 0| 0 + IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50% mu | | | | | + ltiplied by 16.00 and duty cycle correcte | | | | | + d to 160 nS HIGH 80 nS | | | | | +------------------------------------------------------------------------------------------------------ + NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD | N/A | N/A| N/A| N/A| N/A + = 10 ns HIGH 50% | | | | | +------------------------------------------------------------------------------------------------------ + NET "CLK_LCD" PERIOD = 160 ns HIGH 50% | N/A | N/A| N/A| N/A| N/A +------------------------------------------------------------------------------------------------------ + + +All constraints were met. +INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the + constraint does not cover any paths or that it has no requested value. + + + +Section 12 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 13 - Control Set Information +------------------------------------ +No control set information for this architecture. Index: trunk/implement/results/lq057q3dc02_top.nlf =================================================================== --- trunk/implement/results/lq057q3dc02_top.nlf (nonexistent) +++ trunk/implement/results/lq057q3dc02_top.nlf (revision 32) @@ -0,0 +1,17 @@ +Release 9.2.04i - netgen J.40 +Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. + +Command Line: netgen -ofmt vhdl -w lq057q3dc02_top.ngc + +Reading design 'lq057q3dc02_top.ngc' ... +Flattening design ... +Processing design ... + Preping design's networks ... + Preping design's macros ... +Writing VHDL netlist 'lq057q3dc02_top.vhd' ... +INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM + simulation primitives and has to be used with UNISIM library for correct + compilation and simulation. +Number of warnings: 0 +Number of info messages: 1 +Total memory usage is 56472 kilobytes Index: trunk/implement/results/lq057q3dc02_top.blc =================================================================== --- trunk/implement/results/lq057q3dc02_top.blc (nonexistent) +++ trunk/implement/results/lq057q3dc02_top.blc (revision 32) @@ -0,0 +1,46 @@ +Release 9.2.04i ngcbuild J.40 +Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. + +Command Line: ngcbuild -sd ..\..\netlists -uc board.ucf lq057q3dc02_top_part.ngc +lq057q3dc02_top.ngc + +Reading NGO file +"D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/implement/results/lq057 +q3dc02_top_part.ngc" ... +Launcher: The source netlist for "image_gen_bram_red.ngo" was not found; the +current NGO file will be used and no new NGO description will be compiled. This +probably means that the source netlist was moved or deleted. +Loading design module +"D:\MyDocuments\OpenCores\projects\lq057q3dc02\hdl\vhsic\netlists\image_gen_bram +_red.ngo"... +Launcher: The source netlist for "image_gen_bram_green.ngo" was not found; the +current NGO file will be used and no new NGO description will be compiled. This +probably means that the source netlist was moved or deleted. +Loading design module +"D:\MyDocuments\OpenCores\projects\lq057q3dc02\hdl\vhsic\netlists\image_gen_bram +_green.ngo"... +Launcher: The source netlist for "image_gen_bram_blue.ngo" was not found; the +current NGO file will be used and no new NGO description will be compiled. This +probably means that the source netlist was moved or deleted. +Loading design module +"D:\MyDocuments\OpenCores\projects\lq057q3dc02\hdl\vhsic\netlists\image_gen_bram +_blue.ngo"... + +Applying constraints in "board.ucf" to the design... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGCBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 71736 kilobytes + +Writing NGC file "lq057q3dc02_top.ngc" ... + +Writing NGCBUILD log file "lq057q3dc02_top.blc"... Index: trunk/implement/results/lq057q3dc02_top.bld =================================================================== --- trunk/implement/results/lq057q3dc02_top.bld (nonexistent) +++ trunk/implement/results/lq057q3dc02_top.bld (revision 32) @@ -0,0 +1,30 @@ +Release 9.2.04i ngdbuild J.40 +Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. + +Command Line: ngdbuild lq057q3dc02_top.ngc lq057q3dc02_top.ngd + +Reading NGO file +"D:/MyDocuments/OpenCores/projects/lq057q3dc02/hdl/vhsic/implement/results/lq057 +q3dc02_top.ngc" ... + +Checking timing specifications ... +Checking expanded design ... +WARNING:NgdBuild:478 - clock net DCM_LCD_CLK/CLKFX_OUT with clock driver + DCM_LCD_CLK/CLKFX_BUFG_INST drives no clock pins + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 1 + +Total memory usage is 69760 kilobytes + +Writing NGD file "lq057q3dc02_top.ngd" ... + +Writing NGDBUILD log file "lq057q3dc02_top.bld"... Index: trunk/implement/results/lq057q3dc02_top.par =================================================================== --- trunk/implement/results/lq057q3dc02_top.par (nonexistent) +++ trunk/implement/results/lq057q3dc02_top.par (revision 32) @@ -0,0 +1,151 @@ +Release 9.2.04i par J.40 +Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. + +NAUTILUS:: Thu Nov 06 13:56:37 2008 + +par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf + + +Constraints file: lq057q3dc02_top.pcf. +Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2. + "lq057q3dc02_top" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7 + +Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) +Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts) + + +Device speed data version: "PRODUCTION 1.94 2007-10-19". + + +INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance. + +Device Utilization Summary: + + Number of BUFGMUXs 2 out of 16 12% + Number of DCMs 1 out of 8 12% + Number of External IOBs 27 out of 556 4% + Number of LOCed IOBs 27 out of 27 100% + + Number of RAMB16s 87 out of 136 63% + Number of SLICEs 250 out of 13696 1% + + +Overall effort level (-ol): High +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 8 secs +Finished initial Timing Analysis. REAL time: 8 secs + +Starting Router + +Phase 1: 2989 unrouted; REAL time: 19 secs + +Phase 2: 2827 unrouted; REAL time: 19 secs + +Phase 3: 411 unrouted; REAL time: 21 secs + +Phase 4: 411 unrouted; (0) REAL time: 21 secs + +Phase 5: 411 unrouted; (0) REAL time: 21 secs + +Phase 6: 411 unrouted; (0) REAL time: 21 secs + +Phase 7: 0 unrouted; (0) REAL time: 22 secs + +Phase 8: 0 unrouted; (0) REAL time: 23 secs + +WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because + 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. + +Total REAL time to Router completion: 23 secs +Total CPU time to Router completion: 23 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| CLK_LCD_OBUF | BUFGMUX6P| No | 155 | 0.234 | 1.229 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + + + The Delay Summary Report + + +The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 + + The AVERAGE CONNECTION DELAY for this design is: 2.107 + The MAXIMUM PIN DELAY IS: 8.688 + The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 7.641 + + Listing Pin Delays by value: (nsec) + + d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 9.00 d >= 9.00 + --------- --------- --------- --------- --------- --------- + 1599 1024 311 73 8 0 + +Timing Score: 0 + +Number of Timing Constraints that were not applied: 2 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +------------------------------------------------------------------------------------------------------ + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +------------------------------------------------------------------------------------------------------ + PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP | 149.921ns| 10.079ns| 0| 0 + V_BUF" derived from NET "DCM_LCD_CLK/CLK | HOLD | 0.562ns| | 0| 0 + IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50% | | | | | +------------------------------------------------------------------------------------------------------ + NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD | N/A | N/A| N/A| N/A| N/A + = 10 ns HIGH 50% | | | | | +------------------------------------------------------------------------------------------------------ + NET "CLK_LCD" PERIOD = 160 ns HIGH 50% | N/A | N/A| N/A| N/A| N/A +------------------------------------------------------------------------------------------------------ + + +All constraints were met. +INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the + constraint does not cover any paths or that it has no requested value. + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 25 secs +Total CPU time to PAR completion: 25 secs + +Peak Memory Usage: 196 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 1 +Number of info messages: 1 + +Writing design to file lq057q3dc02_top.ncd + + + +PAR done! Index: trunk/implement/results/lq057q3dc02_top.bgn =================================================================== --- trunk/implement/results/lq057q3dc02_top.bgn (nonexistent) +++ trunk/implement/results/lq057q3dc02_top.bgn (revision 32) @@ -0,0 +1,142 @@ +Release 9.2.04i - Bitgen J.40 +Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. +Loading device for application Rf_Device from file '2vp30.nph' in environment +C:\Xilinx\ISE_9_2. + "lq057q3dc02_top" is an NCD, version 3.1, device xc2vp30, package ff896, +speed -7 +Opened constraints file lq057q3dc02_top.pcf. + +Thu Nov 06 13:57:11 2008 + +bitgen -g StartUpClk:JTAGCLK -g GTS_cycle:1 -g GWE_cycle:1 -g LCK_cycle:2 -g DONE_cycle:4 -w lq057q3dc02_top.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| CRC | Enable* | ++----------------------+----------------------+ +| DebugBitstream | No* | ++----------------------+----------------------+ +| ConfigRate | 4* | ++----------------------+----------------------+ +| StartupClk | JtagClk | ++----------------------+----------------------+ +| DCMShutdown | Disable* | ++----------------------+----------------------+ +| DisableBandgap | No* | ++----------------------+----------------------+ +| CclkPin | Pullup* | ++----------------------+----------------------+ +| DonePin | Pullup* | ++----------------------+----------------------+ +| HswapenPin | Pullup* | ++----------------------+----------------------+ +| M0Pin | Pullup* | ++----------------------+----------------------+ +| M1Pin | Pullup* | ++----------------------+----------------------+ +| M2Pin | Pullup* | ++----------------------+----------------------+ +| PowerdownPin | Pullup* | ++----------------------+----------------------+ +| ProgPin | Pullup* | ++----------------------+----------------------+ +| TckPin | Pullup* | ++----------------------+----------------------+ +| TdiPin | Pullup* | ++----------------------+----------------------+ +| TdoPin | Pullup* | ++----------------------+----------------------+ +| TmsPin | Pullup* | ++----------------------+----------------------+ +| UnusedPin | Pulldown* | ++----------------------+----------------------+ +| GWE_cycle | 1 | ++----------------------+----------------------+ +| GTS_cycle | 1 | ++----------------------+----------------------+ +| LCK_cycle | 2 | ++----------------------+----------------------+ +| Match_cycle | Auto* | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No* | ++----------------------+----------------------+ +| DonePipe | No* | ++----------------------+----------------------+ +| Security | None* | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF* | ++----------------------+----------------------+ +| ActivateGclk | No* | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| PartialMask0 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask1 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask2 | (Not Specified)* | ++----------------------+----------------------+ +| PartialGclk | (Not Specified)* | ++----------------------+----------------------+ +| PartialLeft | (Not Specified)* | ++----------------------+----------------------+ +| PartialRight | (Not Specified)* | ++----------------------+----------------------+ +| Encrypt | No* | ++----------------------+----------------------+ +| Key0 | pick* | ++----------------------+----------------------+ +| Key1 | pick* | ++----------------------+----------------------+ +| Key2 | pick* | ++----------------------+----------------------+ +| Key3 | pick* | ++----------------------+----------------------+ +| Key4 | pick* | ++----------------------+----------------------+ +| Key5 | pick* | ++----------------------+----------------------+ +| Keyseq0 | M* | ++----------------------+----------------------+ +| Keyseq1 | M* | ++----------------------+----------------------+ +| Keyseq2 | M* | ++----------------------+----------------------+ +| Keyseq3 | M* | ++----------------------+----------------------+ +| Keyseq4 | M* | ++----------------------+----------------------+ +| Keyseq5 | M* | ++----------------------+----------------------+ +| KeyFile | (Not Specified)* | ++----------------------+----------------------+ +| StartKey | 0* | ++----------------------+----------------------+ +| StartCBC | pick* | ++----------------------+----------------------+ +| FreezeDCI | No* | ++----------------------+----------------------+ +| DCIUpdateMode | AsRequired* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No* | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "lq057q3dc02_top.bit". +Bitstream generation is complete. Index: trunk/implement/results =================================================================== --- trunk/implement/results (nonexistent) +++ trunk/implement/results (revision 32)
trunk/implement/results Property changes : Added: svn:ignore ## -0,0 +1,20 ## +lq057q3dc02_top.pcf +lq057q3dc02_top.vhd +lq057q3dc02_top.xpi +cfs_to_clink_top_part_vhdl.prj +lq057q3dc02_top.drc +lq057q3dc02_top.lso +lq057q3dc02_top.pad +lq057q3dc02_top.ncd +lq057q3dc02_top.ngc +lq057q3dc02_top.ngd +lq057q3dc02_top.ngm +lq057q3dc02_top_summary.xml +lq057q3dc02_top_usage.xml +netlist.lst +lq057q3dc02_top_part_vhdl.prj +lq057q3dc02_top_pad.txt +lq057q3dc02_top_part.ngc +lq057q3dc02_top_pad.csv +lq057q3dc02_top.unroutes +xst

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