URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/neorv32/trunk/docs/NEORV32.pdf
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svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
|
package neorv32_application_image is |
|
type application_init_image_t is array (0 to 849) of std_ulogic_vector(31 downto 0); |
type application_init_image_t is array (0 to 865) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
19,844 → 19,860
00000008 => x"00000493", |
00000009 => x"00000713", |
00000010 => x"00000793", |
00000011 => x"00002537", |
00000012 => x"80050513", |
00000013 => x"30051073", |
00000014 => x"30401073", |
00000015 => x"80002117", |
00000016 => x"fc010113", |
00000017 => x"ffc17113", |
00000018 => x"00010413", |
00000019 => x"80000197", |
00000020 => x"7b418193", |
00000021 => x"00000597", |
00000022 => x"08058593", |
00000023 => x"30559073", |
00000024 => x"f8000593", |
00000025 => x"0005a023", |
00000026 => x"00458593", |
00000027 => x"feb01ce3", |
00000028 => x"80000597", |
00000029 => x"f9058593", |
00000030 => x"84018613", |
00000031 => x"00c5d863", |
00000032 => x"00058023", |
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"cb858593", |
00000037 => x"80000617", |
00000038 => x"f6c60613", |
00000039 => x"80000697", |
00000040 => x"f6468693", |
00000041 => x"00d65c63", |
00000042 => x"00058703", |
00000043 => x"00e60023", |
00000044 => x"00158593", |
00000045 => x"00160613", |
00000046 => x"fedff06f", |
00000047 => x"00000513", |
00000048 => x"00000593", |
00000049 => x"05c000ef", |
00000050 => x"30047073", |
00000051 => x"10500073", |
00000052 => x"0000006f", |
00000053 => x"ff810113", |
00000054 => x"00812023", |
00000055 => x"00912223", |
00000056 => x"34202473", |
00000057 => x"02044663", |
00000058 => x"34102473", |
00000059 => x"00041483", |
00000060 => x"0034f493", |
00000061 => x"00240413", |
00000062 => x"34141073", |
00000063 => x"00300413", |
00000064 => x"00941863", |
00000065 => x"34102473", |
00000066 => x"00240413", |
00000067 => x"34141073", |
00000068 => x"00012483", |
00000069 => x"00412403", |
00000070 => x"00810113", |
00000071 => x"30200073", |
00000072 => x"00005537", |
00000073 => x"ff010113", |
00000074 => x"00000613", |
00000075 => x"00000593", |
00000076 => x"b0050513", |
00000077 => x"00112623", |
00000078 => x"00812423", |
00000079 => x"514000ef", |
00000080 => x"7b8000ef", |
00000081 => x"02050c63", |
00000082 => x"3a4000ef", |
00000083 => x"00001537", |
00000084 => x"a4c50513", |
00000085 => x"598000ef", |
00000086 => x"00000513", |
00000087 => x"7ac000ef", |
00000088 => x"00000413", |
00000089 => x"0ff47513", |
00000090 => x"7a0000ef", |
00000091 => x"0c800513", |
00000092 => x"7a0000ef", |
00000093 => x"00140413", |
00000094 => x"fedff06f", |
00000095 => x"00001537", |
00000096 => x"a2850513", |
00000097 => x"568000ef", |
00000098 => x"00c12083", |
00000099 => x"00812403", |
00000100 => x"00000513", |
00000101 => x"01010113", |
00000102 => x"00008067", |
00000103 => x"00000000", |
00000104 => x"fc010113", |
00000105 => x"02112e23", |
00000106 => x"02512c23", |
00000107 => x"02612a23", |
00000108 => x"02712823", |
00000109 => x"02a12623", |
00000110 => x"02b12423", |
00000111 => x"02c12223", |
00000112 => x"02d12023", |
00000113 => x"00e12e23", |
00000114 => x"00f12c23", |
00000115 => x"01012a23", |
00000116 => x"01112823", |
00000117 => x"01c12623", |
00000118 => x"01d12423", |
00000119 => x"01e12223", |
00000120 => x"01f12023", |
00000121 => x"34102773", |
00000122 => x"342027f3", |
00000123 => x"0807c863", |
00000124 => x"00071683", |
00000125 => x"00300593", |
00000126 => x"0036f693", |
00000127 => x"00270613", |
00000128 => x"00b69463", |
00000129 => x"00470613", |
00000130 => x"34161073", |
00000131 => x"00b00713", |
00000132 => x"04f77a63", |
00000133 => x"34000793", |
00000134 => x"000780e7", |
00000135 => x"03c12083", |
00000136 => x"03812283", |
00000137 => x"03412303", |
00000138 => x"03012383", |
00000139 => x"02c12503", |
00000140 => x"02812583", |
00000141 => x"02412603", |
00000142 => x"02012683", |
00000143 => x"01c12703", |
00000144 => x"01812783", |
00000145 => x"01412803", |
00000146 => x"01012883", |
00000147 => x"00c12e03", |
00000148 => x"00812e83", |
00000149 => x"00412f03", |
00000150 => x"00012f83", |
00000151 => x"04010113", |
00000152 => x"30200073", |
00000153 => x"00001737", |
00000154 => x"00279793", |
00000155 => x"a6870713", |
00000156 => x"00e787b3", |
00000157 => x"0007a783", |
00000158 => x"00078067", |
00000159 => x"80000737", |
00000160 => x"ffd74713", |
00000161 => x"00e787b3", |
00000162 => x"01000713", |
00000163 => x"f8f764e3", |
00000164 => x"00001737", |
00000165 => x"00279793", |
00000166 => x"a9870713", |
00000167 => x"00e787b3", |
00000168 => x"0007a783", |
00000169 => x"00078067", |
00000170 => x"800007b7", |
00000171 => x"0007a783", |
00000172 => x"f69ff06f", |
00000173 => x"800007b7", |
00000174 => x"0047a783", |
00000175 => x"f5dff06f", |
00000176 => x"800007b7", |
00000177 => x"0087a783", |
00000178 => x"f51ff06f", |
00000179 => x"800007b7", |
00000180 => x"00c7a783", |
00000181 => x"f45ff06f", |
00000182 => x"8101a783", |
00000183 => x"f3dff06f", |
00000184 => x"8141a783", |
00000185 => x"f35ff06f", |
00000186 => x"8181a783", |
00000187 => x"f2dff06f", |
00000188 => x"81c1a783", |
00000189 => x"f25ff06f", |
00000190 => x"8201a783", |
00000191 => x"f1dff06f", |
00000192 => x"8241a783", |
00000193 => x"f15ff06f", |
00000194 => x"8281a783", |
00000195 => x"f0dff06f", |
00000196 => x"82c1a783", |
00000197 => x"f05ff06f", |
00000198 => x"8301a783", |
00000199 => x"efdff06f", |
00000200 => x"8341a783", |
00000201 => x"ef5ff06f", |
00000202 => x"8381a783", |
00000203 => x"eedff06f", |
00000204 => x"83c1a783", |
00000205 => x"ee5ff06f", |
00000206 => x"00000000", |
00000207 => x"00000000", |
00000208 => x"00001537", |
00000209 => x"ff010113", |
00000210 => x"adc50513", |
00000211 => x"00112623", |
00000212 => x"00812423", |
00000213 => x"3f0000ef", |
00000214 => x"34202473", |
00000215 => x"00b00793", |
00000216 => x"0487f263", |
00000217 => x"800007b7", |
00000218 => x"ffd7c793", |
00000219 => x"00f407b3", |
00000220 => x"01000713", |
00000221 => x"00f77c63", |
00000222 => x"00001537", |
00000223 => x"00040593", |
00000224 => x"c5050513", |
00000225 => x"3c0000ef", |
00000226 => x"0400006f", |
00000227 => x"00001737", |
00000228 => x"00279793", |
00000229 => x"c7c70713", |
00000230 => x"00e787b3", |
00000231 => x"0007a783", |
00000232 => x"00078067", |
00000233 => x"00001737", |
00000234 => x"00241793", |
00000235 => x"cc070713", |
00000236 => x"00e787b3", |
00000237 => x"0007a783", |
00000238 => x"00078067", |
00000239 => x"00001537", |
00000240 => x"ae450513", |
00000241 => x"380000ef", |
00000242 => x"341025f3", |
00000243 => x"00059783", |
00000244 => x"00044a63", |
00000245 => x"0037f793", |
00000246 => x"00300713", |
00000247 => x"0ce79c63", |
00000248 => x"ffc58593", |
00000249 => x"34302673", |
00000250 => x"00812403", |
00000251 => x"00c12083", |
00000252 => x"00001537", |
00000253 => x"c6050513", |
00000254 => x"01010113", |
00000255 => x"3480006f", |
00000256 => x"00001537", |
00000257 => x"b0450513", |
00000258 => x"fbdff06f", |
00000259 => x"00001537", |
00000260 => x"b2050513", |
00000261 => x"fb1ff06f", |
00000262 => x"00001537", |
00000263 => x"b3450513", |
00000264 => x"fa5ff06f", |
00000265 => x"00001537", |
00000266 => x"b4050513", |
00000267 => x"f99ff06f", |
00000011 => x"00000813", |
00000012 => x"00000893", |
00000013 => x"00000913", |
00000014 => x"00000993", |
00000015 => x"00000a13", |
00000016 => x"00000a93", |
00000017 => x"00000b13", |
00000018 => x"00000b93", |
00000019 => x"00000c13", |
00000020 => x"00000c93", |
00000021 => x"00000d13", |
00000022 => x"00000d93", |
00000023 => x"00000e13", |
00000024 => x"00000e93", |
00000025 => x"00000f13", |
00000026 => x"00000f93", |
00000027 => x"00002537", |
00000028 => x"80050513", |
00000029 => x"30051073", |
00000030 => x"30401073", |
00000031 => x"80002117", |
00000032 => x"f8010113", |
00000033 => x"ffc17113", |
00000034 => x"00010413", |
00000035 => x"80000197", |
00000036 => x"77418193", |
00000037 => x"00000597", |
00000038 => x"08058593", |
00000039 => x"30559073", |
00000040 => x"f8000593", |
00000041 => x"0005a023", |
00000042 => x"00458593", |
00000043 => x"feb01ce3", |
00000044 => x"80000597", |
00000045 => x"f5058593", |
00000046 => x"84018613", |
00000047 => x"00c5d863", |
00000048 => x"00058023", |
00000049 => x"00158593", |
00000050 => x"ff5ff06f", |
00000051 => x"00001597", |
00000052 => x"cb858593", |
00000053 => x"80000617", |
00000054 => x"f2c60613", |
00000055 => x"80000697", |
00000056 => x"f2468693", |
00000057 => x"00d65c63", |
00000058 => x"00058703", |
00000059 => x"00e60023", |
00000060 => x"00158593", |
00000061 => x"00160613", |
00000062 => x"fedff06f", |
00000063 => x"00000513", |
00000064 => x"00000593", |
00000065 => x"05c000ef", |
00000066 => x"30047073", |
00000067 => x"10500073", |
00000068 => x"0000006f", |
00000069 => x"ff810113", |
00000070 => x"00812023", |
00000071 => x"00912223", |
00000072 => x"34202473", |
00000073 => x"02044663", |
00000074 => x"34102473", |
00000075 => x"00041483", |
00000076 => x"0034f493", |
00000077 => x"00240413", |
00000078 => x"34141073", |
00000079 => x"00300413", |
00000080 => x"00941863", |
00000081 => x"34102473", |
00000082 => x"00240413", |
00000083 => x"34141073", |
00000084 => x"00012483", |
00000085 => x"00412403", |
00000086 => x"00810113", |
00000087 => x"30200073", |
00000088 => x"00005537", |
00000089 => x"ff010113", |
00000090 => x"00000613", |
00000091 => x"00000593", |
00000092 => x"b0050513", |
00000093 => x"00112623", |
00000094 => x"00812423", |
00000095 => x"514000ef", |
00000096 => x"7f8000ef", |
00000097 => x"02050c63", |
00000098 => x"3a4000ef", |
00000099 => x"00001537", |
00000100 => x"a8c50513", |
00000101 => x"598000ef", |
00000102 => x"00000513", |
00000103 => x"7ec000ef", |
00000104 => x"00000413", |
00000105 => x"0ff47513", |
00000106 => x"7e0000ef", |
00000107 => x"0c800513", |
00000108 => x"788000ef", |
00000109 => x"00140413", |
00000110 => x"fedff06f", |
00000111 => x"00001537", |
00000112 => x"a6850513", |
00000113 => x"568000ef", |
00000114 => x"00c12083", |
00000115 => x"00812403", |
00000116 => x"00000513", |
00000117 => x"01010113", |
00000118 => x"00008067", |
00000119 => x"00000000", |
00000120 => x"fc010113", |
00000121 => x"02112e23", |
00000122 => x"02512c23", |
00000123 => x"02612a23", |
00000124 => x"02712823", |
00000125 => x"02a12623", |
00000126 => x"02b12423", |
00000127 => x"02c12223", |
00000128 => x"02d12023", |
00000129 => x"00e12e23", |
00000130 => x"00f12c23", |
00000131 => x"01012a23", |
00000132 => x"01112823", |
00000133 => x"01c12623", |
00000134 => x"01d12423", |
00000135 => x"01e12223", |
00000136 => x"01f12023", |
00000137 => x"34102773", |
00000138 => x"342027f3", |
00000139 => x"0807c863", |
00000140 => x"00071683", |
00000141 => x"00300593", |
00000142 => x"0036f693", |
00000143 => x"00270613", |
00000144 => x"00b69463", |
00000145 => x"00470613", |
00000146 => x"34161073", |
00000147 => x"00b00713", |
00000148 => x"04f77a63", |
00000149 => x"38000793", |
00000150 => x"000780e7", |
00000151 => x"03c12083", |
00000152 => x"03812283", |
00000153 => x"03412303", |
00000154 => x"03012383", |
00000155 => x"02c12503", |
00000156 => x"02812583", |
00000157 => x"02412603", |
00000158 => x"02012683", |
00000159 => x"01c12703", |
00000160 => x"01812783", |
00000161 => x"01412803", |
00000162 => x"01012883", |
00000163 => x"00c12e03", |
00000164 => x"00812e83", |
00000165 => x"00412f03", |
00000166 => x"00012f83", |
00000167 => x"04010113", |
00000168 => x"30200073", |
00000169 => x"00001737", |
00000170 => x"00279793", |
00000171 => x"aa870713", |
00000172 => x"00e787b3", |
00000173 => x"0007a783", |
00000174 => x"00078067", |
00000175 => x"80000737", |
00000176 => x"ffd74713", |
00000177 => x"00e787b3", |
00000178 => x"01000713", |
00000179 => x"f8f764e3", |
00000180 => x"00001737", |
00000181 => x"00279793", |
00000182 => x"ad870713", |
00000183 => x"00e787b3", |
00000184 => x"0007a783", |
00000185 => x"00078067", |
00000186 => x"800007b7", |
00000187 => x"0007a783", |
00000188 => x"f69ff06f", |
00000189 => x"800007b7", |
00000190 => x"0047a783", |
00000191 => x"f5dff06f", |
00000192 => x"800007b7", |
00000193 => x"0087a783", |
00000194 => x"f51ff06f", |
00000195 => x"800007b7", |
00000196 => x"00c7a783", |
00000197 => x"f45ff06f", |
00000198 => x"8101a783", |
00000199 => x"f3dff06f", |
00000200 => x"8141a783", |
00000201 => x"f35ff06f", |
00000202 => x"8181a783", |
00000203 => x"f2dff06f", |
00000204 => x"81c1a783", |
00000205 => x"f25ff06f", |
00000206 => x"8201a783", |
00000207 => x"f1dff06f", |
00000208 => x"8241a783", |
00000209 => x"f15ff06f", |
00000210 => x"8281a783", |
00000211 => x"f0dff06f", |
00000212 => x"82c1a783", |
00000213 => x"f05ff06f", |
00000214 => x"8301a783", |
00000215 => x"efdff06f", |
00000216 => x"8341a783", |
00000217 => x"ef5ff06f", |
00000218 => x"8381a783", |
00000219 => x"eedff06f", |
00000220 => x"83c1a783", |
00000221 => x"ee5ff06f", |
00000222 => x"00000000", |
00000223 => x"00000000", |
00000224 => x"00001537", |
00000225 => x"ff010113", |
00000226 => x"b1c50513", |
00000227 => x"00112623", |
00000228 => x"00812423", |
00000229 => x"3f0000ef", |
00000230 => x"34202473", |
00000231 => x"00b00793", |
00000232 => x"0487f263", |
00000233 => x"800007b7", |
00000234 => x"ffd7c793", |
00000235 => x"00f407b3", |
00000236 => x"01000713", |
00000237 => x"00f77c63", |
00000238 => x"00001537", |
00000239 => x"00040593", |
00000240 => x"c9050513", |
00000241 => x"3c0000ef", |
00000242 => x"0400006f", |
00000243 => x"00001737", |
00000244 => x"00279793", |
00000245 => x"cbc70713", |
00000246 => x"00e787b3", |
00000247 => x"0007a783", |
00000248 => x"00078067", |
00000249 => x"00001737", |
00000250 => x"00241793", |
00000251 => x"d0070713", |
00000252 => x"00e787b3", |
00000253 => x"0007a783", |
00000254 => x"00078067", |
00000255 => x"00001537", |
00000256 => x"b2450513", |
00000257 => x"380000ef", |
00000258 => x"341025f3", |
00000259 => x"00059783", |
00000260 => x"00044a63", |
00000261 => x"0037f793", |
00000262 => x"00300713", |
00000263 => x"0ce79c63", |
00000264 => x"ffc58593", |
00000265 => x"34302673", |
00000266 => x"00812403", |
00000267 => x"00c12083", |
00000268 => x"00001537", |
00000269 => x"b5850513", |
00000270 => x"f8dff06f", |
00000271 => x"00001537", |
00000272 => x"b6c50513", |
00000273 => x"f81ff06f", |
00000274 => x"00001537", |
00000275 => x"b8850513", |
00000276 => x"f75ff06f", |
00000277 => x"00001537", |
00000278 => x"b9c50513", |
00000279 => x"f69ff06f", |
00000280 => x"00001537", |
00000281 => x"bb050513", |
00000282 => x"f5dff06f", |
00000283 => x"00001537", |
00000284 => x"bcc50513", |
00000285 => x"f51ff06f", |
00000286 => x"00001537", |
00000287 => x"be450513", |
00000288 => x"f45ff06f", |
00000289 => x"00001537", |
00000290 => x"c0050513", |
00000291 => x"f39ff06f", |
00000292 => x"00001537", |
00000293 => x"c1450513", |
00000294 => x"f2dff06f", |
00000295 => x"00001537", |
00000296 => x"c2850513", |
00000297 => x"f21ff06f", |
00000298 => x"00001537", |
00000299 => x"c3c50513", |
00000300 => x"f15ff06f", |
00000301 => x"ffe58593", |
00000302 => x"f2dff06f", |
00000303 => x"00f00793", |
00000304 => x"02a7e263", |
00000305 => x"800007b7", |
00000306 => x"00078793", |
00000307 => x"00251513", |
00000308 => x"00a78533", |
00000309 => x"34000793", |
00000310 => x"00f52023", |
00000311 => x"00000513", |
00000312 => x"00008067", |
00000313 => x"00100513", |
00000314 => x"00008067", |
00000315 => x"ff010113", |
00000316 => x"00112623", |
00000317 => x"00812423", |
00000318 => x"00912223", |
00000319 => x"301027f3", |
00000320 => x"00079863", |
00000321 => x"00001537", |
00000322 => x"cf050513", |
00000323 => x"238000ef", |
00000324 => x"1a000793", |
00000325 => x"30579073", |
00000326 => x"00000413", |
00000327 => x"01000493", |
00000328 => x"00040513", |
00000329 => x"00140413", |
00000330 => x"0ff47413", |
00000331 => x"f91ff0ef", |
00000332 => x"fe9418e3", |
00000333 => x"00c12083", |
00000334 => x"00812403", |
00000335 => x"00412483", |
00000336 => x"01010113", |
00000337 => x"00008067", |
00000338 => x"fd010113", |
00000339 => x"02812423", |
00000340 => x"02912223", |
00000341 => x"03212023", |
00000342 => x"01312e23", |
00000343 => x"01412c23", |
00000344 => x"02112623", |
00000345 => x"01512a23", |
00000346 => x"00001a37", |
00000347 => x"00050493", |
00000348 => x"00058413", |
00000349 => x"00058523", |
00000350 => x"00000993", |
00000351 => x"00410913", |
00000352 => x"d24a0a13", |
00000353 => x"00a00593", |
00000354 => x"00048513", |
00000355 => x"438000ef", |
00000356 => x"00aa0533", |
00000357 => x"00054783", |
00000358 => x"01390ab3", |
00000359 => x"00048513", |
00000360 => x"00fa8023", |
00000361 => x"00a00593", |
00000362 => x"3d4000ef", |
00000363 => x"00198993", |
00000364 => x"00a00793", |
00000365 => x"00050493", |
00000366 => x"fcf996e3", |
00000367 => x"00090693", |
00000368 => x"00900713", |
00000369 => x"03000613", |
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00000744 => x"6d6e6f72", |
00000745 => x"20746e65", |
00000746 => x"6c6c6163", |
00000747 => x"00000000", |
00000748 => x"6863614d", |
00000749 => x"20656e69", |
00000750 => x"74666f73", |
00000751 => x"65726177", |
00000752 => x"746e6920", |
00000753 => x"75727265", |
00000754 => x"00007470", |
00000755 => x"6863614d", |
00000756 => x"20656e69", |
00000757 => x"656d6974", |
00000758 => x"6e692072", |
00000759 => x"72726574", |
00000760 => x"00747075", |
00000761 => x"6863614d", |
00000762 => x"20656e69", |
00000763 => x"65747865", |
00000764 => x"6c616e72", |
00000765 => x"746e6920", |
00000766 => x"75727265", |
00000767 => x"00007470", |
00000768 => x"74736146", |
00000769 => x"746e6920", |
00000770 => x"75727265", |
00000771 => x"30207470", |
00000772 => x"00000000", |
00000773 => x"74736146", |
00000774 => x"746e6920", |
00000775 => x"75727265", |
00000776 => x"31207470", |
00000777 => x"00000000", |
00000778 => x"74736146", |
00000779 => x"746e6920", |
00000780 => x"75727265", |
00000781 => x"32207470", |
00000782 => x"00000000", |
00000783 => x"74736146", |
00000784 => x"746e6920", |
00000785 => x"75727265", |
00000786 => x"33207470", |
00000787 => x"00000000", |
00000788 => x"6e6b6e55", |
00000789 => x"206e776f", |
00000790 => x"25783028", |
00000791 => x"00002978", |
00000792 => x"30204020", |
00000793 => x"2c782578", |
00000794 => x"56544d20", |
00000795 => x"303d4c41", |
00000796 => x"20782578", |
00000797 => x"54522f3c", |
00000798 => x"00003e45", |
00000799 => x"00000460", |
00000800 => x"00000378", |
00000801 => x"00000378", |
00000802 => x"00000378", |
00000803 => x"0000046c", |
00000804 => x"00000378", |
00000805 => x"00000378", |
00000806 => x"00000378", |
00000807 => x"00000478", |
00000808 => x"00000378", |
00000809 => x"00000378", |
00000810 => x"00000378", |
00000811 => x"00000378", |
00000812 => x"00000484", |
00000813 => x"00000490", |
00000814 => x"0000049c", |
00000815 => x"000004a8", |
00000816 => x"000003bc", |
00000817 => x"00000400", |
00000818 => x"0000040c", |
00000819 => x"00000418", |
00000820 => x"00000424", |
00000821 => x"00000430", |
00000822 => x"0000043c", |
00000823 => x"00000448", |
00000824 => x"00000378", |
00000825 => x"00000378", |
00000826 => x"00000378", |
00000827 => x"00000454", |
00000828 => x"4554523c", |
00000829 => x"4157203e", |
00000830 => x"4e494e52", |
00000831 => x"43202147", |
00000832 => x"43205550", |
00000833 => x"73205253", |
00000834 => x"65747379", |
00000835 => x"6f6e206d", |
00000836 => x"76612074", |
00000837 => x"616c6961", |
00000838 => x"21656c62", |
00000839 => x"522f3c20", |
00000840 => x"003e4554", |
00000841 => x"33323130", |
00000842 => x"37363534", |
00000843 => x"00003938", |
00000844 => x"33323130", |
00000845 => x"37363534", |
00000846 => x"62613938", |
00000847 => x"66656463", |
00000848 => x"00000000", |
00000540 => x"02000613", |
00000541 => x"00000713", |
00000542 => x"00e5d7b3", |
00000543 => x"00f7f793", |
00000544 => x"00f487b3", |
00000545 => x"0007c783", |
00000546 => x"00470713", |
00000547 => x"fff68693", |
00000548 => x"00f68423", |
00000549 => x"fec712e3", |
00000550 => x"00010623", |
00000551 => x"0140006f", |
00000552 => x"00012783", |
00000553 => x"0007a503", |
00000554 => x"00478713", |
00000555 => x"00e12023", |
00000556 => x"e7dff0ef", |
00000557 => x"00098413", |
00000558 => x"f3dff06f", |
00000559 => x"00012783", |
00000560 => x"0007c503", |
00000561 => x"00478713", |
00000562 => x"00e12023", |
00000563 => x"e51ff0ef", |
00000564 => x"fe5ff06f", |
00000565 => x"00012783", |
00000566 => x"0007a403", |
00000567 => x"00478713", |
00000568 => x"00e12023", |
00000569 => x"00045863", |
00000570 => x"02d00513", |
00000571 => x"40800433", |
00000572 => x"e2dff0ef", |
00000573 => x"00410593", |
00000574 => x"00040513", |
00000575 => x"c8dff0ef", |
00000576 => x"00410513", |
00000577 => x"fadff06f", |
00000578 => x"00012783", |
00000579 => x"00410593", |
00000580 => x"00478713", |
00000581 => x"0007a503", |
00000582 => x"00e12023", |
00000583 => x"fe1ff06f", |
00000584 => x"015c1663", |
00000585 => x"00d00513", |
00000586 => x"df5ff0ef", |
00000587 => x"00140993", |
00000588 => x"000c0513", |
00000589 => x"f99ff06f", |
00000590 => x"00050593", |
00000591 => x"fe002503", |
00000592 => x"ff010113", |
00000593 => x"00112623", |
00000594 => x"00f55513", |
00000595 => x"044000ef", |
00000596 => x"00051863", |
00000597 => x"00c12083", |
00000598 => x"01010113", |
00000599 => x"00008067", |
00000600 => x"00000013", |
00000601 => x"00000013", |
00000602 => x"00000013", |
00000603 => x"00000013", |
00000604 => x"fff50513", |
00000605 => x"fddff06f", |
00000606 => x"fe802503", |
00000607 => x"01055513", |
00000608 => x"00157513", |
00000609 => x"00008067", |
00000610 => x"f8a02223", |
00000611 => x"00008067", |
00000612 => x"00050613", |
00000613 => x"00000513", |
00000614 => x"0015f693", |
00000615 => x"00068463", |
00000616 => x"00c50533", |
00000617 => x"0015d593", |
00000618 => x"00161613", |
00000619 => x"fe0596e3", |
00000620 => x"00008067", |
00000621 => x"06054063", |
00000622 => x"0605c663", |
00000623 => x"00058613", |
00000624 => x"00050593", |
00000625 => x"fff00513", |
00000626 => x"02060c63", |
00000627 => x"00100693", |
00000628 => x"00b67a63", |
00000629 => x"00c05863", |
00000630 => x"00161613", |
00000631 => x"00169693", |
00000632 => x"feb66ae3", |
00000633 => x"00000513", |
00000634 => x"00c5e663", |
00000635 => x"40c585b3", |
00000636 => x"00d56533", |
00000637 => x"0016d693", |
00000638 => x"00165613", |
00000639 => x"fe0696e3", |
00000640 => x"00008067", |
00000641 => x"00008293", |
00000642 => x"fb5ff0ef", |
00000643 => x"00058513", |
00000644 => x"00028067", |
00000645 => x"40a00533", |
00000646 => x"00b04863", |
00000647 => x"40b005b3", |
00000648 => x"f9dff06f", |
00000649 => x"40b005b3", |
00000650 => x"00008293", |
00000651 => x"f91ff0ef", |
00000652 => x"40a00533", |
00000653 => x"00028067", |
00000654 => x"00008293", |
00000655 => x"0005ca63", |
00000656 => x"00054c63", |
00000657 => x"f79ff0ef", |
00000658 => x"00058513", |
00000659 => x"00028067", |
00000660 => x"40b005b3", |
00000661 => x"fe0558e3", |
00000662 => x"40a00533", |
00000663 => x"f61ff0ef", |
00000664 => x"40b00533", |
00000665 => x"00028067", |
00000666 => x"6f727245", |
00000667 => x"4e202172", |
00000668 => x"5047206f", |
00000669 => x"75204f49", |
00000670 => x"2074696e", |
00000671 => x"746e7973", |
00000672 => x"69736568", |
00000673 => x"2164657a", |
00000674 => x"0000000a", |
00000675 => x"6e696c42", |
00000676 => x"676e696b", |
00000677 => x"44454c20", |
00000678 => x"6d656420", |
00000679 => x"7270206f", |
00000680 => x"6172676f", |
00000681 => x"00000a6d", |
00000682 => x"000002e8", |
00000683 => x"000002f4", |
00000684 => x"00000300", |
00000685 => x"0000030c", |
00000686 => x"00000318", |
00000687 => x"00000320", |
00000688 => x"00000328", |
00000689 => x"00000330", |
00000690 => x"00000254", |
00000691 => x"00000254", |
00000692 => x"00000254", |
00000693 => x"00000338", |
00000694 => x"00000340", |
00000695 => x"00000254", |
00000696 => x"00000254", |
00000697 => x"00000254", |
00000698 => x"00000348", |
00000699 => x"00000254", |
00000700 => x"00000254", |
00000701 => x"00000254", |
00000702 => x"00000350", |
00000703 => x"00000254", |
00000704 => x"00000254", |
00000705 => x"00000254", |
00000706 => x"00000254", |
00000707 => x"00000358", |
00000708 => x"00000360", |
00000709 => x"00000368", |
00000710 => x"00000370", |
00000711 => x"4554523c", |
00000712 => x"0000203e", |
00000713 => x"74736e49", |
00000714 => x"74637572", |
00000715 => x"206e6f69", |
00000716 => x"72646461", |
00000717 => x"20737365", |
00000718 => x"6173696d", |
00000719 => x"6e67696c", |
00000720 => x"00006465", |
00000721 => x"74736e49", |
00000722 => x"74637572", |
00000723 => x"206e6f69", |
00000724 => x"65636361", |
00000725 => x"66207373", |
00000726 => x"746c7561", |
00000727 => x"00000000", |
00000728 => x"656c6c49", |
00000729 => x"206c6167", |
00000730 => x"74736e69", |
00000731 => x"74637572", |
00000732 => x"006e6f69", |
00000733 => x"61657242", |
00000734 => x"696f706b", |
00000735 => x"0000746e", |
00000736 => x"64616f4c", |
00000737 => x"64646120", |
00000738 => x"73736572", |
00000739 => x"73696d20", |
00000740 => x"67696c61", |
00000741 => x"0064656e", |
00000742 => x"64616f4c", |
00000743 => x"63636120", |
00000744 => x"20737365", |
00000745 => x"6c756166", |
00000746 => x"00000074", |
00000747 => x"726f7453", |
00000748 => x"64612065", |
00000749 => x"73657264", |
00000750 => x"696d2073", |
00000751 => x"696c6173", |
00000752 => x"64656e67", |
00000753 => x"00000000", |
00000754 => x"726f7453", |
00000755 => x"63612065", |
00000756 => x"73736563", |
00000757 => x"75616620", |
00000758 => x"0000746c", |
00000759 => x"69766e45", |
00000760 => x"6d6e6f72", |
00000761 => x"20746e65", |
00000762 => x"6c6c6163", |
00000763 => x"00000000", |
00000764 => x"6863614d", |
00000765 => x"20656e69", |
00000766 => x"74666f73", |
00000767 => x"65726177", |
00000768 => x"746e6920", |
00000769 => x"75727265", |
00000770 => x"00007470", |
00000771 => x"6863614d", |
00000772 => x"20656e69", |
00000773 => x"656d6974", |
00000774 => x"6e692072", |
00000775 => x"72726574", |
00000776 => x"00747075", |
00000777 => x"6863614d", |
00000778 => x"20656e69", |
00000779 => x"65747865", |
00000780 => x"6c616e72", |
00000781 => x"746e6920", |
00000782 => x"75727265", |
00000783 => x"00007470", |
00000784 => x"74736146", |
00000785 => x"746e6920", |
00000786 => x"75727265", |
00000787 => x"30207470", |
00000788 => x"00000000", |
00000789 => x"74736146", |
00000790 => x"746e6920", |
00000791 => x"75727265", |
00000792 => x"31207470", |
00000793 => x"00000000", |
00000794 => x"74736146", |
00000795 => x"746e6920", |
00000796 => x"75727265", |
00000797 => x"32207470", |
00000798 => x"00000000", |
00000799 => x"74736146", |
00000800 => x"746e6920", |
00000801 => x"75727265", |
00000802 => x"33207470", |
00000803 => x"00000000", |
00000804 => x"6e6b6e55", |
00000805 => x"206e776f", |
00000806 => x"25783028", |
00000807 => x"00002978", |
00000808 => x"30204020", |
00000809 => x"2c782578", |
00000810 => x"56544d20", |
00000811 => x"303d4c41", |
00000812 => x"20782578", |
00000813 => x"54522f3c", |
00000814 => x"00003e45", |
00000815 => x"000004a0", |
00000816 => x"000003b8", |
00000817 => x"000003b8", |
00000818 => x"000003b8", |
00000819 => x"000004ac", |
00000820 => x"000003b8", |
00000821 => x"000003b8", |
00000822 => x"000003b8", |
00000823 => x"000004b8", |
00000824 => x"000003b8", |
00000825 => x"000003b8", |
00000826 => x"000003b8", |
00000827 => x"000003b8", |
00000828 => x"000004c4", |
00000829 => x"000004d0", |
00000830 => x"000004dc", |
00000831 => x"000004e8", |
00000832 => x"000003fc", |
00000833 => x"00000440", |
00000834 => x"0000044c", |
00000835 => x"00000458", |
00000836 => x"00000464", |
00000837 => x"00000470", |
00000838 => x"0000047c", |
00000839 => x"00000488", |
00000840 => x"000003b8", |
00000841 => x"000003b8", |
00000842 => x"000003b8", |
00000843 => x"00000494", |
00000844 => x"4554523c", |
00000845 => x"4157203e", |
00000846 => x"4e494e52", |
00000847 => x"43202147", |
00000848 => x"43205550", |
00000849 => x"73205253", |
00000850 => x"65747379", |
00000851 => x"6f6e206d", |
00000852 => x"76612074", |
00000853 => x"616c6961", |
00000854 => x"21656c62", |
00000855 => x"522f3c20", |
00000856 => x"003e4554", |
00000857 => x"33323130", |
00000858 => x"37363534", |
00000859 => x"00003938", |
00000860 => x"33323130", |
00000861 => x"37363534", |
00000862 => x"62613938", |
00000863 => x"66656463", |
00000864 => x"00000000", |
others => x"00000000" |
); |
|
/neorv32/trunk/rtl/core/neorv32_cpu_control.vhd
117,7 → 117,7
end record; |
signal fetch_engine : fetch_engine_t; |
|
-- instrucion prefetch buffer (IPB) -- |
-- instrucion prefetch buffer (IPB, real FIFO) -- |
type ipb_data_fifo_t is array (0 to ipb_entries_c-1) of std_ulogic_vector(2+31 downto 0); |
type ipb_t is record |
wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data |
155,7 → 155,7
end record; |
signal issue_engine : issue_engine_t; |
|
-- instruction buffer -- |
-- instruction buffer ("FIFO" with just one entry) -- |
type i_buf_t is record |
wdata : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction |
rdata : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction |
1837,16 → 1837,16
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID |
csr.rdata <= (others => '0'); |
when csr_marchid_c => -- R/-: marchid - architecture ID |
csr.rdata <= (others => '0'); |
when csr_mimpid_c => -- R/-: mimpid - implementation ID / NEORV32 hardware version |
csr.rdata <= hw_version_c; |
csr.rdata(4 downto 0) <= "10011"; -- official open-source arch ID |
when csr_mimpid_c => -- R/-: mimpid - implementation ID |
csr.rdata <= hw_version_c; -- NEORV32 hardware version |
when csr_mhartid_c => -- R/-: mhartid - hardware thread ID |
csr.rdata <= HW_THREAD_ID; |
|
-- custom machine read-only CSRs -- |
when csr_mzext_c => -- R/-: mzext |
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr CPU extension |
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei CPU extension |
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension |
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension |
|
-- undefined/unavailable -- |
when others => |
/neorv32/trunk/rtl/core/neorv32_package.vhd
41,8 → 41,9
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040408"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040500"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
-- Architecture Configuration ------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
51,7 → 52,7
constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and triggers an access exception |
constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode (better timing) |
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2 |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW |
|
-- Helper Functions ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
64,6 → 65,7
function xor_all_f(a : std_ulogic_vector) return std_ulogic; |
function xnor_all_f(a : std_ulogic_vector) return std_ulogic; |
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character; |
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector; |
|
-- Internal Types ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
1286,4 → 1288,15
return output_v; |
end function to_hexchar_f; |
|
-- Function: Bit reversal ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is |
variable output_v : std_ulogic_vector(input'range); |
begin |
for i in 0 to input'length-1 loop |
output_v(input'length-i-1) := input(i); |
end loop; -- i |
return output_v; |
end function bit_rev_f; |
|
end neorv32_package; |
/neorv32/trunk/rtl/core/neorv32_top.vhd
237,6 → 237,8
-- memory layout notifier -- |
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning; |
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning; |
-- memory latency notifier -- |
assert not (MEM_EXT_USE = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning; |
|
|
-- Reset Generator ------------------------------------------------------------------------ |
/neorv32/trunk/sw/bootloader/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/common/crt0.S
47,29 → 47,54
.cfi_undefined ra |
|
// ********************************************************* |
// Clear register file |
// Assume 'worst case': rv32e |
// Clear register file (lower half, assume E extension) |
// ********************************************************* |
__crt0_reg_file_clear: |
//addi x0, x0, 0 // hardwired to zero |
addi x1, x0, 0 |
addi x2, x0, 0 |
addi x3, x0, 0 |
addi x4, x0, 0 |
addi x5, x0, 0 |
addi x6, x0, 0 |
addi x7, x0, 0 |
addi x8, x0, 0 |
addi x9, x0, 0 |
//addi x10, x0, 0 |
//addi x11, x0, 0 |
//addi x12, x0, 0 |
//addi x13, x0, 0 |
addi x14, x0, 0 |
addi x15, x0, 0 |
//addi x0, x0, 0 // hardwired to zero |
addi x1, x0, 0 |
addi x2, x0, 0 |
addi x3, x0, 0 |
addi x4, x0, 0 |
addi x5, x0, 0 |
addi x6, x0, 0 |
addi x7, x0, 0 |
addi x8, x0, 0 |
addi x9, x0, 0 |
//addi x10, x0, 0 |
//addi x11, x0, 0 |
//addi x12, x0, 0 |
//addi x13, x0, 0 |
addi x14, x0, 0 |
addi x15, x0, 0 |
|
|
// ********************************************************* |
// Clear register file (upper half, if no E extension) |
// ********************************************************* |
#ifndef __riscv_32e |
// save some program space if compiling bootloader |
#ifndef make_bootloader |
addi x16, x0, 0 |
addi x17, x0, 0 |
addi x18, x0, 0 |
addi x19, x0, 0 |
addi x20, x0, 0 |
addi x21, x0, 0 |
addi x22, x0, 0 |
addi x23, x0, 0 |
addi x24, x0, 0 |
addi x25, x0, 0 |
addi x26, x0, 0 |
addi x27, x0, 0 |
addi x28, x0, 0 |
addi x29, x0, 0 |
addi x30, x0, 0 |
addi x31, x0, 0 |
#endif |
#endif |
|
|
// ********************************************************* |
// No interrupts, thanks |
// ********************************************************* |
__crt0_status_init: |
/neorv32/trunk/sw/example/blink_led/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/coremark/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/cpu_test/main.c
97,8 → 97,6
* This program uses mostly synthetic case to trigger all implemented exceptions. |
* Each exception is captured and evaluated for correct detection. |
* |
* @note This program requires the UART, MTIME and CLIC to be synthesized. |
* |
* @return Irrelevant. |
**************************************************************************/ |
int main() { |
/neorv32/trunk/sw/example/cpu_test/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/demo_freeRTOS/makefile
66,37 → 66,6
|
|
# ----------------------------------------------------------------------------- |
# FreeRTOS |
# ----------------------------------------------------------------------------- |
ifneq (,$(findstring RUN_FREERTOS_DEMO,$(USER_FLAGS))) |
# FreeRTOS home folder (adapt this!) |
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOS/FreeRTOS |
|
# Application |
APP_SRC += blinky_demo/main_blinky.c |
|
# FreeRTOS core |
APP_SRC += $(wildcard $(FREERTOS_HOME)/Source/*.c) |
APP_SRC += $(wildcard $(FREERTOS_HOME)/Source/portable/MemMang/heap_1.c) |
|
APP_INC += -I $(FREERTOS_HOME)/Source/include |
|
# FreeRTOS RISC-V specific |
APP_SRC += $(wildcard $(FREERTOS_HOME)/Source/portable/GCC/RISC-V/*.c) |
APP_SRC += $(FREERTOS_HOME)/Source/portable/GCC/RISC-V/portASM.S |
|
APP_INC += -I $(FREERTOS_HOME)/Source/portable/GCC/RISC-V |
|
# NEORV32 specific |
ASM_INC += -DportasmHANDLE_INTERRUPT=SystemIrqHandler |
|
APP_INC += -I chip_specific_extensions/neorv32 |
|
ASM_INC += -I chip_specific_extensions/neorv32 |
endif |
|
|
# ----------------------------------------------------------------------------- |
# NEORV32 framework |
# ----------------------------------------------------------------------------- |
# Path to NEORV32 linker script and startup file |
156,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
173,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/demo_pwm/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/demo_trng/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/demo_twi/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/demo_wdt/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/example/game_of_life/makefile
125,6 → 125,8
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
142,7 → 144,8
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
/neorv32/trunk/sw/lib/include/neorv32.h
193,6 → 193,12
|
|
/**********************************************************************//** |
* Official NEORV32 open-source architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) |
**************************************************************************/ |
#define NEORV32_ARCHID 19 |
|
|
/**********************************************************************//** |
* @name Helper macros for easy memory-mapped register access |
**************************************************************************/ |
/**@{*/ |
/neorv32/trunk/sw/lib/source/neorv32_rte.c
227,6 → 227,7
register uint32_t trap_inst; |
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr)); |
|
// modify return address only if exception (NOT for interrupts) |
if ((trap_cause & 0x80000000) == 0) { // is exception? |
if ((trap_inst & 3) == 3) { // is uncompressed instruction? |
trap_addr -= 4; |
248,7 → 249,7
int i; |
char c; |
|
neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n"); |
neorv32_uart_printf("\n\n<< Hardware Configuration Overview >>\n"); |
|
// CPU configuration |
neorv32_uart_printf("\n-- Central Processing Unit --\n"); |
260,6 → 261,9
|
tmp = neorv32_cpu_csr_read(CSR_MARCHID); |
neorv32_uart_printf("Architecture ID: 0x%x", tmp); |
if (tmp == NEORV32_ARCHID) { |
neorv32_uart_printf(" (NEORV32)"); |
} |
|
// HW version |
neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID)); |
/neorv32/trunk/CHANGELOG.md
14,6 → 14,8
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 13.10.2020 | [**:rocket:1.4.5.0**](https://github.com/stnolting/neorv32/releases/tag/v1.4.5.0) | An official *open-soucre RISC-V architecture ID* was assigned to the project: decimal = `19`, 32-bit hexadecimal = `0x00000013` - software can retrieve the ID from the `marchid` CSR | |
| 12.10.2020 | 1.4.4.9 | Added *alignment flags* to makefiles: branch targets are forced to be 32-bit aligned -> increases performance when using the `C` extension; added makefile flag listing to NEORV32.pdf; updated performance results for CPUs with `C` extension; `crt0.S` will initialize *all* registers with zero if not using `E` extension and not compiling bootloader | |
| 11.10.2020 | 1.4.4.8 | Reworked pipeline frontend: Optimized fetch enginge, added issue engine, faster instruction fetch after taken branches + reduced hardware requirements; updated synthesis and performance results | |
| 11.10.2020 | 1.4.4.6 | Added option to configure external memory interface (Wishbone) to either use *standard/classic protocol* (default) or *pipelined protocol* (for better timing): via `wb_pipe_mode_c` constant in VHDL package file (`rtl/core/neorv32_package.vhd`); added help text to NEORV32.pdf section "3.4.4. Processor-External Memory Interface (WISHBONE)" | |
| 08.10.2020 | 1.4.4.5 | Removed CPU’s `BUS_TIMEOUT` and processor’s `MEM_EXT_TIMEOUT` generics; instead, a global configuration `bus_timeout_c` in the VHDL package file is used now | |
/neorv32/trunk/README.md
7,7 → 7,8
|
## Table of Content |
|
* [Introduction](#Introduction) |
* [Overview](#Overview) |
* [Project Status](#Status) |
* [Features](#Features) |
* [FPGA Implementation Results](#FPGA-Implementation-Results) |
* [Performance](#Performance) |
18,7 → 19,7
|
|
|
## Introduction |
## Overview |
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based |
on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts: |
37,7 → 38,7
|
### [NEORV32 Processor](#Processor-Features) |
|
Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system |
Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system (**SoC**) |
that already provides common peripherals like GPIO, serial interfaces, timers, embedded |
memories and an external bus interface for connectivity and custom extension. |
All optional features and modules beyond the base CPU can be enabled and configured via |
64,23 → 65,23
For more information take a look at the [![NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
|
### Key Features |
### Key Features |
|
- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions |
- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
- [**Detailed data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf) |
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc. |
- Fully synchronous design, no latches, no gated clocks |
- Small hardware footprint and high operating frequency |
- Highly configurable CPU and processor setup |
- [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available |
* RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions |
* GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
* [**Detailed data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf) |
* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc. |
* Fully synchronous design, no latches, no gated clocks |
* Small hardware footprint and high operating frequency |
* Highly configurable CPU and processor setup |
* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available |
|
|
### Design Principles |
|
* From zero to main(): Completely open source and documented. |
* From zero to `main()`: Completely open source and documented. |
* Plain VHDL without technology-specific parts like attributes, macros or primitives. |
* Easy to use – working out of the box. |
* Clean synchronous design, no wacky combinatorial interfaces. |
88,7 → 89,7
* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz. |
|
|
### Status |
## Status |
|
The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute |
all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark). |
106,14 → 107,14
|
### To-Do / Wish List |
|
- Add AXI(-Lite) bridges |
- Synthesis results (+ wrappers?) for more platforms |
- Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org)) |
- Implement further CPU extensions: |
- Atomic operations (`A`) |
- Bitmanipulation operations (`B`), when they are "official" |
- Floating-point instructions (`F`) |
- ... |
* Add AXI(-Lite) bridges |
* Synthesis results (+ wrappers?) for more platforms |
* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org)) |
* Implement further CPU extensions: |
* Atomic operations (`A`) |
* Bitmanipulation operations (`B`), when they are "official" |
* Floating-point instructions (`F`) |
* ... |
|
|
## Features |
128,19 → 129,19
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup |
is highly customizable via the processor's top generics. |
|
- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**) |
- Optional internal **Bootloader** with UART console and automatic SPI flash boot option |
- Optional machine system timer (**MTIME**), RISC-V-compliant |
- Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io |
- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines |
- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard |
- Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt |
- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode |
- Optional watchdog timer (**WDT**) |
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**) |
- Optional GARO-based true random number generator (**TRNG**) |
- Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors |
- System configuration information memory to check hardware configuration by software (**SYSINFO**) |
* Optional processor-internal data and instruction memories (**DMEM** / **IMEM**) |
* Optional internal **Bootloader** with UART console and automatic SPI flash boot option |
* Optional machine system timer (**MTIME**), RISC-V-compliant |
* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io |
* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines |
* Optional two wire serial interface controller (**TWI**), compatible to the I²C standard |
* Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt |
* Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode |
* Optional watchdog timer (**WDT**) |
* Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**) |
* Optional GARO-based true random number generator (**TRNG**) |
* Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors |
* System configuration information memory to check hardware configuration by software (**SYSINFO**) |
|
### CPU Features |
|
312,17 → 313,17
**Configuration** |
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock |
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK |
Compiler: RISCV32-GCC 10.1.0 (rv32i) |
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain) |
Flags: default, see makefile |
Peripherals: UART for printing the results |
~~~ |
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz | |
|:--------------------------|:---------------:|:------------:|:--------------:|:-------------:| |
| `rv32i` | 26 940 bytes | `-O3` | 33.89 | 0.3389 | |
| `rv32im` | 25 772 bytes | `-O3` | 64.51 | 0.6451 | |
| `rv32im` + `FAST_MUL_EN` | 25 772 bytes | `-O3` | 80.00 | 0.8000 | |
| `rv32imc` | 19 812 bytes | `-O3` | 62.50 | 0.6250 | |
| `rv32imc` + `FAST_MUL_EN` | 19 812 bytes | `-O3` | 76.92 | 0.7692 | |
| `rv32i` | 26 940 bytes | `-O3` | 33.89 | **0.3389** | |
| `rv32im` | 25 772 bytes | `-O3` | 64.51 | **0.6451** | |
| `rv32imc` | 20 524 bytes | `-O3` | 64.51 | **0.6451** | |
| `rv32imc` + `FAST_MUL_EN` | 20 524 bytes | `-O3` | 80.00 | **0.8000** | |
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). |
|
347,11 → 348,10
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI | |
|:------------------------|----------------------:|----------------------:|:-----------:| |
| `rv32i` | 5 945 938 586 | 1 469 587 406 | 4.05 | |
| `rv32im` | 3 110 282 586 | 602 225 760 | 5.16 | |
| `rv32im` `FAST_MUL_EN` | 2 527 730 586 | 602 225 728 | 4.19 | |
| `rv32imc` | 3 217 064 278 | 602 225 530 | 5.34 | |
| `rv32imc` `FAST_MUL_EN` | 2 634 512 278 | 602 225 574 | 4.37 | |
| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** | |
| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** | |
| `rv32imc` | 3 172 969 968 | 615 388 924 | **5.16** | |
| `rv32imc` `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** | |
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). |
|
606,12 → 606,12
Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader |
uses the following default UART configuration: |
|
- 19200 Baud |
- 8 data bits |
- 1 stop bit |
- No parity bits |
- No transmission / flow control protocol (raw bytes only) |
- Newline on `\r\n` (carriage return & newline) - also for sent data |
* 19200 Baud |
* 8 data bits |
* 1 stop bit |
* No parity bits |
* No transmission / flow control protocol (raw bytes only) |
* Newline on `\r\n` (carriage return & newline) - also for sent data |
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Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image. |
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745,6 → 745,8
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org). |
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This repository was created on June 23th, 2020. |
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Made with :coffee: in Hannover, Germany. |