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    from Rev 31 to Rev 32
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Rev 31 → Rev 32

/trunk/rtl/vhdl/system/t8048.vhd
2,7 → 2,7
--
-- T8048 Microcontroller System
--
-- $Id: t8048.vhd,v 1.1 2004-03-24 21:32:27 arniml Exp $
-- $Id: t8048.vhd,v 1.2 2004-03-29 19:40:14 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
69,7 → 69,6
 
 
use work.t48_core_comp_pack.t48_core;
use work.t48_core_comp_pack.clk_gen;
use work.t48_core_comp_pack.syn_rom;
use work.t48_core_comp_pack.syn_ram;
 
80,9 → 79,9
signal db_s : std_logic_vector( 7 downto 0);
signal db_dir_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal p2_limp_s : std_logic;
signal p2_low_imp_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal p1_limp_s : std_logic;
signal p1_low_imp_s : std_logic;
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
104,37 → 103,37
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
reset_i => reset_n_i,
t0_i => t0_b,
t0_o => t0_s,
t0_dir_o => t0_dir_s,
int_n_i => int_n_i,
ea_i => ea_i,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_b,
db_o => db_s,
db_dir_o => db_dir_s,
t1_i => t1_i,
p2_i => p2_b,
p2_o => p2_s,
p2_limp_o => p2_limp_s,
p1_i => p1_b,
p1_o => p1_s,
p1_limp_o => p1_limp_s,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
xtal_i => xtal_i,
reset_i => reset_n_i,
t0_i => t0_b,
t0_o => t0_s,
t0_dir_o => t0_dir_s,
int_n_i => int_n_i,
ea_i => ea_i,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_b,
db_o => db_s,
db_dir_o => db_dir_s,
t1_i => t1_i,
p2_i => p2_b,
p2_o => p2_s,
p2_low_imp_o => p2_low_imp_s,
p1_i => p1_b,
p1_o => p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
);
 
-----------------------------------------------------------------------------
145,8 → 144,8
--
bidirs: process (t0_b, t0_s, t0_dir_s,
db_b, db_s, db_dir_s,
p1_b, p1_s, p1_limp_s,
p2_b, p2_s, p2_limp_s)
p1_b, p1_s, p1_low_imp_s,
p2_b, p2_s, p2_low_imp_s)
 
function open_collector_f(sig : std_logic) return std_logic is
variable sig_v : std_logic;
179,7 → 178,7
for i in p1_b'range loop
p1_b(i) <= open_collector_f(p1_s(i));
end loop;
-- if p1_limp_s = '1' then
-- if p1_low_imp_s = '1' then
-- p1_b <= p1_s;
-- else
-- p1_b <= (others => 'Z');
189,7 → 188,7
for i in p2_b'range loop
p2_b(i) <= open_collector_f(p2_s(i));
end loop;
-- if p2_limp_s = '1' then
-- if p2_low_imp_s = '1' then
-- p2_b <= p2_b_s;
-- else
-- p2_b <= (others => 'Z');
229,4 → 228,7
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/03/24 21:32:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
/trunk/rtl/vhdl/p1.vhd
3,7 → 3,7
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1.vhd,v 1.1 2004-03-23 21:31:52 arniml Exp $
-- $Id: p1.vhd,v 1.2 2004-03-29 19:39:58 arniml Exp $
--
-- All rights reserved
--
51,19 → 51,19
 
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
-- Port 1 Interface -------------------------------------------------------
p1_i : in word_t;
p1_o : out word_t;
p1_limp_o : out std_logic
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
 
end p1;
79,7 → 79,7
signal p1_q : word_t;
 
-- the low impedance marker
signal limp_q : std_logic;
signal low_imp_q : std_logic;
 
begin
 
92,17 → 92,17
p1_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
p1_q <= (others => '1');
limp_q <= '0';
p1_q <= (others => '1');
low_imp_q <= '0';
 
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
 
if write_p1_i then
p1_q <= data_i;
limp_q <= '1';
p1_q <= data_i;
low_imp_q <= '1';
else
limp_q <= '0';
low_imp_q <= '0';
end if;
 
end if;
117,13 → 117,13
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p1_o <= p1_q;
p1_limp_o <= limp_q;
data_o <= (others => bus_idle_level_c)
when not read_p1_i else
p1_q
when read_reg_i else
p1_i;
p1_o <= p1_q;
p1_low_imp_o <= low_imp_q;
data_o <= (others => bus_idle_level_c)
when not read_p1_i else
p1_q
when read_reg_i else
p1_i;
 
end rtl;
 
132,5 → 132,7
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
/trunk/rtl/vhdl/p2.vhd
3,7 → 3,7
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2.vhd,v 1.2 2004-03-28 13:11:43 arniml Exp $
-- $Id: p2.vhd,v 1.3 2004-03-29 19:39:58 arniml Exp $
--
-- All rights reserved
--
69,7 → 69,7
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2_limp_o : out std_logic
p2_low_imp_o : out std_logic
);
 
end p2;
89,7 → 89,7
signal p2_q : word_t;
 
-- the low impedance marker
signal limp_q : std_logic;
signal low_imp_q : std_logic;
 
-- the expander register
signal exp_q : nibble_t;
105,22 → 105,22
p2_regs: process (res_i, clk_i)
begin
if res_i = res_active_c then
p2_q <= (others => '1');
limp_q <= '0';
exp_q <= (others => '0');
p2_q <= (others => '1');
low_imp_q <= '0';
exp_q <= (others => '0');
 
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
 
if write_p2_i then
p2_q <= data_i;
limp_q <= '1';
p2_q <= data_i;
low_imp_q <= '1';
else
limp_q <= '0';
low_imp_q <= '0';
end if;
 
if write_exp_i then
exp_q <= data_i(exp_q'range);
exp_q <= data_i(exp_q'range);
end if;
 
end if;
189,7 → 189,7
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p2_limp_o <= limp_q;
p2_low_imp_o <= low_imp_q;
 
end rtl;
 
198,6 → 198,9
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/03/28 13:11:43 arniml
-- rework Port 2 expander handling
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
/trunk/rtl/vhdl/t48_core_comp_pack-p.vhd
1,6 → 1,6
-------------------------------------------------------------------------------
--
-- $Id: t48_core_comp_pack-p.vhd,v 1.1 2004-03-23 21:31:53 arniml Exp $
-- $Id: t48_core_comp_pack-p.vhd,v 1.2 2004-03-29 19:39:58 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
25,57 → 25,40
);
 
port (
xtal_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2_limp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_limp_o : out std_logic;
prog_n_o : out std_logic;
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
xtal_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
end component;
 
component clk_gate
port (
xtal_i : in std_logic;
xtal3_i : in std_logic;
clk_o : out std_logic
);
end component;
 
component clk_gen
port (
xtal_i : in std_logic;
xtal3_i : in std_logic;
res_i : in std_logic;
clk_o : out std_logic
);
end component;
 
component syn_rom
generic (
address_width_g : positive := 10
/trunk/rtl/vhdl/t48_core.vhd
2,7 → 2,7
--
-- T48 Microcontroller Core
--
-- $Id: t48_core.vhd,v 1.3 2004-03-28 21:27:50 arniml Exp $
-- $Id: t48_core.vhd,v 1.4 2004-03-29 19:39:58 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
82,38 → 82,38
 
port (
-- T48 Interface ----------------------------------------------------------
xtal_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2_limp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_limp_o : out std_logic;
prog_n_o : out std_logic;
xtal_i : in std_logic;
reset_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
-- Core Interface ---------------------------------------------------------
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
 
end t48_core;
520,24 → 520,24
use_p1: if include_port1_g = 1 generate
p1_b : p1
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p1_data_s,
write_p1_i => p1_write_p1_s,
read_p1_i => p1_read_p1_s,
read_reg_i => p1_read_reg_s,
p1_i => p1_i,
p1_o => p1_o,
p1_limp_o => p1_limp_o
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p1_data_s,
write_p1_i => p1_write_p1_s,
read_p1_i => p1_read_p1_s,
read_reg_i => p1_read_reg_s,
p1_i => p1_i,
p1_o => p1_o,
p1_low_imp_o => p1_low_imp_o
);
end generate;
 
skip_p1: if include_port1_g = 0 generate
p1_data_s <= (others => bus_idle_level_c);
p1_o <= (others => '0');
p1_limp_o <= '0';
p1_data_s <= (others => bus_idle_level_c);
p1_o <= (others => '0');
p1_low_imp_o <= '0';
end generate;
 
use_p2: if include_port2_g = 1 generate
558,14 → 558,14
pch_i => pmem_addr_s(11 downto 8),
p2_i => p2_i,
p2_o => p2_o,
p2_limp_o => p2_limp_o
p2_low_imp_o => p2_low_imp_o
);
end generate;
 
skip_p2: if include_port2_g = 0 generate
p2_data_s <= (others => bus_idle_level_c);
p2_o <= (others => '0');
p2_limp_o <= '0';
p2_data_s <= (others => bus_idle_level_c);
p2_o <= (others => '0');
p2_low_imp_o <= '0';
end generate;
 
pmem_ctrl_b : pmem_ctrl
632,6 → 632,9
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/03/28 21:27:50 arniml
-- update wiring for DA support
--
-- Revision 1.2 2004/03/28 13:13:20 arniml
-- connect control signal for Port 2 expander
--
/trunk/rtl/vhdl/t48_comp_pack-p.vhd
1,6 → 1,6
-------------------------------------------------------------------------------
--
-- $Id: t48_comp_pack-p.vhd,v 1.3 2004-03-28 21:27:49 arniml Exp $
-- $Id: t48_comp_pack-p.vhd,v 1.4 2004-03-29 19:39:58 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
308,17 → 308,17
 
component p1
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
p1_i : in word_t;
p1_o : out word_t;
p1_limp_o : out std_logic
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
end component;
 
339,7 → 339,7
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2_limp_o : out std_logic
p2_low_imp_o : out std_logic
);
end component;
 

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