OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 31 to Rev 32
    ↔ Reverse comparison
  •

Rev 31 → Rev 32

/trunk/tests/tv80_env.h
11,6 → 11,7
sfr at 0x82 timeout_port;
sfr at 0x83 max_timeout_low;
sfr at 0x84 max_timeout_high;
sfr at 0x90 intr_cntdwn;
 
#define SC_TEST_PASSED 0x01
#define SC_TEST_FAILED 0x02
47,10 → 48,7
msg_port = digits[i-1];
}
 
void sim_ctl (unsigned char code)
{
sim_ctl_port = code;
}
#define sim_ctl(code) sim_ctl_port = code
 
void set_timeout (unsigned int max_timeout)
{
/trunk/tests/bintr.c
0,0 → 1,52
#include "tv80_env.h"
 
/*
* This test covers interrupt handling routines. The actual interrupt code
* is in assembly, in bintr_crt0.asm.
*
* The test generates five interrupts, and clears the interrupt after
* each one.
*
* The isr routine uses the two writes to intr_cntdwn to first clear
* assertion of the current interrupt and then disable the countdown
* timer.
*/
 
unsigned char foo;
volatile unsigned char test_pass;
static unsigned char triggers;
 
void isr (void)
{
triggers++;
 
if (triggers > 5) {
test_pass = 1;
intr_cntdwn = 255;
intr_cntdwn = 0;
} else
intr_cntdwn = 32;
}
 
int main ()
{
int i;
unsigned char check;
 
test_pass = 0;
triggers = 0;
 
// start interrupt countdown
intr_cntdwn = 64;
 
for (i=0; i<200; i++)
check = sim_ctl_port;
 
if (test_pass)
sim_ctl (SC_TEST_PASSED);
else
sim_ctl (SC_TEST_FAILED);
 
return 0;
}
 
/trunk/tests/bintr_crt0.asm
0,0 → 1,70
;; Generic crt0.s for a Z80
.module bintr_crt0
.globl _main
.globl _isr
 
.area _HEADER (ABS)
;; Reset vector
.org 0
jp init
 
.org 0x08
reti
.org 0x10
reti
.org 0x18
reti
.org 0x20
reti
.org 0x28
reti
.org 0x30
reti
.org 0x38
di
call _isr
ei
reti
.org 0x100
init:
;; Stack at the top of memory.
ld sp,#0xffff
 
;; enable interrupts
im 1
ei
;; Initialise global variables
call _main
jp _exit
 
;; Ordering of segments for the linker.
.area _HOME
.area _CODE
.area _GSINIT
.area _GSFINAL
.area _DATA
.area _BSS
.area _HEAP
 
.area _CODE
__clock::
ld a,#2
rst 0x08
ret
_exit::
;; Exit - special code to the emulator
ld a,#0
rst 0x08
1$:
halt
jr 1$
 
.area _GSINIT
gsinit::
 
.area _GSFINAL
ret
/trunk/tests/Makefile
1,12 → 1,12
# Makefile for Z80 C/Assembly files
# Assumes that SDCC is installed parallel to TV80 root
# SDCC_HOME environment variable should be set to SDCC install location
 
SDCC_ROOT=../../sdcc
SDCC_ROOT=$(SDCC_HOME)
CC=$(SDCC_ROOT)/bin/sdcc -mz80
AS=$(SDCC_ROOT)/bin/as-z80
LD=$(SDCC_ROOT)/bin/link-z80
IHEX2MEM=../scripts/ihex2mem.py
LINK_OPTIONS=-- -m -j -x -b_CODE=0x0200 -b_DATA=0x8000 -k$(SDCC_ROOT)/share/sdcc/lib/z80 -k$(SDCC_ROOT)/lib/z80 -lz80
LINK_OPTIONS=-- -m -j -x -b_CODE=0x0200 -b_DATA=0x8000 -k$(SDCC_ROOT)/device/lib/z80 -k$(SDCC_ROOT)/lib/z80 -lz80
AS_LINK_OPTIONS=-bBOOT_VEC=0x0000 -bINT_VEC=0x0038
C_LINK_OPTIONS=$(SDCC_ROOT)/share/sdcc/lib/z80/crt0.o
 
22,6 → 22,9
%.ihx : %.o
$(LD) $(LINK_OPTIONS) $(AS_LINK_OPTIONS) -i $* $^ -e
 
bintr.ihx : bintr.c bintr_crt0.o
$(CC) --no-std-crt0 bintr.c bintr_crt0.o
 
clean :
rm -f *.map
rm -f *.mem

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.