URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/uart_block/trunk/hdl/iseProject/isim.log
1,5 → 1,5
ISim log file |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
11,81 → 11,10
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
In process testUart_communication_block.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
# exit 0 |
/uart_block/trunk/hdl/iseProject/serial_receiver.vhd
19,7 → 19,8
architecture Behavioral of serial_receiver is |
signal current_s: rxStates; |
signal filterRx : rxFilterStates; |
signal syncDetected : std_logic; |
signal syncDetected : std_logic; |
--signal getPoint : std_logic; |
|
begin |
-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC |
59,12 → 60,21
syncDetected <= '0'; |
else |
filterRx <= s0; |
end if; |
|
when s3 => |
syncDetected <= '0'; |
if serial_in = '0' then |
filterRx <= s4; |
syncDetected <= '0'; |
else |
filterRx <= s0; |
end if; |
|
when s3 => |
when s4 => |
-- Real Beginning of start bit detected |
if serial_in = '0' then |
filterRx <= s3; |
filterRx <= s4; |
syncDetected <= '1'; |
end if; |
|
78,55 → 88,115
|
-- Process to handle the serial receive (On this case our reset is the syncDetected signal |
-- Always include all of your signals on the sensivity list!! (Even if the simulation is already ok) |
process (syncDetected, baudClk, serial_in) |
variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0); |
process (syncDetected, baudOverSampleClk, serial_in) |
variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0); |
variable waitBestPoint : integer range 0 to 10; |
constant numTicks : integer := 7; |
begin |
if syncDetected = '0' then |
current_s <= bit0; |
data_ready <= '0'; |
byteReceived := (others => '0'); |
elsif rising_edge(baudClk) then |
byteReceived := (others => '0'); |
waitBestPoint := 0; |
--getPoint <= '0'; |
elsif rising_edge(baudOverSampleClk) then |
case current_s is |
when bit0 => |
data_ready <= '0'; |
byteReceived(0) := serial_in; |
current_s <= bit1; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(0) := serial_in; |
current_s <= bit1; |
--getPoint <= '1'; |
end if; |
|
when bit1 => |
data_ready <= '0'; |
byteReceived(1) := serial_in; |
current_s <= bit2; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(1) := serial_in; |
current_s <= bit2; |
--getPoint <= '1'; |
end if; |
|
when bit2 => |
data_ready <= '0'; |
byteReceived(2) := serial_in; |
current_s <= bit3; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(2) := serial_in; |
current_s <= bit3; |
--getPoint <= '1'; |
end if; |
|
when bit3 => |
data_ready <= '0'; |
byteReceived(3) := serial_in; |
current_s <= bit4; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(3) := serial_in; |
current_s <= bit4; |
--getPoint <= '1'; |
end if; |
|
when bit4 => |
data_ready <= '0'; |
byteReceived(4) := serial_in; |
current_s <= bit5; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(4) := serial_in; |
current_s <= bit5; |
--getPoint <= '1'; |
end if; |
|
when bit5 => |
data_ready <= '0'; |
byteReceived(5) := serial_in; |
current_s <= bit6; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(5) := serial_in; |
current_s <= bit6; |
--getPoint <= '1'; |
end if; |
|
when bit6 => |
data_ready <= '0'; |
byteReceived(6) := serial_in; |
current_s <= bit7; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(6) := serial_in; |
current_s <= bit7; |
--getPoint <= '1'; |
end if; |
|
when bit7 => |
data_ready <= '0'; |
byteReceived(7) := serial_in; |
data_byte <= byteReceived; |
current_s <= rx_stop; |
data_ready <= '0'; |
if (waitBestPoint < numTicks) then |
waitBestPoint := waitBestPoint + 1; |
--getPoint <= '0'; |
else |
waitBestPoint := 0; |
byteReceived(7) := serial_in; |
data_byte <= byteReceived; |
current_s <= rx_stop; |
--getPoint <= '1'; |
end if; |
|
when rx_stop => |
data_ready <= '1'; |
/uart_block/trunk/hdl/iseProject/fuseRelaunch.cmd
1,55 → 88,115
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_beh.prj" "testUart_communication_block" |
/uart_block/trunk/hdl/iseProject/pkgDefinitions.vhd
23,7 → 23,7
|
type txStates is (tx_idle, tx_start, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, tx_stop1, tx_stop2); |
type rxStates is (bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, rx_stop, rx_idle); |
type rxFilterStates is (s0, s1, s2, s3); |
type rxFilterStates is (s0, s1, s2, s3, s4); |
|
type sendByte is (idle, prepare_byte, start_sending, wait_completion); |
|
/uart_block/trunk/hdl/iseProject/fuse.log
1,4 → 1,4
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -relaunch -intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_beh.prj testUart_communication_block |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
6,35 → 6,28
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work |
WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 37472 KB |
Fuse CPU Usage: 1110 ms |
Fuse Memory Usage: 37468 KB |
Fuse CPU Usage: 1080 ms |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package std_logic_unsigned |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity divisor [divisor_default] |
Compiling architecture behavioral of entity uart_control [uart_control_default] |
Compiling package numeric_std |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default] |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default] |
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...] |
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Compiling architecture behavior of entity testuart_communication_block |
Time Resolution for simulation is 1ps. |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 21 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 90296 KB |
Fuse CPU Usage: 1280 ms |
GCC CPU Usage: 230 ms |
Compiled 15 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe |
Fuse Memory Usage: 90156 KB |
Fuse CPU Usage: 1250 ms |
GCC CPU Usage: 500 ms |
/uart_block/trunk/hdl/iseProject/webtalk_pn.xml
1,50 → 1,49
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Fri May 04 03:12:11 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="27" type="project"/> |
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
<section name="Project Statistics" visible="true"> |
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> |
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/> |
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
<property name="PROP_FitterReportFormat" value="HTML" type="process"/> |
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
<property name="PROP_UseSmartGuide" value="false" type="design"/> |
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWbtProjectIteration" value="27" type="process"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_DevFamily" value="Spartan3E" type="design"/> |
<property name="PROP_DevDevice" value="xc3s500e" type="design"/> |
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> |
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/> |
<property name="PROP_DevPackage" value="fg320" type="design"/> |
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_CDC" value="1" type="source"/> |
<property name="FILE_UCF" value="1" type="source"/> |
<property name="FILE_VHDL" value="18" type="source"/> |
</section> |
</application> |
</document> |
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Fri May 4 12:25:47 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="27" type="project"/> |
<property name="ProjectFile" value="/home/laraujo/work/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
<section name="Project Statistics" visible="true"> |
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> |
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/> |
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
<property name="PROP_UseSmartGuide" value="false" type="design"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWbtProjectIteration" value="27" type="process"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/> |
<property name="PROP_DevFamily" value="Spartan3E" type="design"/> |
<property name="PROP_DevDevice" value="xc3s500e" type="design"/> |
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> |
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/> |
<property name="PROP_DevPackage" value="fg320" type="design"/> |
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_CDC" value="1" type="source"/> |
<property name="FILE_UCF" value="1" type="source"/> |
<property name="FILE_VHDL" value="18" type="source"/> |
</section> |
</application> |
</document> |
/uart_block/trunk/hdl/iseProject/testUart_communication_block.vhd
43,7 → 43,7
signal serial_out : std_logic; |
|
-- Clock period definitions |
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz) |
constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz) |
|
BEGIN |
|
77,7 → 77,7
-- Setup communication blocks |
rst <= '1'; |
serial_in <= '1'; -- Idle.. |
cycle_wait_baud <= conv_std_logic_vector(16, (nBitsLarge)); |
cycle_wait_baud <= conv_std_logic_vector(434, (nBitsLarge)); |
start_tx <= '0'; |
wait for 2 ns; |
rst <= '0'; |
123,7 → 123,7
|
-- Stop bit here |
serial_in <= '1'; |
wait for clk_period*20; |
wait for clk_period*200; |
|
-- Receive 0xC4 value (11000100) |
serial_in <= '0'; -- Start bit |
148,7 → 148,7
|
-- Stop bit here |
serial_in <= '1'; |
wait for clk_period*20; |
wait for clk_period*200; |
|
|
|
/uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
1,12 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
1,965 → 1,1031
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">80</arg>: Unconnected output port '<arg fmt="%s" index="3">CYC_O</arg>' of component '<arg fmt="%s" index="4">SERIALMASTER</arg>'. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/INTERCON_P2P</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">80</arg>: Unconnected output port '<arg fmt="%s" index="3">SEL_O</arg>' of component '<arg fmt="%s" index="4">SERIALMASTER</arg>'. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/INTERCON_P2P/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">95</arg>: Unconnected output port '<arg fmt="%s" index="3">data_Avaible</arg>' of component '<arg fmt="%s" index="4">uart_wishbone_slave</arg>'. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/SERIALMASTER</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="1610" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>" line <arg fmt="%d" index="2">46</arg>: Width mismatch. <<arg fmt="%s" index="3">byteIncome</arg>> has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/SERIALMASTER/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">62</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/SYC0001a</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/SYC0001a.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">DAT_I<31:8></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/SYC0001a/SYC0001a1</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/SYC0001a.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">CYC_O</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/uart_wishbone_slave</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">SEL_O</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/uart_wishbone_slave/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd</arg>". |
</msg> |
|
<msg type="warning" file="Xst" num="1306" delta="old" >Output <<arg fmt="%s" index="1">data_avaible</arg>> is never assigned. |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/uart_communication_blocks</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/uart_communication_blocks/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/uart_control</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/uart_control/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/baud_generator</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/baud_generator.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/baud_generator/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/baud_generator.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/divisor</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/divisor.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/divisor/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/divisor.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/serial_receiver</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/serial_receiver.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/serial_receiver/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/serial_receiver.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/serial_transmitter</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/serial_transmitter.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/serial_transmitter/Behavioral</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/serial_transmitter.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/pkgDefinitions</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/pkgDefinitions.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
<msg type="warning" file="HDLParsers" num="3607" delta="new" >Unit <arg fmt="%s" index="1">work/pkgDefinitions</arg> is now defined in a different file. It was defined in "<arg fmt="%s" index="2">E:/uart_block/hdl/iseProject/pkgDefinitions.vhd</arg>", and is now defined in "<arg fmt="%s" index="3">/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd</arg>". |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">80</arg>: Unconnected output port '<arg fmt="%s" index="3">CYC_O</arg>' of component '<arg fmt="%s" index="4">SERIALMASTER</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">80</arg>: Unconnected output port '<arg fmt="%s" index="3">SEL_O</arg>' of component '<arg fmt="%s" index="4">SERIALMASTER</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">95</arg>: Unconnected output port '<arg fmt="%s" index="3">data_Avaible</arg>' of component '<arg fmt="%s" index="4">uart_wishbone_slave</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1610" delta="new" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>" line <arg fmt="%d" index="2">46</arg>: Width mismatch. <<arg fmt="%s" index="3">byteIncome</arg>> has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">62</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">DAT_I<31:8></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">CYC_O</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">SEL_O</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1306" delta="old" >Output <<arg fmt="%s" index="1">data_avaible</arg>> is never assigned. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uBaudGen</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uBaudGen</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycles2Wait_0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_2</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_3</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_4</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_23</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>> in Unit <<arg fmt="%s" index="2">serial_receiver</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><data_ready> </arg> |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">uart_control</arg>: <arg fmt="%d" index="2">32</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycles2Wait_0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_2</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_3</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_4</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_23</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>> in Unit <<arg fmt="%s" index="2">serial_receiver</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><data_ready> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">uart_control</arg>: <arg fmt="%d" index="2">32</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<11></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<18></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<24></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<26></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<27></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<28></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<29></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<30></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<31></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<8></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. |
</msg> |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<11></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<18></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<24></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<26></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<27></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<28></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<29></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<30></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<31></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<8></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. |
</msg> |
|
</messages> |
|
|
/uart_block/trunk/hdl/iseProject/baud_generator.vhd
61,10 → 61,11
if rst = '1' then |
wait_clk_cycles := (others => '0'); |
|
-- Divide cycle_wait by 4 |
-- Divide cycle_wait by 8 |
--cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1); |
--cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1); |
cycle_wait_oversample := "00" & cycle_wait(cycle_wait'high downto 2); -- Shift right by 2 |
--cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1); |
cycle_wait_oversample := "000" & cycle_wait(cycle_wait'high downto 3); -- Shift right by 3 |
|
|
-- Half of cycle_wait_oversample |
86,7 → 87,7
|
-- Avoid creation of transparent latch (By default the VHDL will create an register for vectors that are assigned only in one |
-- ocasion of a (if, case) instruction |
cycle_wait_oversample := "00" & cycle_wait(cycle_wait'high downto 2); |
cycle_wait_oversample := "000" & cycle_wait(cycle_wait'high downto 3); |
half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1); |
end if; |
end process; |
/uart_block/trunk/hdl/iseProject/iseProject.xise
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/> |
</file> |
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL"> |
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/> |
</file> |
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL"> |
60,17 → 60,17
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/> |
</file> |
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="103"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="103"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/> |
</file> |
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL"> |
80,25 → 80,25
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/> |
</file> |
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/> |
</file> |
<file xil_pn:name="SYC0001a.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
</file> |
<file xil_pn:name="SERIALMASTER.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
</file> |
<file xil_pn:name="INTERCON_P2P.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="141"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
<file xil_pn:name="pins_spartan3EStarterKit.ucf" xil_pn:type="FILE_UCF"> |
133,7 → 133,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
331,8 → 331,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_communication_block" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
348,7 → 348,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
398,7 → 398,7
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_communication_block|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
/uart_block/trunk/hdl/iseProject/xst/work/hdpdeps.ref
1,81 → 1,97
V3 51 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/02.17:47:51 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.17:54:04 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd |
EN work/baud_generator 1336093055 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \ |
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \ |
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336093054 |
AR work/baud_generator/Behavioral 1336093056 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336093055 |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
EN work/divisor 1336093061 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1336093054 |
AR work/divisor/Behavioral 1336093062 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336093061 |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd |
EN work/INTERCON_P2P 1336093073 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/INTERCON_P2P/Behavioral 1336093074 \ |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336093073 \ |
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/03.23:01:52 O.87xd |
PH work/pkgDefinitions 1336093053 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1336093054 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336093053 |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.01:05:05 O.87xd |
EN work/SERIALMASTER 1336093069 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336093054 |
AR work/SERIALMASTER/Behavioral 1336093070 \ |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336093069 |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/04.02:53:30 O.87xd |
EN work/serial_receiver 1336093059 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \ |
PB work/pkgDefinitions 1336093054 |
AR work/serial_receiver/Behavioral 1336093060 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336093059 |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
EN work/serial_transmitter 1336093057 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336093054 |
AR work/serial_transmitter/Behavioral 1336093058 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1336093057 |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd |
EN work/SYC0001a 1336093067 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/SYC0001a/SYC0001a1 1336093068 \ |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336093067 |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd |
EN work/uart_communication_blocks 1336093065 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336093054 |
AR work/uart_communication_blocks/Behavioral 1336093066 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1336093065 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_control 1336093063 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336093054 |
AR work/uart_control/Behavioral 1336093064 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336093063 \ |
CP divisor |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_wishbone_slave 1336093071 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336093054 |
AR work/uart_wishbone_slave/Behavioral 1336093072 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1336093071 CP uart_control \ |
CP uart_communication_blocks |
V3 54 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
EN work/baud_generator 1336127156 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \ |
PB work/pkgDefinitions 1336127155 |
AR work/baud_generator/Behavioral 1336127157 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
EN work/baud_generator 1336127156 |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
EN work/divisor 1336127162 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1336127155 |
AR work/divisor/Behavioral 1336127163 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336127162 |
FL /home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.10:27:16 O.87xd |
EN work/INTERCON_P2P 1336127174 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/INTERCON_P2P/Behavioral 1336127175 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
EN work/INTERCON_P2P 1336127174 CP SYC0001a CP SERIALMASTER \ |
CP uart_wishbone_slave |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/04.10:27:16 O.87xd |
PH work/pkgDefinitions 1336127154 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1336127155 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PH work/pkgDefinitions 1336127154 |
FL /home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.10:27:16 O.87xd |
EN work/SERIALMASTER 1336127170 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336127155 |
AR work/SERIALMASTER/Behavioral 1336127171 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
EN work/SERIALMASTER 1336127170 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
EN work/serial_receiver 1336127160 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336127155 |
AR work/serial_receiver/Behavioral 1336127161 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
EN work/serial_receiver 1336127160 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
EN work/serial_transmitter 1336127158 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336127155 |
AR work/serial_transmitter/Behavioral 1336127159 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1336127158 |
FL /home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.10:27:16 O.87xd |
EN work/SYC0001a 1336127168 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/SYC0001a/SYC0001a1 1336127169 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd \ |
EN work/SYC0001a 1336127168 |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
EN work/uart_communication_blocks 1336127166 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336127155 |
AR work/uart_communication_blocks/Behavioral 1336127167 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1336127166 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.17:56:59 O.87xd |
EN work/uart_control 1336127164 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336127155 |
AR work/uart_control/Behavioral 1336127165 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1336127164 CP divisor |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/02.08:07:03 O.87xd |
EN work/uart_wishbone_slave 1336127172 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336127155 |
AR work/uart_wishbone_slave/Behavioral 1336127173 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1336127172 CP uart_control \ |
CP uart_communication_blocks |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/03.23:01:52 O.87xd |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.01:05:05 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/04.02:53:30 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd |
/uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
1,22 → 1,22
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336093066 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336093064 |
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336093068 |
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336093073 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336093054 |
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336093059 |
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336093072 |
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336093058 |
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336093065 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336093061 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336093062 |
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336093056 |
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336093067 |
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336093069 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336093063 |
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336093074 |
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336093057 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336093053 |
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336093070 |
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336093071 |
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336093055 |
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336093060 |
EN serialmaster NULL /home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336127170 |
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336127164 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336127159 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336127172 |
AR syc0001a syc0001a1 /home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336127169 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336127157 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336127160 |
AR intercon_p2p behavioral /home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336127175 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336127162 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336127163 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336127158 |
EN intercon_p2p NULL /home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336127174 |
EN syc0001a NULL /home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336127168 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336127167 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336127173 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336127161 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336127166 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336127155 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336127165 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336127156 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336127154 |
AR serialmaster behavioral /home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336127171 |
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl00.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream