URL
https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk
Subversion Repositories vga_lcd
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- This comparison shows the changes necessary to convert path
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- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/trunk/rtl/verilog/vga_wb_slave.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: vga_wb_slave.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $ |
// $Id: vga_wb_slave.v,v 1.7 2002-02-25 06:13:44 rherveille Exp $ |
// |
// $Date: 2002-02-07 05:42:10 $ |
// $Revision: 1.6 $ |
// $Date: 2002-02-25 06:13:44 $ |
// $Revision: 1.7 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,12
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/02/07 05:42:10 rherveille |
// Fixed some bugs discovered by modified testbench |
// Removed / Changed some strange logic constructions |
// Started work on hardware cursor support (not finished yet) |
// Changed top-level name to vga_enh_top.v |
// |
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`include "timescale.v" |
195,19 → 201,27
begin : gen_regs |
if(!nRESET) |
begin |
htim <= #1 0; |
vtim <= #1 0; |
hvlen <= #1 0; |
VBARa <= #1 0; |
VBARb <= #1 0; |
htim <= #1 0; |
vtim <= #1 0; |
hvlen <= #1 0; |
VBARa <= #1 0; |
VBARb <= #1 0; |
cursor0_xy <= #1 0; |
cursor0_ba <= #1 0; |
cursor1_xy <= #1 0; |
cursor1_ba <= #1 0; |
end |
else if (RST_I) |
begin |
htim <= #1 0; |
vtim <= #1 0; |
hvlen <= #1 0; |
VBARa <= #1 0; |
VBARb <= #1 0; |
htim <= #1 0; |
vtim <= #1 0; |
hvlen <= #1 0; |
VBARa <= #1 0; |
VBARb <= #1 0; |
cursor0_xy <= #1 0; |
cursor0_ba <= #1 0; |
cursor1_xy <= #1 0; |
cursor1_ba <= #1 0; |
end |
else if (reg_wacc) |
case (ADR_I) // synopsis full_case parallel_case |
327,7 → 341,8
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// assign output |
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp) |
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or |
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba) |
case (REG_ADR) // synopsis full_case parallel_case |
CTRL_ADR : reg_dato = ctrl; |
STAT_ADR : reg_dato = stat; |