URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
Subversion Repositories xucpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/xucpu/trunk/src/system/S2MEM.vhdl
0,0 → 1,22
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
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ENTITY S2MEM IS |
PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
I_RD : IN STD_LOGIC; |
I_WR : IN STD_LOGIC; |
I_ADDRESS : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
END ENTITY S2MEM; |
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ARCHITECTURE Structural OF S2MEM IS |
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BEGIN -- ARCHITECTURE Structural |
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END ARCHITECTURE Structural; |
/xucpu/trunk/src/system/S2CPU.vhdl
0,0 → 1,27
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
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ENTITY S2CPU IS |
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PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
O_IF : OUT STD_LOGIC; |
O_INSTR_ADDR : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_INSTRUCTION : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_RD : OUT STD_LOGIC; |
O_WR : OUT STD_LOGIC; |
O_DATA_ADDR : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0)); |
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END ENTITY S2CPU; |
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ARCHITECTURE Structural OF S2CPU IS |
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BEGIN -- ARCHITECTURE Structural |
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END ARCHITECTURE Structural; |
/xucpu/trunk/src/system/S2DCC.vhdl
0,0 → 1,33
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
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ENTITY S2DCC IS |
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PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
O_ADDRESS : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_RD : OUT STD_LOGIC; |
O_WR : OUT STD_LOGIC; |
I_ACK : IN STD_LOGIC; |
I_ADDRESS : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
I_RD : IN STD_LOGIC; |
I_WR : IN STD_LOGIC; |
I_CPU_RD : IN STD_LOGIC; |
I_CPU_WR : IN STD_LOGIC; |
I_CPU_DATA_ADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_CPU_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_CPU_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
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END ENTITY S2DCC; |
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ARCHITECTURE Structural OF S2DCC IS |
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BEGIN -- ARCHITECTURE Structural |
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END ARCHITECTURE Structural; |
/xucpu/trunk/src/system/S2ICC.vhdl
0,0 → 1,31
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
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ENTITY S2ICC IS |
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PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
O_ADDRESS : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_RD : OUT STD_LOGIC; |
O_WR : OUT STD_LOGIC; |
I_ACK : IN STD_LOGIC; |
I_ADDRESS : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
I_RD : IN STD_LOGIC; |
I_WR : IN STD_LOGIC; |
I_CPU_IF : IN STD_LOGIC; |
I_CPU_INSTR_ADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_CPU_INSTRUCTION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
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END ENTITY S2ICC; |
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ARCHITECTURE Structural OF S2ICC IS |
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BEGIN -- ARCHITECTURE Structural |
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END ARCHITECTURE Structural; |
/xucpu/trunk/src/system/S2ARB.vhdl
0,0 → 1,28
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
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ENTITY S2ARB IS |
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PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
I_RD_ICC : IN STD_LOGIC; |
I_WR_ICC : IN STD_LOGIC; |
I_RD_DCC : IN STD_LOGIC; |
I_WR_DCC : IN STD_LOGIC; |
O_ADDRESS_MUX_SEL : OUT STD_LOGIC; |
O_ACK_ICC : OUT STD_LOGIC; |
O_ACK_DCC : OUT STD_LOGIC); |
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END ENTITY S2ARB; |
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ARCHITECTURE Structural OF S2ARB IS |
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BEGIN -- ARCHITECTURE Structural |
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END ARCHITECTURE Structural; |
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