OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 311 to Rev 312
    ↔ Reverse comparison
  •

Rev 311 → Rev 312

/trunk/or1ksim/sim.cfg
1,5 → 1,7
/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
This file includes a lot of help about configurations and default one
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
17,6 → 19,67
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
The or1ksim have various parameters, which can be set in configuration
files. Multiple configurations may be used and switched between at
or1ksim startup.
By default, or1ksim loads condfiguration file from './sim.cfg' and if not
found it checks '~/.or1k/sim.cfg'. If even this file is not found or
all parameters are not defined, default configuration is used.
Users should not rely on default configuration, but rather redefine all
critical settings, since default configuration may differ in newer
versions of the or1ksim.
If multiple configurations are used, user can switch between them by
supplying -f <filename.cfg> option when starting simulator.
This file may contain (standard C) only comments - no // support.
 
Like normal configuration file, this file is divided in sections,
where each section is described in detail also.
Some section also have subsections. One example of such subsection is
block:
device <index>
instance specific parameters...
enddevice
which creates a device instance.
*/
 
/* MEMORY SECTION
 
This section specifies how is initial memory generated and which blocks
it consist of.
memory_table_file = "<filename>"
loads memory table from filename. If filename does not exists in the
current directory, it is loaded from ~/.or1k/<filename>.
Memory table file structure is as follows:
start_address1 length1 type1 [ce1 [delayr1 [delayw1]]]
start_address2 length2 type2 [ce2 [delayr2 [delayw2]]]
start_address3 length3 type3 [ce3 [delayr3 [delayw3]]]
Example:
00000100 00001F00 flash 3 100
80000000 00010000 RAM
type = random/unknown/pattern
specifies the initial memory values. 'random' parameter generate
random memory using seed 'random_seed' parameter. 'pattern' parameter
fills memory with 'pattern' parameter and 'unknown' does not specify
how memory should be generated - the fastest option.
random_seed = <value>
random seed for randomizer, used if type = random
pattern = <value>
pattern to fill memory, , used if type = pattern
*/
 
section memory
memory_table_file = "simmem.cfg"
/*random_seed = 12345
25,6 → 88,86
type = unknown /* Fastest */
end
 
 
/* SIM SECTION
 
This section specifies how should sim behave.
verbose = 0/1
whether to print out extra messages
debug = 0/1
whether to print out sim debug information
profile = 0/1
whether to generate profiling file 'sim.profile'
prof_fn = "<filename>"
filename, where to generate profiling info, used
only if 'profile' is set
iprompt = 0/1
whether we strart in interactive prompt
 
exe_log = 0/1
whether execution log should be generated
exe_log_fn = "<filename>"
where to put execution log in, used only if 'exe_log'
is set
section sim
/*verbose = 1*/
debug = 0
profile = 0
prof_fn = "sim.profile"
/* iprompt = 0 */
exe_log = 0
exe_log_fn = "executed.log"
end
 
 
/* SECTION VAPI
 
This section configures Verification API, used for Advanced
Core Verification.
enabled = 0/1
whether to start VAPI server
server_port = <value>
TCP/IP port to start VAPI server on
*/
 
section VAPI
enabled = 0
server_port = 9998
end
 
 
/* CPU SECTION
 
This section specifies various CPU parameters.
ver = <value>
rev = <value>
specifies version and revision of the CPU used
upr = <value>
changes the upr register
superscalar = 0/1
hazards = 0/1
history = 0/1
dependstats = 0/1
dependency = 0/1
slp = 0/1
btic = 0/1
bpb = 0/1
parameters for CPU analysis
*/
 
section cpu
ver = 0x1200
rev = 0x0001
39,23 → 182,42
bpb = 0
end
 
 
/* DEBUG SECTION
 
This sections specifies how debug unit should behave.
enabled = 0/1
whether debug unit is enabled
gdb_enabled = 0/1
whether to start gdb server at 'server_port' port
server_port = <value>
TCP/IP port to start gdb server on, used only if gdb_enabled
is set
section debug
/*enabled = 0
gdb_enabled = 0*/
enabled = 0
gdb_enabled = 0
server_port = 9999
end
 
section sim
/*verbose*/
debug = 0
profile = 0
prof_fn = "sim.profile"
/* iprompt = 0 */
exe_log = 0
exe_log_fn = "executed.log"
end
 
/* MC SECTION
 
This section configures the memory controller
 
enabled = 0/1
whether memory controller is enabled
baseaddr = <hex_value>
address of first MC register
POC = <hex_value>
Power On Configuration register
*/
 
section mc
enabled = 0
baseaddr = 0xa0000000
62,6 → 224,32
POC = 0x00000008 /* Power on configuration register */
end
 
 
/* UART SECTION
 
This section configures UARTs
 
enabled = 0/1
whether uarts are enabled
nuarts = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first UART register for this device
rx_file = "<filename>"
filename, where to read data from
tx_file = "<filename>"
filename, where to write data to
jitter = <value>
in msecs... time to block, -1 to disable it
*/
 
section uart
enabled = 0
nuarts = 1
74,6 → 262,26
enddevice
end
 
 
/* DMA SECTION
 
This section configures DMAs
 
enabled = 0/1
whether DMAs are enabled
ndmas = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first DMA register for this device
 
irq = <value>
irq number for this device
*/
 
section dma
enabled = 0
ndmas = 1
84,11 → 292,38
enddevice
end
 
section VAPI
enabled = 0
server_port = 9998
end
 
/* ETHERNET SECTION
 
This section configures ethernets
 
enabled = 0/1
whether ethernets are enabled
nethernets = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first ethernet register for this device
 
dma = <value>
which controller is this ethernet "connected" to
rx_channel = <value>
DMA channel used for RX
tx_channel = <value>
DMA channel used for TX
 
rx_file = "<filename>"
filename, where to read data from
tx_file = "<filename>"
filename, where to write data to
*/
 
section ethernet
enabled = 0
nethernets = 1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.