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URL https://opencores.org/ocsvn/t48/t48/trunk

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    from Rev 312 to Rev 313
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Rev 312 → Rev 313

/t48/trunk/bench/vhdl/upi_stim.vhd
21,14 → 21,17
architecture behav of upi_stim is
 
subtype word_t is std_logic_vector(7 downto 0);
alias int_ibf_n : std_logic is p2_b(5);
alias int_obf : std_logic is p2_b(4);
 
begin
 
stim: process
 
constant test_echo_c : word_t := "00000001";
constant test_status41_c : word_t := "00000010";
constant test_status41a_c : word_t := "00000011";
constant test_echo_c : word_t := "00000001";
constant test_status41_c : word_t := "00000010";
constant test_status41a_c : word_t := "00000011";
constant test_master_int_c : word_t := "00000100";
 
constant del_seq_c : time := 5 us;
constant del_dat_c : time := 10 us;
90,7 → 93,6
 
read_dbbout(a0 => '0');
if rdata /= "10101010" then
-- error
fail_o <= true;
end if;
 
105,7 → 107,6
-- test F1=0, F0=0, IBF=0, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "0000" then
-- error
fail_o <= true;
end if;
 
115,7 → 116,6
-- test F1=1, F0=0, IBF=1, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "1010" then
-- error
fail_o <= true;
end if;
 
125,7 → 125,6
-- test F1=0, F0=0, IBF=1, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "0010" then
-- error
fail_o <= true;
end if;
 
135,7 → 134,6
-- test F1=1, F0=1, IBF=0, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "1100" then
-- error
fail_o <= true;
end if;
 
145,7 → 143,6
-- test F1=0, F0=0, IBF=0, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "0000" then
-- error
fail_o <= true;
end if;
 
155,19 → 152,16
-- test F1=1, F0=1, IBF=0, OBF=1
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "1101" then
-- error
fail_o <= true;
end if;
-- read OBF, test for 099H
read_dbbout(a0 => '0');
if rdata /= "10011001" then
-- error
fail_o <= true;
end if;
-- test F1=1, F0=1, IBF=0, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "1100" then
-- error
fail_o <= true;
end if;
 
178,19 → 172,16
-- test F1=1, F0=0, IBF=0, OBF=1
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "1001" then
-- error
fail_o <= true;
end if;
-- read OBF; test for 066H
read_dbbout(a0 => '0');
if rdata /= "01100110" then
-- error
fail_o <= true;
end if;
-- test F1=1, F0=0, IBF=0, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "1000" then
-- error
fail_o <= true;
end if;
 
205,7 → 196,6
-- test F1=0, F0=0, IBF=0, OBF=0
read_dbbout(a0 => '1');
if rdata(3 downto 0) /= "0000" then
-- error
fail_o <= true;
end if;
 
215,13 → 205,11
-- test STS=A, F1=1, F0=0, IBF=0, OBF=1
read_dbbout(a0 => '1');
if rdata /= "10101001" then
-- error
fail_o <= true;
end if;
--
read_dbbout(a0 => '0');
if rdata /= "00000001" then
-- error
fail_o <= true;
end if;
 
231,13 → 219,11
-- test STS=5, F1=0, F0=0, IBF=0, OBF=1
read_dbbout(a0 => '1');
if rdata /= "01010001" then
-- error
fail_o <= true;
end if;
--
read_dbbout(a0 => '0');
if rdata /= "00000010" then
-- error
fail_o <= true;
end if;
 
247,13 → 233,11
-- test STS=0, F1=1, F0=0, IBF=0, OBF=1
read_dbbout(a0 => '1');
if rdata /= "00001001" then
-- error
fail_o <= true;
end if;
--
read_dbbout(a0 => '0');
if rdata /= "00000011" then
-- error
fail_o <= true;
end if;
 
263,13 → 247,11
-- test STS=0, F1=0, F0=0, IBF=0, OBF=1
read_dbbout(a0 => '1');
if rdata /= "00000001" then
-- error
fail_o <= true;
end if;
--
read_dbbout(a0 => '0');
if rdata /= "00000100" then
-- error
fail_o <= true;
end if;
 
277,6 → 259,74
write_dbbin(data => test_status41a_c, a0 => '1');
end;
 
---------------------------------------------------------------------------
--
procedure master_int_test is
begin
-- check master interrupt lines are low
if int_ibf_n /= '0' or int_obf /= '0' then
fail_o <= true;
end if;
-- acknowledge
write_dbbin(data => not test_master_int_c, a0 => '0');
 
while int_ibf_n = '0' loop
end loop;
 
-- test IBF=1, OBF=0
if int_ibf_n /= 'H' or int_obf /= '0' then
fail_o <= true;
end if;
 
-- send another byte
write_dbbin(data => test_master_int_c, a0 => '1');
 
while int_ibf_n = '0' loop
end loop;
 
-- test IBF=1, OBF=0
if int_ibf_n /= 'H' or int_obf /= '0' then
fail_o <= true;
end if;
 
-- send turnover byte
write_dbbin(data => "10101010", a0 => '0');
 
while int_obf = '0' loop
end loop;
 
-- test IBF=0, OBF=1
if int_ibf_n /= '0' and int_obf /= 'H' then
fail_o <= true;
end if;
--
read_dbbout(a0 => '0');
if rdata /= "01000000" then
fail_o <= true;
end if;
 
while int_obf = '0' loop
end loop;
 
-- test IBF=0, OBF=1
if int_ibf_n /= '0' and int_obf /= 'H' then
fail_o <= true;
end if;
--
read_dbbout(a0 => '0');
if rdata /= "01010000" then
fail_o <= true;
end if;
 
-- test IBF=0, OBF=1
if int_ibf_n /= '0' and int_obf /= '0' then
fail_o <= true;
end if;
 
-- send ok to dut
write_dbbin(data => test_master_int_c, a0 => '1');
end;
 
begin
 
fail_o <= false;
305,6 → 355,9
when test_status41a_c =>
status41a_test;
 
when test_master_int_c =>
master_int_test;
 
when others =>
null;
end case;
/t48/trunk/rtl/vhdl/t48_comp_pack-p.vhd
155,6 → 155,10
ibf_int_i : in boolean;
en_dma_i : in boolean;
en_flags_i : in boolean;
mint_ibf_n_o : out std_logic;
mint_obf_o : out std_logic;
drq_o : out std_logic;
dack_n_i : in std_logic;
a0_i : in std_logic;
cs_n_i : in std_logic;
rd_n_i : in std_logic;
/t48/trunk/rtl/vhdl/upi41_core.vhd
165,6 → 165,9
signal bus_en_dma_s : boolean;
signal bus_en_flags_s : boolean;
signal bus_write_sts_s : boolean;
signal bus_mint_ibf_n_s : std_logic;
signal bus_mint_obf_s : std_logic;
signal bus_drq_s : std_logic;
 
-- Clock Controller signals
signal clk_multi_cycle_s : boolean;
206,6 → 209,7
signal p1_data_s : word_t;
 
-- Port 2 signals
signal p2_s : word_t;
signal p2_write_p2_s : boolean;
signal p2_write_exp_s : boolean;
signal p2_read_p2_s : boolean;
394,6 → 398,10
ibf_int_i => bus_ibf_int_s,
en_dma_i => bus_en_dma_s,
en_flags_i => bus_en_flags_s,
mint_ibf_n_o => bus_mint_ibf_n_s,
mint_obf_o => bus_mint_obf_s,
drq_o => bus_drq_s,
dack_n_i => p2_i(7),
a0_i => a0_i,
cs_n_i => cs_n_i,
rd_n_i => rd_n_i,
587,7 → 595,7
output_pch_i => p2_output_pch_s,
pch_i => pmem_addr_s(11 downto 8),
p2_i => p2_i,
p2_o => p2_o,
p2_o => p2_s,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o
);
595,11 → 603,13
 
skip_p2: if include_port2_g = 0 generate
p2_data_s <= (others => bus_idle_level_c);
p2_o <= (others => '0');
p2_s <= (others => '0');
p2l_low_imp_o <= '0';
p2h_low_imp_o <= '0';
end generate;
 
p2_o <= p2_s and '1' & bus_drq_s & bus_mint_ibf_n_s & bus_mint_obf_s & "1111";
 
pmem_ctrl_b : t48_pmem_ctrl
port map (
clk_i => clk_i,
/t48/trunk/rtl/vhdl/upi41_db_bus.vhd
73,6 → 73,10
ibf_int_i : in boolean;
en_dma_i : in boolean;
en_flags_i : in boolean;
mint_ibf_n_o : out std_logic;
mint_obf_o : out std_logic;
drq_o : out std_logic;
dack_n_i : in std_logic;
-- BUS Interface ----------------------------------------------------------
a0_i : in std_logic;
cs_n_i : in std_logic;
106,6 → 110,9
-- the BUS status register
signal sts_q : std_logic_vector(7 downto 4);
 
signal dma_q,
flags_q : boolean;
 
begin
 
-- pragma translate_off
165,6 → 172,8
ibf_q <= '0';
obf_q <= '0';
int_n_o <= '1';
dma_q <= false;
flags_q <= false;
 
elsif clk_i'event and clk_i = clk_active_c then
-- master access
190,6 → 199,15
int_n_o <= '1';
end if;
 
if is_type_a_g = 1 then
if en_dma_i then
dma_q <= true;
end if;
if en_flags_i then
flags_q <= true;
end if;
end if;
 
end if;
 
end if;
214,4 → 232,11
when read_bus_i else
(others => bus_idle_level_c);
 
mint_ibf_n_o <= '1' when flags_q and ibf_q = '0' else '0';
mint_obf_o <= '1' when flags_q and obf_q = '1' else '0';
 
-- TODO
drq_o <= '0' when dma_q else '1';
-- dack_n_i
 
end rtl;
/t48/trunk/sw/verif/black_box/upi41/master_int/no_gen
/t48/trunk/sw/verif/black_box/upi41/master_int/no_t41
/t48/trunk/sw/verif/black_box/upi41/master_int/test.asm
0,0 → 1,83
;; *******************************************************************
;; Test UPI41A master interrupts.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
 
;; signal test start
anl P1, #~004H
 
;; request master interrupt test
mov a, #004H
uout dbb, a
 
;; read input as data
step1: ujnibf step1
jf1 fail
 
uin a, dbb
xrl a, #~004H
jnz fail
 
;; set up master interrupt flags
uen_flags
orl p2, #00110000B
 
;; read input as command
step2: ujnibf step2
jf1 step2_goon
jmp fail
step2_goon:
uin a, dbb
xrl a, #004H
jnz fail
 
;; read turnover byte as data
step3: ujnibf step3
jf1 fail
 
uin a, dbb
xrl a, #0AAH
jnz fail
 
;; disable IBF interrupt
anl p2, #~00100000B
 
;; send step4 indicator
mov a, #040H
uout dbb, a
step4: ujobf step4
 
;; set step5 indicator
mov a, #050H
uout dbb,a
step5: ujobf step5
 
;; read next input as command
done: ujnibf done
jf1 done_goon
jmp done
done_goon:
 
uin a, dbb
xrl a, #004H
jz pass
 
 
fail: FAIL
 
pass: PASS
/t48/trunk/sw/verif/include/upi41_opcodes.inc
19,3 → 19,7
umov MACRO sts, a
db 090H
ENDM
 
uen_flags MACRO
db 0F5H
ENDM

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