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  • This comparison shows the changes necessary to convert path
    /
    from Rev 317 to Rev 318
    Reverse comparison

Rev 317 → Rev 318

/trunk/mp3/bench/verilog/or1200_monitor.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.1 2001/08/20 18:17:52 damjan
// Initial revision
//
178,7 → 181,8
if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
#2;
if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444))
&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444)
&& !(xess_top.i_xess_fpga.risc.cpu.except.except_flushpipe && xess_top.i_xess_fpga.risc.cpu.except.ex_dslot))
display_arch_state;
if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
caught_sys203;

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