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URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

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Rev 32 → Rev 33

/trunk/rtl/verilog/vga_wb_master.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_wb_master.v,v 1.7 2002-02-16 10:40:00 rherveille Exp $
// $Id: vga_wb_master.v,v 1.8 2002-03-04 11:01:59 rherveille Exp $
//
// $Date: 2002-02-16 10:40:00 $
// $Revision: 1.7 $
// $Date: 2002-03-04 11:01:59 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/02/16 10:40:00 rherveille
// Some minor bug-fixes.
// Changed vga_ssel into vga_curproc (cursor processor).
//
// Revision 1.6 2002/02/07 05:42:10 rherveille
// Fixed some bugs discovered by modified testbench
// Removed / Changed some strange logic constructions
59,7 → 63,8
 
module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw,
cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
cursor0_en, cursor0_res, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_o, cc0_dat_i,
cursor1_en, cursor1_res, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_o, cc1_dat_i,
VBAa, VBAb, Thgate, Tvgate,
stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,
clut_req, clut_ack, clut_adr, clut_q);
95,14 → 100,20
input ctrl_vbsw; // enable video bank switching
input ctrl_cbsw; // enable clut bank switching
 
input cursor0_en; // enable hardware cursor0
input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
input [31:11] cursor0_ba; // cursor0 video memory base address
input cursor0_ld; // reload cursor0 from video memory
input cursor1_en; // enable hardware cursor1
input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
input [31:11] cursor1_ba; // cursor1 video memory base address
input cursor1_ld; // reload cursor1 from video memory
input cursor0_en; // enable hardware cursor0
input cursor0_res; // cursor0 resolution
input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
input [31:11] cursor0_ba; // cursor0 video memory base address
input cursor0_ld; // reload cursor0 from video memory
output [ 3: 0] cc0_adr_o; // cursor0 color registers address output
input [15: 0] cc0_dat_i; // cursor0 color registers data input
input cursor1_en; // enable hardware cursor1
input cursor1_res; // cursor1 resolution
input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
input [31:11] cursor1_ba; // cursor1 video memory base address
input cursor1_ld; // reload cursor1 from video memory
output [ 3: 0] cc1_adr_o; // cursor1 color registers address output
input [15: 0] cc1_dat_i; // cursor1 color registers data input
 
// video memory addresses
input [31: 2] VBAa; // video memory base address A
421,6 → 432,7
`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
reg scursor1_ld;
reg scursor1_en;
reg scursor1_res;
reg [31:0] scursor1_xy;
 
always@(posedge clk_i)
439,6 → 451,10
if (scursor1_ld)
scursor1_xy <= #1 cursor1_xy;
 
always@(posedge clk_i)
if (scursor1_ld)
scursor1_res <= #1 cursor1_res;
 
vga_curproc hw_cursor1 (
.clk(clk_i),
.rst_i(sclr),
447,10 → 463,13
.idat(color_proc_q),
.idat_wreq(color_proc_wreq),
.cursor_xy(scursor1_xy),
.cursor_res(scursor1_res),
.cursor_en(scursor1_en),
.cursor_adr(cursor_adr),
.cursor_wadr(cursor_adr),
.cursor_we(cursor1_we),
.cursor_dat(dat_i),
.cursor_wdat(dat_i),
.cc_adr_o(cc1_adr_o),
.cc_dat_i(cc1_dat_i),
.rgb_fifo_wreq(ssel1_wreq),
.rgb(ssel1_q)
);
471,6 → 490,8
assign ssel1_wreq = color_proc_wreq;
assign ssel1_q = color_proc_q;
 
assign cc1_adr_0 = 4'h0;
 
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
wire sddImDoneFifoQ, sdImDoneFifoQ;
 
484,6 → 505,7
`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
reg scursor0_ld;
reg scursor0_en;
reg scursor0_res;
reg [31:0] scursor0_xy;
 
always@(posedge clk_i)
502,6 → 524,10
if (scursor0_ld)
scursor0_xy <= #1 cursor0_xy;
 
always@(posedge clk_i)
if (scursor0_ld)
scursor0_res <= #1 cursor0_res;
 
vga_curproc hw_cursor0 (
.clk(clk_i),
.rst_i(sclr),
511,9 → 537,12
.idat_wreq(ssel1_wreq),
.cursor_xy(scursor0_xy),
.cursor_en(scursor0_en),
.cursor_adr(cursor_adr),
.cursor_res(scursor0_res),
.cursor_wadr(cursor_adr),
.cursor_we(cursor0_we),
.cursor_dat(dat_i),
.cursor_wdat(dat_i),
.cc_adr_o(cc0_adr_o),
.cc_dat_i(cc0_dat_i),
.rgb_fifo_wreq(rgb_fifo_wreq),
.rgb(rgb_fifo_d)
);
520,10 → 549,16
`else // Hardware Cursor0 disabled, generate pass-through signals
assign rgb_fifo_wreq = ssel1_wreq;
assign rgb_fifo_d = ssel1_q;
 
assign cc0_adr_o = 4'h0;
`endif
 
// hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain)
vga_fifo #(3, 24) rgb_fifo (
// hookup RGB buffer (temporary station between WISHBONE-clock-domain
// and pixel-clock-domain)
// The cursor_processor pipelines introduce a delay between the color
// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
// for this we double the rgb_fifo.
vga_fifo #(4, 24) rgb_fifo (
.clk(clk_i),
.aclr(1'b1),
.sclr(sclr),
542,5 → 577,3
endmodule
 
 
 
 
/trunk/rtl/verilog/vga_enh_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_enh_top.v,v 1.1 2002-02-07 05:42:10 rherveille Exp $
// $Id: vga_enh_top.v,v 1.2 2002-03-04 11:01:59 rherveille Exp $
//
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.1 $
// $Date: 2002-03-04 11:01:59 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/07 05:42:10 rherveille
// Fixed some bugs discovered by modified testbench
// Removed / Changed some strange logic constructions
// Started work on hardware cursor support (not finished yet)
// Changed top-level name to vga_enh_top.v
//
 
`include "timescale.v"
`include "vga_defines.v"
123,10 → 129,13
wire cursor0_en, cursor1_en;
wire [31:11] cursor0_ba, cursor1_ba;
wire cursor0_ld, cursor1_ld;
wire cursor0_res, cursor1_res;
wire [15: 0] cc0_dat_o, cc1_dat_o;
 
// to wb_slave
wire stat_avmp, stat_acmp, vmem_swint, clut_swint, hint, vint, sint;
reg luint;
wire [ 3: 0] cc0_adr_i, cc1_adr_i;
 
// from pixel generator
wire cgate; // composite gate signal
150,41 → 159,47
// hookup wishbone slave
vga_wb_slave u1 (
// wishbone interface
.CLK_I(wb_clk_i),
.RST_I(wb_rst_i),
.nRESET(arst),
.ADR_I(wbs_adr_i[11:2]),
.DAT_I(wbs_dat_i),
.DAT_O(wbs_dat_o),
.SEL_I(wbs_sel_i),
.WE_I(wbs_we_i),
.STB_I(wbs_stb_i),
.CYC_I(wbs_cyc_i),
.ACK_O(wbs_ack_o),
.ERR_O(wbs_err_o),
.INTA_O(wb_inta_o),
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.arst_i(arst),
.adr_i(wbs_adr_i[11:2]),
.dat_i(wbs_dat_i),
.dat_o(wbs_dat_o),
.sel_i(wbs_sel_i),
.we_i(wbs_we_i),
.stb_i(wbs_stb_i),
.cyc_i(wbs_cyc_i),
.ack_o(wbs_ack_o),
.err_o(wbs_err_o),
.inta_o(wb_inta_o),
 
// internal connections
.bl(ctrl_bl),
.csl(ctrl_csl),
.vsl(ctrl_vsl),
.hsl(ctrl_hsl),
.pc(ctrl_pc),
.cd(ctrl_cd),
.vbl(ctrl_vbl),
.cbsw(ctrl_cbsw),
.vbsw(ctrl_vbsw),
.ven(ctrl_ven),
.acmp(stat_acmp),
.avmp(stat_avmp),
.bl(ctrl_bl), // blank polarization level
.csl(ctrl_csl), // csync polarization level
.vsl(ctrl_vsl), // vsync polarization level
.hsl(ctrl_hsl), // hsync polarization level
.pc(ctrl_pc), // pseudo-color mode (only for 8bpp)
.cd(ctrl_cd), // color depth
.vbl(ctrl_vbl), // video memory burst length
.cbsw(ctrl_cbsw), // color lookup table bank switch enable
.vbsw(ctrl_vbsw), // video bank switch enable
.ven(ctrl_ven), // video enable
.acmp(stat_acmp), // active color lookup table page
.avmp(stat_avmp), // active video memory page
.cursor0_res(cursor0_res), // cursor0 resolution
.cursor0_en(cursor0_en), // cursor0 enable
.cursor0_xy(cursor0_xy), // cursor0 (x,y)
.cursor0_ba(cursor0_ba), // curso0 video memory base address
.cursor0_ld(cursor0_ld), // reload curso0 from video memory
.cc0_adr_i(cc0_adr_i), // cursor0 color registers address
.cc0_dat_o(cc0_dat_o), // cursor0 color registers data
.cursor1_res(cursor1_res), // cursor1 resolution
.cursor1_en(cursor1_en), // cursor1 enable
.cursor1_xy(cursor1_xy), // cursor1 (x,y)
.cursor1_ba(cursor1_ba), // cursor1 video memory base address
.cursor1_ld(cursor1_ld), // reload cursor1 from video memory
.cc1_adr_i(cc1_adr_i), // cursor1 color registers address
.cc1_dat_o(cc1_dat_o), // cursor1 color registers data
.vbsint_in(vmem_swint), // video memory bank switch interrupt
.cbsint_in(clut_swint), // clut memory bank switch interrupt
.hint_in(hint), // horizontal interrupt
231,13 → 246,19
.ctrl_cbsw(ctrl_cbsw),
.ctrl_vbsw(ctrl_vbsw),
.cursor0_en(cursor0_en), // cursor0 enable
.cursor0_res(cursor0_res), // cursor0 resolution
.cursor0_xy(cursor0_xy), // cursor0 (x,y)
.cursor0_ba(cursor0_ba), // curso0 video memory base address
.cursor0_ld(cursor0_ld), // reload curso0 from video memory
.cc0_adr_o(cc0_adr_i), // cursor0 color registers address
.cc0_dat_i(cc0_dat_o), // cursor0 color registers data
.cursor1_en(cursor1_en), // cursor1 enable
.cursor1_res(cursor1_res), // cursor1 resolution
.cursor1_xy(cursor1_xy), // cursor1 (x,y)
.cursor1_ba(cursor1_ba), // cursor1 video memory base address
.cursor1_ld(cursor1_ld), // reload cursor1 from video memory
.cc1_adr_o(cc1_adr_i), // cursor1 color registers address
.cc1_dat_i(cc1_dat_o), // cursor1 color registers data
.VBAa(VBARa),
.VBAb(VBARb),
.Thgate(Thgate),
364,3 → 385,8
end
 
endmodule
 
 
 
 
 
/trunk/rtl/verilog/vga_colproc.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_colproc.v,v 1.6 2002-02-07 05:42:10 rherveille Exp $
// $Id: vga_colproc.v,v 1.7 2002-03-04 11:01:59 rherveille Exp $
//
// $Date: 2002-02-07 05:42:10 $
// $Revision: 1.6 $
// $Date: 2002-03-04 11:01:59 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/02/07 05:42:10 rherveille
// Fixed some bugs discovered by modified testbench
// Removed / Changed some strange logic constructions
// Started work on hardware cursor support (not finished yet)
// Changed top-level name to vga_enh_top.v
//
 
`include "timescale.v"
 
61,13 → 67,13
input clk; // master clock
input srst; // synchronous reset
 
input [31:0] vdat_buffer_di; // video memory data input
input [31:0] vdat_buffer_di; // video memory data input
 
input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
 
input vdat_buffer_empty;
output vdat_buffer_rreq; // pixel buffer read request
output vdat_buffer_rreq; // pixel buffer read request
reg vdat_buffer_rreq;
 
input rgb_fifo_full;
160,13 → 166,21
nxt_state = idle;
 
col_8bpp:
// do NOT check for rgb_fifo_full here, because in 8bpp_pc mode
// the color-processor always finishes the current 4pixel-block
// i.e. it runs until colcnt = '11'
// Do NOT check for rgb_fifo_full here.
// In 8bpp pseudo-color mode the color-processor must always finish
// the current 4pixel-block(i.e. it runs until colcnt = '11').
// This is because of the late clut-response which shuffles all
// signals the state-machine depends on.
// Because of this we can not do an early video_memory_data fetch,
// i.e. we can not jump to the fill_buf state. Instead we always
// jump to idle and check for rgb_fifo_full there.
//
// The addition of the cursor-processors forces us to increase the
// rgb-fifo size. The increased rgb-fifo also handles the above
// described problem. Thus erradicating the above comment.
// We add the early video_memory_data fetch again.
if (!(|colcnt))
if (!vdat_buffer_empty)
if (!vdat_buffer_empty && !rgb_fifo_full)
nxt_state = fill_buf;
else
nxt_state = idle;
308,13 → 322,21
 
col_8bpp:
begin
// do NOT check for rgb_fifo_full here, because in 8bpp_pc mode
// the color-processor always finishes the current 4pixel-block
// i.e. it runs until colcnt = '11'.
// Do NOT check for rgb_fifo_full here.
// In 8bpp pseudo-color mode the color-processor must always finish
// the current 4pixel-block(i.e. it runs until colcnt = '11').
// This is because of the late clut-response which shuffles all
// signals the state-machine depends on.
// Because of this we can not do an early video_memory_data fetch,
// i.e. we can not jump to the fill_buf state. Instead we always
// jump to idle and check for rgb_fifo_full there.
//
// The addition of the cursor-processors forces us to increase the
// rgb-fifo size. The increased rgb-fifo also handles the above
// described problem. Thus erradicating the above comment.
// We add the early video_memory_data fetch again.
if (!(|colcnt))
if (!vdat_buffer_empty && !(|colcnt) )
if (!vdat_buffer_empty && !rgb_fifo_full)
ivdat_buf_rreq = 1'b1;
 
RGBbuf_wreq = clut_ack;
475,16 → 497,3
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/vga_wb_slave.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_wb_slave.v,v 1.7 2002-02-25 06:13:44 rherveille Exp $
// $Id: vga_wb_slave.v,v 1.8 2002-03-04 11:01:59 rherveille Exp $
//
// $Date: 2002-02-25 06:13:44 $
// $Revision: 1.7 $
// $Date: 2002-03-04 11:01:59 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/02/25 06:13:44 rherveille
// Fixed dat_o incomplete sensitivity list.
//
// Revision 1.6 2002/02/07 05:42:10 rherveille
// Fixed some bugs discovered by modified testbench
// Removed / Changed some strange logic constructions
58,9 → 61,10
`include "timescale.v"
`include "vga_defines.v"
 
module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
module vga_wb_slave(clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, err_o, inta_o,
bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld,
cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o,
cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o,
vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
 
69,23 → 73,23
//
 
// wishbone slave interface
input CLK_I;
input RST_I;
input nRESET;
input [11:2] ADR_I;
input [31:0] DAT_I;
output [31:0] DAT_O;
reg [31:0] DAT_O;
input [ 3:0] SEL_I;
input WE_I;
input STB_I;
input CYC_I;
output ACK_O;
reg ACK_O;
output ERR_O;
reg ERR_O;
output INTA_O;
reg INTA_O;
input clk_i;
input rst_i;
input arst_i;
input [11:2] adr_i;
input [31:0] dat_i;
output [31:0] dat_o;
reg [31:0] dat_o;
input [ 3:0] sel_i;
input we_i;
input stb_i;
input cyc_i;
output ack_o;
reg ack_o;
output err_o;
reg err_o;
output inta_o;
reg inta_o;
 
// control register settings
output bl; // blanking level
100,14 → 104,20
output ven; // video system enable
 
// hardware cursor settings
output cursor0_en;
output [31: 0] cursor0_xy;
output cursor0_res; // cursor0 resolution
output cursor0_en; // cursor0 enable
output [31: 0] cursor0_xy; // cursor0 location
output [31:11] cursor0_ba; // cursor0 base address
output cursor0_ld; // reload cursor0 from video memory
output cursor1_en;
output [31: 0] cursor1_xy;
input [ 3: 0] cc0_adr_i; // cursor0 color register address
output [15: 0] cc0_dat_o; // cursor0 color register data
output cursor1_res; // cursor1 resolution
output cursor1_en; // cursor1 enable
output [31: 0] cursor1_xy; // cursor1 location
output [31:11] cursor1_ba; // cursor1 base address
output cursor1_ld; // reload cursor1 from video memory
input [ 3: 0] cc1_adr_i; // cursor1 color register address
output [15: 0] cc1_dat_o; // cursor1 color register data
 
reg [31: 0] cursor0_xy;
reg [31:11] cursor0_ba;
153,22 → 163,24
//
// variable declarations
//
parameter REG_ADR_HIBIT = 3;
parameter REG_ADR_HIBIT = 7;
 
wire [REG_ADR_HIBIT:0] REG_ADR = ADR_I[REG_ADR_HIBIT +2 : 2];
wire CLUT_ADR = ADR_I[11];
wire [REG_ADR_HIBIT:0] REG_ADR = adr_i[REG_ADR_HIBIT : 2];
wire CLUT_ADR = adr_i[11];
 
parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 4'b0000;
parameter [REG_ADR_HIBIT : 0] STAT_ADR = 4'b0001;
parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 4'b0010;
parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 4'b0011;
parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 4'b0100;
parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 4'b0101;
parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 4'b0110;
parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 4'b1000;
parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 4'b1001;
parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 4'b1010;
parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 4'b1011;
parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 6'b00_0000;
parameter [REG_ADR_HIBIT : 0] STAT_ADR = 6'b00_0001;
parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 6'b00_0010;
parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 6'b00_0011;
parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 6'b00_0100;
parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 6'b00_0101;
parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 6'b00_0110;
parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 6'b00_1100;
parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 6'b00_1101;
parameter [REG_ADR_HIBIT : 0] CCR0_ADR = 6'b01_0???;
parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 6'b01_1100;
parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 6'b01_1101;
parameter [REG_ADR_HIBIT : 0] CCR1_ADR = 6'b10_0???;
 
 
reg [31:0] ctrl, stat, htim, vtim, hvlen;
175,6 → 187,8
wire hint, vint, vbsint, cbsint, luint, sint;
wire hie, vie, vbsie, cbsie;
wire acc, acc32, reg_acc, reg_wacc;
wire cc0_acc, cc1_acc;
wire [31:0] ccr0_dat_o, ccr1_dat_o;
 
 
reg [31:0] reg_dato; // data output from registers
183,23 → 197,26
// Module body
//
 
assign acc = CYC_I & STB_I;
assign acc32 = (SEL_I == 4'b1111);
assign acc = cyc_i & stb_i;
assign acc32 = (sel_i == 4'b1111);
assign clut_acc = CLUT_ADR & acc & acc32;
assign reg_acc = !CLUT_ADR & acc & acc32;
assign reg_wacc = reg_acc & WE_I;
assign reg_wacc = reg_acc & we_i;
 
always@(posedge CLK_I)
ACK_O <= #1 ((reg_acc & acc32) | clut_ack) & !ACK_O;
assign cc0_acc = CCR0_ADR & acc & acc32;
assign cc1_acc = CCR1_ADR & acc & acc32;
 
always@(posedge CLK_I)
ERR_O <= #1 acc & !acc32;
always@(posedge clk_i)
ack_o <= #1 ((reg_acc & acc32) | clut_ack) & !ack_o;
 
always@(posedge clk_i)
err_o <= #1 acc & !acc32 & !err_o;
 
 
// generate registers
always@(posedge CLK_I or negedge nRESET)
always@(posedge clk_i or negedge arst_i)
begin : gen_regs
if(!nRESET)
if(!arst_i)
begin
htim <= #1 0;
vtim <= #1 0;
211,7 → 228,7
cursor1_xy <= #1 0;
cursor1_ba <= #1 0;
end
else if (RST_I)
else if (rst_i)
begin
htim <= #1 0;
vtim <= #1 0;
224,33 → 241,33
cursor1_ba <= #1 0;
end
else if (reg_wacc)
case (ADR_I) // synopsis full_case parallel_case
HTIM_ADR : htim <= #1 DAT_I;
VTIM_ADR : vtim <= #1 DAT_I;
HVLEN_ADR : hvlen <= #1 DAT_I;
VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
C0XY_ADR : cursor0_xy <= #1 DAT_I[31: 0];
C0BAR_ADR : cursor0_ba <= #1 DAT_I[31:11];
C1XY_ADR : cursor1_xy <= #1 DAT_I[31: 0];
C1BAR_ADR : cursor1_ba <= #1 DAT_I[31:11];
case (adr_i) // synopsis full_case parallel_case
HTIM_ADR : htim <= #1 dat_i;
VTIM_ADR : vtim <= #1 dat_i;
HVLEN_ADR : hvlen <= #1 dat_i;
VBARA_ADR : VBARa <= #1 dat_i[31: 2];
VBARB_ADR : VBARb <= #1 dat_i[31: 2];
C0XY_ADR : cursor0_xy <= #1 dat_i[31: 0];
C0BAR_ADR : cursor0_ba <= #1 dat_i[31:11];
C1XY_ADR : cursor1_xy <= #1 dat_i[31: 0];
C1BAR_ADR : cursor1_ba <= #1 dat_i[31:11];
endcase
end
 
always@(posedge CLK_I)
always@(posedge clk_i)
begin
cursor0_ld <= #1 reg_wacc && (ADR_I == C0BAR_ADR);
cursor1_ld <= #1 reg_wacc && (ADR_I == C1BAR_ADR);
cursor0_ld <= #1 reg_wacc && (adr_i == C0BAR_ADR);
cursor1_ld <= #1 reg_wacc && (adr_i == C1BAR_ADR);
end
 
// generate control register
always@(posedge CLK_I or negedge nRESET)
if (!nRESET)
always@(posedge clk_i or negedge arst_i)
if (!arst_i)
ctrl <= #1 0;
else if (RST_I)
else if (rst_i)
ctrl <= #1 0;
else if (reg_wacc & (REG_ADR == CTRL_ADR) )
ctrl <= #1 DAT_I;
ctrl <= #1 dat_i;
else
begin
ctrl[6] <= #1 ctrl[6] & !cbsint_in;
259,10 → 276,10
 
 
// generate status register
always@(posedge CLK_I or negedge nRESET)
if (!nRESET)
always@(posedge clk_i or negedge arst_i)
if (!arst_i)
stat <= #1 0;
else if (RST_I)
else if (rst_i)
stat <= #1 0;
else
begin
282,12 → 299,12
 
if (reg_wacc & (REG_ADR == STAT_ADR) )
begin
stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
stat[5] <= #1 hint_in | (stat[5] & !DAT_I[5]);
stat[4] <= #1 vint_in | (stat[4] & !DAT_I[4]);
stat[1] <= #1 luint_in | (stat[3] & !DAT_I[1]);
stat[0] <= #1 sint_in | (stat[0] & !DAT_I[0]);
stat[7] <= #1 cbsint_in | (stat[7] & !dat_i[7]);
stat[6] <= #1 vbsint_in | (stat[6] & !dat_i[6]);
stat[5] <= #1 hint_in | (stat[5] & !dat_i[5]);
stat[4] <= #1 vint_in | (stat[4] & !dat_i[4]);
stat[1] <= #1 luint_in | (stat[3] & !dat_i[1]);
stat[0] <= #1 sint_in | (stat[0] & !dat_i[0]);
end
else
begin
302,22 → 319,24
 
 
// decode control register
assign cursor1_en = ctrl[21];
assign cursor0_en = ctrl[20];
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[6];
assign vbsw = ctrl[5];
assign cbsie = ctrl[4];
assign vbsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
assign cursor1_res = ctrl[25];
assign cursor1_en = ctrl[24];
assign cursor0_res = ctrl[23];
assign cursor0_en = ctrl[20];
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[6];
assign vbsw = ctrl[5];
assign cbsie = ctrl[4];
assign vbsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
 
// decode status register
assign cbsint = stat[7];
339,11 → 358,50
assign Tvgate = vtim[15:0];
assign Tvlen = hvlen[15:0];
 
 
`ifdef VGA_HWC0
// hookup cursor0 color registers
vga_cur_cregs cregs0(
.clk_i(clk_i),
.rst_i(rst_i),
.arst_i(arst_i),
.hsel_i(cc0_acc),
.hadr_i(adr_i[4:2]),
.hwe_i(we_i),
.hdat_i(dat_i),
.hdat_o(ccr0_dat_o), // host access
.hack_o(),
.cadr_i(cc0_adr_i),
.cdat_o(cc0_dat_o) // cursor processor access
);
`else
assign ccr0_dat_0 = 32'h0;
`endif
 
`ifdef VGA_HWC1
// hookup cursor1 color registers
vga_cur_cregs cregs1(
.clk_i(clk_i),
.rst_i(rst_i),
.arst_i(arst_i),
.hsel_i(cc1_acc),
.hadr_i(adr_i[4:2]),
.hwe_i(we_i),
.hdat_i(dat_i),
.hdat_o(ccr1_dat_o), // host access
.hack_o(),
.cadr_i(cc1_adr_i),
.cdat_o(cc1_dat_o) // cursor processor access
);
`else
assign ccr1_dat_o = 32'h0;
`endif
 
// assign output
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba)
case (REG_ADR) // synopsis full_case parallel_case
casez (REG_ADR) // synopsis full_case parallel_case
CTRL_ADR : reg_dato = ctrl;
STAT_ADR : reg_dato = stat;
HTIM_ADR : reg_dato = htim;
353,17 → 411,19
VBARB_ADR : reg_dato = {VBARb, 2'b0};
C0XY_ADR : reg_dato = cursor0_xy;
C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
CCR0_ADR : reg_dato = ccr0_dat_o;
C1XY_ADR : reg_dato = cursor1_xy;
C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
CCR1_ADR : reg_dato = ccr1_dat_o;
default : reg_dato = 32'h0000_0000;
endcase
 
always@(posedge CLK_I)
DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
always@(posedge clk_i)
dat_o <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
 
// generate interrupt request signal
always@(posedge CLK_I)
INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
always@(posedge clk_i)
inta_o <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
endmodule
 
 
/trunk/rtl/verilog/vga_cur_cregs.v
0,0 → 1,127
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core ////
//// Hardware Cursor Color Registers ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: vga_cur_cregs.v,v 1.1 2002-03-04 11:01:59 rherveille Exp $
//
// $Date: 2002-03-04 11:01:59 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
 
`include "timescale.v"
 
module vga_cur_cregs (
clk_i, rst_i, arst_i,
hsel_i, hadr_i, hwe_i, hdat_i, hdat_o, hack_o,
cadr_i, cdat_o
);
 
//
// inputs & outputs
//
 
// wishbone signals
input clk_i; // master clock input
input rst_i; // synchronous active high reset
input arst_i; // asynchronous active low reset
 
// host interface
input hsel_i; // host select input
input [ 2:0] hadr_i; // host address input
input hwe_i; // host write enable input
input [31:0] hdat_i; // host data in
output [31:0] hdat_o; // host data out
output hack_o; // host acknowledge out
 
reg [31:0] hdat_o;
reg hack_o;
// cursor processor interface
input [ 3:0] cadr_i; // cursor address in
output [15:0] cdat_o; // cursor data out
 
reg [15:0] cdat_o;
 
 
//
// variable declarations
//
reg [31:0] cregs [2:0]; // color registers
wire [31:0] temp_cdat;
 
//
// module body
//
 
 
////////////////////////////
// generate host interface
 
// write section
always@(posedge clk_i or negedge arst_i)
if (~arst_i)
if (hsel_i & hwe_i)
cregs[hadr_i] <= #1 hdat_i;
 
// read section
always@(posedge clk_i)
hdat_o <= #1 cregs[hadr_i];
 
// acknowledge section
always@(posedge clk_i)
hack_o <= #1 hsel_i & !hack_o;
 
 
//////////////////////////////
// generate cursor interface
 
// read section
assign temp_cdat = cregs[cadr_i[3:1]];
 
always@(posedge clk_i)
cdat_o <= #1 cadr_i[0] ? temp_cdat[31:16] : temp_cdat[15:0];
 
endmodule
 
/trunk/rtl/verilog/vga_curproc.v
37,10 → 37,10
 
// CVS Log
//
// $Id: vga_curproc.v,v 1.1 2002-02-16 10:40:00 rherveille Exp $
// $Id: vga_curproc.v,v 1.2 2002-03-04 11:01:59 rherveille Exp $
//
// $Date: 2002-02-16 10:40:00 $
// $Revision: 1.1 $
// $Date: 2002-03-04 11:01:59 $
// $Revision: 1.2 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/16 10:40:00 rherveille
// Some minor bug-fixes.
// Changed vga_ssel into vga_curproc (cursor processor).
//
// Revision 1.1 2002/02/07 05:42:10 rherveille
// Fixed some bugs discovered by modified testbench
// Removed / Changed some strange logic constructions
57,7 → 61,9
`include "timescale.v"
 
module vga_curproc (clk, rst_i, Thgate, Tvgate, idat, idat_wreq,
cursor_xy, cursor_en, cursor_adr, cursor_dat, cursor_we,
cursor_xy, cursor_en, cursor_res,
cursor_wadr, cursor_wdat, cursor_we,
cc_adr_o, cc_dat_i,
rgb_fifo_wreq, rgb);
 
//
77,10 → 83,16
// cursor data
input [31:0] cursor_xy; // cursor (x,y)
input cursor_en; // cursor enable (on/off)
input [ 8:0] cursor_adr; // cursor address
input [31:0] cursor_dat; // cursor data
input cursor_we; // write enable
input cursor_res; // cursor resolution (32x32 or 64x64 pixels)
input [ 8:0] cursor_wadr; // cursor buffer write address
input [31:0] cursor_wdat; // cursor buffer write data
input cursor_we; // cursor buffer write enable
 
// color registers interface
output [ 3:0] cc_adr_o; // cursor color registers address
reg [ 3:0] cc_adr_o;
input [15:0] cc_dat_i; // cursor color registers data
 
// rgb-fifo connections
output rgb_fifo_wreq; // rgb-out write request
reg rgb_fifo_wreq;
90,24 → 102,32
//
// variable declarations
//
reg dcursor_en;
reg dcursor_en, ddcursor_en, dddcursor_en;
reg [15:0] xcnt, ycnt;
wire xdone, ydone;
wire [15:0] cursor_x, cursor_y;
wire cursor_transparent;
reg alpha, dalpha;
wire cursor_alpha;
reg [ 4:0] r, g, b, dr, dg, db;
wire [ 7:0] cursor_r, cursor_g, cursor_b;
reg inbox_x, inbox_y;
wire inbox;
reg [23:0] didat;
reg store_one;
wire [31:0] cmem_q;
reg [ 9:0] cmem_ra;
wire [ 8:0] cmem_a;
reg dinbox, ddinbox, dddinbox;
 
reg [23:0] didat, ddidat, dddidat;
reg didat_wreq, ddidat_wreq;
wire [31:0] cbuf_q;
reg [11:0] cbuf_ra;
reg [ 2:0] dcbuf_ra;
wire [ 8:0] cbuf_a;
 
reg store1, store2;
 
//
// module body
//
 
//
// generate x-y counters
always@(posedge clk)
if(rst_i || xdone)
123,7 → 143,7
else if (xdone)
ycnt <= #1 ycnt + 16'h1;
 
assign ydone = (ycnt == Tvgate) && idat_wreq;
assign ydone = (ycnt == Tvgate) && xdone;
 
 
// decode cursor (x,y)
130,77 → 150,151
assign cursor_x = cursor_xy[15: 0];
assign cursor_y = cursor_xy[31:16];
 
 
//
// generate inbox signals
always@(posedge clk)
begin
inbox_x <= #1 (xcnt >= cursor_x) && (xcnt < (cursor_x +16'h1f) );
inbox_y <= #1 (ycnt >= cursor_y) && (ycnt < (cursor_y +16'h1f) );
inbox_x <= #1 (xcnt >= cursor_x) && (xcnt < (cursor_x + (cursor_res ? 16'h7f : 16'h1f) ));
inbox_y <= #1 (ycnt >= cursor_y) && (ycnt < (cursor_y + (cursor_res ? 16'h7f : 16'h1f) ));
end
 
assign inbox = inbox_x && inbox_y;
 
always@(posedge clk)
dinbox <= #1 inbox;
 
always@(posedge clk)
if (didat_wreq)
ddinbox <= #1 dinbox;
 
always@(posedge clk)
dddinbox <= #1 ddinbox;
 
//
// generate cursor buffer address counter
always@(posedge clk)
if (!cursor_en || ydone)
cbuf_ra <= #1 12'h0;
else if (inbox && idat_wreq)
cbuf_ra <= #1 cbuf_ra +12'h1;
 
always@(posedge clk)
dcbuf_ra <= #1 cbuf_ra[2:0];
 
assign cbuf_a = cursor_we ? cursor_wadr : cursor_res ? cbuf_ra[11:3] : cbuf_ra[9:1];
 
// hookup local cursor memory (generic synchronous single port memory)
// cursor memory should never be written to/read from at the same time
generic_spram #(9, 32) cmem(
generic_spram #(9, 32) cbuf(
.clk(clk),
.rst(1'b0), // no reset
.ce(1'b1), // always enable memory
.we(cursor_we),
.oe(1'b1), // always output data
.addr(cmem_a),
.di(cursor_dat),
.do(cmem_q)
.addr(cbuf_a),
.di(cursor_wdat),
.do(cbuf_q)
);
 
assign cmem_a = cursor_we ? cursor_adr : cmem_ra[9:1];
//
// decode cursor data for 32x32x16bpp mode
always@(posedge clk)
if (didat_wreq)
begin
alpha <= #1 dcbuf_ra[0] ? cbuf_q[31] : cbuf_q[15];
r <= #1 dcbuf_ra[0] ? cbuf_q[30:26] : cbuf_q[14:10];
g <= #1 dcbuf_ra[0] ? cbuf_q[25:21] : cbuf_q[ 9: 5];
b <= #1 dcbuf_ra[0] ? cbuf_q[20:16] : cbuf_q[ 4: 0];
end
 
always@(posedge clk)
begin
dalpha <= #1 alpha;
dr <= #1 r;
dg <= #1 g;
db <= #1 b;
end
 
// decode cursor data
assign cursor_transparent = cmem_ra[0] ? cmem_q[31] : cmem_q[15];
assign cursor_r = cmem_ra[0] ? {cmem_q[30:26], 3'h0} : {cmem_q[14:10], 3'h0};
assign cursor_g = cmem_ra[0] ? {cmem_q[25:21], 3'h0} : {cmem_q[ 9: 5], 3'h0};
assign cursor_b = cmem_ra[0] ? {cmem_q[20:16], 3'h0} : {cmem_q[ 4: 0], 3'h0};
//
// decode cursor data for 64x64x4bpp mode
 
// generate cursor-color address
always@(posedge clk)
if (didat_wreq)
case (dcbuf_ra)
3'b000: cc_adr_o <= cbuf_q[ 3: 0];
3'b001: cc_adr_o <= cbuf_q[ 7: 4];
3'b010: cc_adr_o <= cbuf_q[11: 8];
3'b011: cc_adr_o <= cbuf_q[15:12];
3'b100: cc_adr_o <= cbuf_q[19:16];
3'b101: cc_adr_o <= cbuf_q[23:20];
3'b110: cc_adr_o <= cbuf_q[27:24];
3'b111: cc_adr_o <= cbuf_q[31:28];
endcase
 
//
// generate cursor colors
assign cursor_alpha = cursor_res ? cc_dat_i[15] : dalpha;
assign cursor_r = {cursor_res ? cc_dat_i[14:10] : dr, 3'h0};
assign cursor_g = {cursor_res ? cc_dat_i[ 9: 5] : dg, 3'h0};
assign cursor_b = {cursor_res ? cc_dat_i[ 4: 0] : db, 3'h0};
 
 
//
// delay image data
always@(posedge clk)
if (idat_wreq)
didat <= #1 idat;
didat <= #1 idat;
 
always@(posedge clk)
if (didat_wreq)
ddidat <= #1 didat;
 
always@(posedge clk)
dddidat <= #1 ddidat;
 
always@(posedge clk)
begin
didat_wreq <= #1 idat_wreq;
ddidat_wreq <= #1 didat_wreq;
end
 
//
// generate selection unit
always@(posedge clk)
dcursor_en <= #1 cursor_en;
 
always@(posedge clk)
if (idat_wreq)
if (!dcursor_en || !inbox)
rgb <= #1 didat;
else if (cursor_transparent)
rgb <= #1 didat;
else
rgb <= #1 {cursor_r, cursor_g, cursor_b};
if (didat_wreq)
ddcursor_en <= #1 dcursor_en;
 
always@(posedge clk)
dddcursor_en <= #1 ddcursor_en;
 
always@(posedge clk)
if (ddidat_wreq)
if (!dddcursor_en || !dddinbox)
rgb <= #1 dddidat;
else if (cursor_alpha)
rgb <= #1 dddidat;
else
rgb <= #1 {cursor_r, cursor_g, cursor_b};
 
//
// generate write request signal
always@(posedge clk)
if (rst_i)
store_one <= #1 1'b0;
else if (idat_wreq)
store_one <= #1 1'b1;
begin
store1 <= #1 1'b0;
store2 <= #1 1'b0;
end
else
begin
store1 <= #1 didat_wreq | store1;
store2 <= #1 (didat_wreq & store1) | store2;
end
 
// skip 2 idat_wreq signal, to keep in pace with rgb_fifo_full signal
always@(posedge clk)
rgb_fifo_wreq <= #1 idat_wreq & store_one;
rgb_fifo_wreq <= #1 ddidat_wreq & store2;
 
 
// generate cursor address counter
always@(posedge clk)
if (!cursor_en || ydone)
cmem_ra <= #1 10'h0;
else if (inbox && idat_wreq)
cmem_ra <= #1 cmem_ra +10'h1;
 
endmodule
 

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