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trunk/sim/rtl_sim/bin/Makefile Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/syn/bin/comp.dc =================================================================== --- trunk/syn/bin/comp.dc (revision 32) +++ trunk/syn/bin/comp.dc (nonexistent) @@ -1,120 +0,0 @@ -############################################################################### -# -# Actual Synthesis Script -# -# This script does the actual synthesis -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_cmp.log" -append pre_comp_db_file ../out/$design_name "_pre.db" -append post_comp_db_file ../out/$design_name ".db" -append post_syn_verilog_file ../out/$design_name "_ps.v" -set junk_file /dev/null - -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Reading Design ..." >> $log_file -read_file $pre_comp_db_file >> $log_file - -# ============================================== -# Operating conditions - -echo "+++++++++ Setting up Operation Conditions ..." >> $log_file -current_design $design_name -set_operating_conditions WORST >> $log_file - -# Turn off automatic wire load selection, as this -# always (WHY ???) defaults to "zero_load" -#set auto_wire_load_selection false -#set_wire_load_mode enclosed >> $log_file -#set_wire_load_mode top >> $log_file -#set_wire_load_model -name suggested_40K >> $log_file - -# ============================================== -# Setup Clocks and Resets - -echo "+++++++++ Setting up Clocks ..." >> $log_file - -set_drive 0 [find port {*clk*}] - -# !!! WISHBONE Clock !!! -set clock_period 5 -create_clock -period $clock_period wb_clk_i -set_clock_skew -uncertainty 0.1 wb_clk_i -set_clock_transition 0.5 wb_clk_i -set_dont_touch_network wb_clk_i - -# !!! Reset !!! -set_drive 0 [find port {*rst*}] -set_dont_touch_network [find port {*rst*}] - -# ============================================== -# Setup IOs - -echo "+++++++++ Setting up IOs ..." >> $log_file - -set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file -set_load 0.2 [all_outputs] - -set_input_delay -max 1 -clock wb_clk_i [all_inputs] -set_output_delay -max 1 -clock wb_clk_i [all_outputs] - -# ============================================== -# Setup Area Constrains -set_max_area 0.0 - -# ============================================== -# Force Ultra -set_ultra_optimization -f - -# ============================================== -# Compile Design - -echo "+++++++++ Starting Compile ..." >> $log_file -compile -map_effort medium -area_effort medium -ungroup_all >> $log_file -#compile -map_effort low -area_effort low >> $log_file -#compile -map_effort high -area_effort high -ungroup_all >> $log_file -#compile -map_effort high -area_effort high -auto_ungroup >> $log_file - -# ============================================== -# Write Out the optimized design - -echo "+++++++++ Saving Optimized Design ..." >> $log_file -write_file -format verilog -output $post_syn_verilog_file -write_file -hierarchy -format db -output $post_comp_db_file - -# ============================================== -# Create Some Basic Reports - -echo "+++++++++ Reporting Final Results ..." >> $log_file -report_timing -nworst 10 >> $log_file -report_area >> $log_file - - Index: trunk/syn/bin/lib_spec.dc =================================================================== --- trunk/syn/bin/lib_spec.dc (revision 32) +++ trunk/syn/bin/lib_spec.dc (nonexistent) @@ -1,36 +0,0 @@ -############################################################################### -# -# Library Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Libraries - -set search_path [list $search_path . \ - /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ - $hdl_src_dir] - -set snps [getenv "SYNOPSYS"] - -set synthetic_library "" -append synthetic_library $snps "/libraries/syn/dw01.sldb " -append synthetic_library $snps "/libraries/syn/dw02.sldb " -append synthetic_library $snps "/libraries/syn/dw03.sldb " -append synthetic_library $snps "/libraries/syn/dw04.sldb " -append synthetic_library $snps "/libraries/syn/dw05.sldb " -append synthetic_library $snps "/libraries/syn/dw06.sldb " -append synthetic_library $snps "/libraries/syn/dw07.sldb " - -set target_library { umcl18u250t2_typ.db } -set link_library "" -append link_library $target_library " " $synthetic_library -set symbol_library { umcl18u250t2.sdb } - Index: trunk/syn/bin/design_spec.dc =================================================================== --- trunk/syn/bin/design_spec.dc (revision 32) +++ trunk/syn/bin/design_spec.dc (nonexistent) @@ -1,26 +0,0 @@ -############################################################################### -# -# Design Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters - -set design_files {ud_cnt ro_cnt atahost_pio_tctrl atahost_controller atahost_top} - -set design_name atahost_top -set active_design atahost_top - -# Next Statement defines all clocks and resets in the design -set special_net {wb_rst_i rst_nreset_i wb_clk_i} - -set hdl_src_dir ../../rtl/verilog/ocidec-1/ - Index: trunk/syn/bin/read.dc =================================================================== --- trunk/syn/bin/read.dc (revision 32) +++ trunk/syn/bin/read.dc (nonexistent) @@ -1,66 +0,0 @@ -############################################################################### -# -# Pre Synthesis Script -# -# This script only reads in the design and saves it in a DB file -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_pre.log" -append pre_comp_db_file ../out/$design_name "_pre.db" - -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Analyzing all design files ..." >> $log_file - -foreach module $design_files { - echo "+++++++++ Reading: $module" >> $log_file - echo +++++++++ Reading: $module - set module_file_name "" - append module_file_name $module ".v" - analyze -f verilog $module_file_name >> $log_file - elaborate $module >> $log_file - } - -current_design $active_design - -echo "+++++++++ Linking Design ..." >> $log_file -link >> $log_file - -echo "+++++++++ Uniquifying Design ..." >> $log_file -uniquify >> $log_file - -echo "+++++++++ Checking Design ..." >> $log_file -check_design >> $log_file - -# ============================================== -# Save Design -echo "+++++++++ Saving Design ..." >> $log_file -write_file -hierarchy -format db -output $pre_comp_db_file - Index: trunk/bench/verilog/wb_model_defines.v =================================================================== --- trunk/bench/verilog/wb_model_defines.v (revision 32) +++ trunk/bench/verilog/wb_model_defines.v (nonexistent) @@ -1,52 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Model Definitions //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_model_defines.v,v 1.1 2001-08-16 10:01:05 rudi Exp $ -// -// $Date: 2001-08-16 10:01:05 $ -// $Revision: 1.1 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// -// -// - -`timescale 1ns / 10ps Index: trunk/bench/verilog/wb_mast_model.v =================================================================== --- trunk/bench/verilog/wb_mast_model.v (revision 32) +++ trunk/bench/verilog/wb_mast_model.v (nonexistent) @@ -1,631 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Master Model //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_mast_model.v,v 1.1 2001-08-16 10:01:05 rudi Exp $ -// -// $Date: 2001-08-16 10:01:05 $ -// $Revision: 1.1 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// -// -// -// -// - -/* - -task mem_fill; - -- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values. - - -task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data); - -- Performs a single WISHBONE write - - -task wb_wr4( 32 bit address, 4 bit byte select, integer delay, - 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); - -- Performs 4 consecutive WISHBONE writes -- Strobe is deasserted between writes for 'delay' number of cycles - (This simulates wait state insertion ...) - - -task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay, - integer count); - -- Simular to wb_wr4, except it pwrforms "count" number of write cycles. - The data is taken from the internal wr_bub[] memory. -- Strobe is deasserted between writes for 'delay' number of cycles - (This simulates wait state insertion ...) - - -task wb_rmw( 32 bit address, 4 bit byte select, integer delay, - integer rcount, integer wcount); - -- This task performs "rcount" read cycles, followed by wcount write cycles. -- read data is placed in to the internal rd_buf[] memory, write data is - taken from the internal wr_buf[] memory. -- Strobe is deasserted between writes for 'delay' number of cycles - (This simulates wait state insertion ...) - - -task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data); - -- Performs a single WISHBONE write - - -task wb_rd4( 32 bit address, 4 bit byte select, integer delay, - 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); - -- Performs 4 consecutive WISHBONE reads -- Strobe is deasserted between reads for 'delay' number of cycles - (This simulates wait state insertion ...) - - -task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay, - integer count); - -- Simular to wb_rd4, except it pwrforms "count" number of read cycles. - The data is read in to the internal rd_buf[] memory. -- Strobe is deasserted between reads for 'delay' number of cycles - (This simulates wait state insertion ...) - - -*/ - - -`include "wb_model_defines.v" - -module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); - -input clk, rst; -output [31:0] adr; -input [31:0] din; -output [31:0] dout; -output cyc, stb; -output [3:0] sel; -output we; -input ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -parameter mem_size = 4096; - -reg [31:0] adr; -reg [31:0] dout; -reg cyc, stb; -reg [3:0] sel; -reg we; - -reg [31:0] rd_mem[mem_size:0]; -reg [31:0] wr_mem[mem_size:0]; -integer rd_cnt; -integer wr_cnt; - -//////////////////////////////////////////////////////////////////// -// -// Memory Logic -// - -initial - begin - adr = 32'hxxxx_xxxx; - dout = 32'hxxxx_xxxx; - cyc = 0; - stb = 0; - sel = 4'hx; - we = 1'hx; - rd_cnt = 0; - wr_cnt = 0; - #1; - $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); - end - - - -task mem_fill; - -integer n; -begin -rd_cnt = 0; -wr_cnt = 0; -for(n=0;n(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); - -The parameter "mem_addr_bus_width" indicates the size of the memory by -specifiying the number of address lines to the memory. - -task fill_mem(mode); -- This task initializes the internal memory. - If mode is 0, the memory is initialized to { ~address[15:0], address[15:0] }; - If mode is 1, the memory is initialized to random values. - - -The internal register "delay" specifies how fast ack is generated by the slave. -A value of 0 indicated immediatly, a value of 1 1 cycle delay etc. -It can be accesset by: -.delay = 5 bit value - -*/ - -`include "wb_model_defines.v" - -module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); - -input clk, rst; -input [31:0] adr, din; -output [31:0] dout; -input cyc, stb; -input [3:0] sel; -input we; -output ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -parameter mem_size = 13; -parameter sz = (1<5000) - begin - $display("\n\n*************************************\n"); - $display("ERROR: Watch Dog Counter Expired\n"); - $display("*************************************\n\n\n"); - $finish; - end - -///////////////////////////////////////////////////////////////////// -// -// DUT & Models -// - -// Create an external Tri-State Bus to the ATA Device -assign ata_din = ata_data; -assign ata_data = ata_doe ? ata_dout : 16'hzzzz; - -// DUT: ATA Host -atahost_top u0( //-- WISHBONE SYSCON signals - .wb_clk_i( clk ), - .arst_i( rst ), - .wb_rst_i( ~rst ), - - //-- WISHBONE SLAVE signals - .wb_cyc_i( wb_cyc_i ), - .wb_stb_i( wb_stb_i ), - .wb_ack_o( wb_ack_o ), - .wb_err_o( wb_err_o ), - .wb_adr_i( wb_addr_i[6:2] ), - .wb_dat_i( wb_data_i ), - .wb_dat_o( wb_data_o ), - .wb_sel_i( wb_sel_i ), - .wb_we_i( wb_we_i ), - .wb_inta_o( int ), - - //-- ATA signals - .resetn_pad_o( ata_rst_ ), - .dd_pad_i( ata_din ), - .dd_pad_o( ata_dout ), - .dd_padoe_o( ata_doe ), - .da_pad_o( ata_da ), - .cs0n_pad_o( ata_cs0 ), - .cs1n_pad_o( ata_cs1 ), - .diorn_pad_o( ata_dior_ ), - .diown_pad_o( ata_diow_ ), - .iordy_pad_i( ata_iordy ), - .intrq_pad_i( ata_intrq_r ) - ); - -// ATA Device Model -ata_device a0( .ata_rst_( ata_rst_ ), - .ata_data( ata_data ), - .ata_da( ata_da ), - .ata_cs0( ata_cs0 ), - .ata_cs1( ata_cs1 ), - .ata_dior_( ata_dior_ ), - .ata_diow_( ata_diow_ ), - .ata_iordy( ata_iordy ), - .ata_intrq( ata_intrq ) ); - -// WISHBONE Master Model -wb_mast m0( .clk( clk ), - .rst( rst ), - .adr( wb_addr_i ), - .din( wb_data_o ), - .dout( wb_data_i ), - .cyc( wb_cyc_i ), - .stb( wb_stb_i ), - .sel( wb_sel_i ), - .we( wb_we_i ), - .ack( wb_ack_o ), - .err( wb_err_o ), - .rty( 1'b0 ) ); - -// External Tests -`include "tests.v" - -endmodule - - Index: trunk/bench/verilog/tests.v =================================================================== --- trunk/bench/verilog/tests.v (revision 32) +++ trunk/bench/verilog/tests.v (nonexistent) @@ -1,676 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Tests Library //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: tests.v,v 1.1 2001-08-16 10:01:05 rudi Exp $ -// -// $Date: 2001-08-16 10:01:05 $ -// $Revision: 1.1 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// -// -// -// - - -task show_errors; -begin - -$display("\n"); -$display(" +--------------------+"); -$display(" | Total ERRORS: %0d |", error_cnt); -$display(" +--------------------+"); - -end -endtask - - -task reg_test; - -reg [31:0] data; -reg [31:0] pattern; -integer n; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** Register Test ***"); -$display("*****************************************************\n"); - - - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - -task io_test1; - -reg [31:0] data; -reg [31:0] data1; -reg [31:0] data2; -reg [31:0] data3; -integer n; -integer id; -integer del; -integer del_max; -integer iordy_del; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** IO Test 1 ***"); -$display("*** Testing WISHBONE wait state insertion, and ***"); -$display("*** iordy assertion. ***"); -$display("*****************************************************\n"); - -id = 0; -del_max = 16; -for(del=0;del>> Running Read Only test 1 ... (%0t)", $time); - for(n=0;n<16;n=n+1) - begin - m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); - if(data[15:0] != (n+8) ) - begin - $display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)", - (n+8), data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 1 ... (%0t)", $time); - - for(n=0;n<16;n=n+1) - begin - m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] ); - if(a0.mem[n+8] != ~n[15:0] ) - begin - $display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)", - ~n[15:0], a0.mem[n+8], $time); - error_cnt = error_cnt + 1; - end - end - - for(n=0;n<16;n=n+1) - begin - m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); - if(data[15:0] != ~n[15:0] ) - begin - $display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)", - ~n[15:0], data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 2 ... (%0t)", $time); - - for(n=0;n<16;n=n+1) - begin - m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] ); - m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); - if(data[15:0] != n[15:0] ) - begin - $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", - n[15:0], data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 3 ... (%0t)", $time); - - for(n=0;n<16;n=n+4) - begin - m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del, - {16'h0, ~n[13:0], 2'h3}, - {16'h0, ~n[13:0], 2'h2}, - {16'h0, ~n[13:0], 2'h1}, - {16'h0, ~n[13:0], 2'h0} ); - - m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 ); - - if( (data[15:0] != {~n[13:0], 2'h3}) | - (data1[15:0] != {~n[13:0], 2'h2}) | - (data2[15:0] != {~n[13:0], 2'h1}) | - (data3[15:0] != {~n[13:0], 2'h0}) ) - begin - $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", - n[15:0], data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time); - - a0.init_mem; - - for(n=0;n<16;n=n+1) - begin - m0.wr_mem[n] = n[15:0]; - m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1); - data = m0.rd_mem[n]; - - data2[15:0] = n[15:0] + 8; - - data1 = a0.mem[n+8]; - data3 = n[15:0]; - - if( (data[15:0] != data2[15:0] ) | - (data1[15:0] != data3[15:0]) ) - begin - $display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)", - data2[15:0], data[15:0], $time); - $display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)", - data1[15:0], data3[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - end -end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - -task io_test2; - -reg [31:0] data; -reg [31:0] data1; -reg [31:0] data2; -reg [31:0] data3; -integer n; -integer id; -integer del; -integer del_max; -integer pio_mode; -integer iordy_del; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** IO Test 2 ***"); -$display("*** Testing PIO Modes, iordy assertion and ***"); -$display("*** iordy delays. ***"); -$display("*****************************************************\n"); - -id = 0; -del = 1; -verbose = 0; -iordy_del = 0; -pio_mode=4; - -for(pio_mode=0;pio_mode<5;pio_mode=pio_mode+1) -for(id=0;id<2;id=id+1) -begin - if(!verbose) - $display("*** MODE SELECT: PIO mode: %0d iordy enable: %0d", pio_mode, id); - -for(iordy_del=0;iordy_del < (id ? 600 : 1); iordy_del=iordy_del+1) - begin - - if(verbose) - $display("*** MODE SELECT: PIO mode: %0d, 'iordy' enable: %0d iordy del: %0d\n", - pio_mode, id, iordy_del ); - - a0.mode = pio_mode; - a0.iordy_enable = id; - a0.iordy_delay = iordy_del; // Delay in nS - a0.init_mem; - - data1 = 32'h0000_0001; - m0.wb_wr1( `CTRL, 4'hf, data1); - m0.wb_rd1( `CTRL, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - data1 = 32'h1000_0000; - m0.wb_rd1( `STAT, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: STAT Register read Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - case(pio_mode) - 0: data1 = {8'h18, 8'h02, 8'h1c, 8'h04}; // Teoc, T4, T2, T1 - 1: data1 = {8'h05, 8'h01, 8'h1c, 8'h02}; // Teoc, T4, T2, T1 - 2: data1 = {8'h01, 8'h01, 8'h1c, 8'h00}; // Teoc, T4, T2, T1 - 3: data1 = {8'h07, 8'h00, 8'h07, 8'h00}; // Teoc, T4, T2, T1 - 4: data1 = {8'h02, 8'h00, 8'h06, 8'h00}; // Teoc, T4, T2, T1 - endcase - m0.wb_wr1( `PCTR, 4'hf, data1); - m0.wb_rd1( `PCTR, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: PCTR Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - if(id==1) data1 = 32'h0000_0082; - else data1 = 32'h0000_0080; - m0.wb_wr1( `CTRL, 4'hf, data1); - m0.wb_rd1( `CTRL, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - repeat(10) @(posedge clk); - - // Read only Test of ATA registers - if(verbose) $display(">>> Running Read Only test 1 ... (%0t)", $time); - for(n=0;n<16;n=n+1) - begin - m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); - if(data[15:0] != (n+8) ) - begin - $display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)", - (n+8), data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 1 ... (%0t)", $time); - - for(n=0;n<16;n=n+1) - begin - m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] ); - if(a0.mem[n+8] != ~n[15:0] ) - begin - $display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)", - ~n[15:0], a0.mem[n+8], $time); - error_cnt = error_cnt + 1; - end - end - - for(n=0;n<16;n=n+1) - begin - m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); - if(data[15:0] != ~n[15:0] ) - begin - $display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)", - ~n[15:0], data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 2 ... (%0t)", $time); - - for(n=0;n<16;n=n+1) - begin - m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] ); - m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); - if(data[15:0] != n[15:0] ) - begin - $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", - n[15:0], data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 3 ... (%0t)", $time); - - for(n=0;n<16;n=n+4) - begin - m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del, - {16'h0, ~n[13:0], 2'h3}, - {16'h0, ~n[13:0], 2'h2}, - {16'h0, ~n[13:0], 2'h1}, - {16'h0, ~n[13:0], 2'h0} ); - - m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 ); - - if( (data[15:0] != {~n[13:0], 2'h3}) | - (data1[15:0] != {~n[13:0], 2'h2}) | - (data2[15:0] != {~n[13:0], 2'h1}) | - (data3[15:0] != {~n[13:0], 2'h0}) ) - begin - $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", - n[15:0], data[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - - // Write Then Read Test of ATA registers - if(verbose) $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time); - - a0.init_mem; - - for(n=0;n<16;n=n+1) - begin - m0.wr_mem[n] = n[15:0]; - m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1); - data = m0.rd_mem[n]; - - data2[15:0] = n[15:0] + 8; - - data1 = a0.mem[n+8]; - data3 = n[15:0]; - - if( (data[15:0] != data2[15:0] ) | - (data1[15:0] != data3[15:0]) ) - begin - $display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)", - data2[15:0], data[15:0], $time); - $display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)", - data1[15:0], data3[15:0], $time); - error_cnt = error_cnt + 1; - end - end - if(verbose) $display(""); - - end -end - - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - -task rst_test; -reg [31:0] data; -reg [31:0] data1; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** RST Test ***"); -$display("*** ***"); -$display("*****************************************************\n"); - - - a0.iordy_enable = 0; - a0.iordy_delay = 0; // Delay in nS - a0.init_mem; - - data1 = 32'h0000_0080; - m0.wb_wr1( `CTRL, 4'hf, data1); - m0.wb_rd1( `CTRL, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - m0.wb_rd1( `STAT, 4'hf, data ); - m0.wb_rd1( `PCTR, 4'hf, data ); - - if(ata_rst_ !== 1'b1) - begin - $display("ERROR: ATA Reset not deasserted ... (%0t)", $time); - error_cnt = error_cnt + 1; - end - repeat(500) @(posedge clk); - - data1[0] = 1; - m0.wb_wr1( `CTRL, 4'hf, data1); - m0.wb_rd1( `CTRL, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - repeat(100) - begin - if(ata_rst_ !== 1'b0) - begin - $display("ERROR: ATA Reset not asserted ... (%0t)", $time); - error_cnt = error_cnt + 1; - end - - @(posedge clk); - end - - data1[0] = 0; - m0.wb_wr1( `CTRL, 4'hf, data1); - m0.wb_rd1( `CTRL, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - if(ata_rst_ !== 1'b1) - begin - $display("ERROR: ATA Reset not deasserted ... (%0t)", $time); - error_cnt = error_cnt + 1; - end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - - -task int_test; -reg [31:0] data; -reg [31:0] data1; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** INT Test ***"); -$display("*** ***"); -$display("*****************************************************\n"); - - a0.iordy_enable = 0; - a0.iordy_delay = 0; - a0.init_mem; - - data1 = 32'h0000_0080; - m0.wb_wr1( `CTRL, 4'hf, data1); - m0.wb_rd1( `CTRL, 4'hf, data ); - if(data != data1 ) - begin - $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", - data1, data, $time); - error_cnt = error_cnt + 1; - end - - // No interrupts at this point - m0.wb_rd1( `STAT, 4'hf, data ); - data1 = 32'h1000_0000; - if(data !== data1) - begin - $display("ERROR: ATA STATUS mismatch (1), Expected: %0h Got: %0h (%0t)", $time, data1, data); - error_cnt = error_cnt + 1; - end - - repeat(20) @(posedge clk); - - - // No interrupts at this point - m0.wb_rd1( `STAT, 4'hf, data ); - data1 = 32'h1000_0000; - if(data !== data1) - begin - $display("ERROR: ATA STATUS mismatch (2), Expected: %0h Got: %0h (%0t)", $time, data1, data); - error_cnt = error_cnt + 1; - end - - // Assert Interrup - ata_intrq_r = 1; - repeat(10) @(posedge clk); - ata_intrq_r = 0; - - - // Check to see if int bit is set - m0.wb_rd1( `STAT, 4'hf, data ); - data1 = 32'h1000_0001; - if(data !== data1) - begin - $display("ERROR: ATA STATUS mismatch (3), Expected: %0h Got: %0h (%0t)", data1, data, $time); - error_cnt = error_cnt + 1; - end - - repeat(10) @(posedge clk); - - // Make sure it is not cleared after another read - m0.wb_rd1( `STAT, 4'hf, data ); - data1 = 32'h1000_0001; - if(data !== data1) - begin - $display("ERROR: ATA STATUS mismatch (4), Expected: %0h Got: %0h (%0t)", data1, data, $time); - error_cnt = error_cnt + 1; - end - - // Clear interrupt - data1 = 32'h0000_0000; - m0.wb_wr1( `STAT, 4'hf, data1 ); - - - // Should be cleared now ... - m0.wb_rd1( `STAT, 4'hf, data ); - data1 = 32'h1000_0000; - if(data !== data1) - begin - $display("ERROR: ATA STATUS mismatch (5), Expected: %0h Got: %0h (%0t)", data1, data, $time); - error_cnt = error_cnt + 1; - end - - // Check again .... - m0.wb_rd1( `STAT, 4'hf, data ); - data1 = 32'h1000_0000; - if(data !== data1) - begin - $display("ERROR: ATA STATUS mismatch (6), Expected: %0h Got: %0h (%0t)", data1, data, $time); - error_cnt = error_cnt + 1; - end - - repeat(100) @(posedge clk); - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); - -end -endtask - - Index: trunk/bench/verilog/ata_device.v =================================================================== --- trunk/bench/verilog/ata_device.v (revision 32) +++ trunk/bench/verilog/ata_device.v (nonexistent) @@ -1,397 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// ATA (IDE) Device Model //// -//// This Model Supports PIO cycles only ! //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/ata/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: ata_device.v,v 1.2 2002-02-25 06:07:21 rherveille Exp $ -// -// $Date: 2002-02-25 06:07:21 $ -// $Revision: 1.2 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/08/16 10:01:05 rudi -// -// - Added Test Bench -// - Added Synthesis scripts for Design Compiler -// - Fixed minor bug in atahost_top -// -// -// -// -// - -`timescale 1ns / 10ps - -module ata_device( ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1, - ata_dior_, ata_diow_, ata_iordy, ata_intrq ); -input ata_rst_; -inout [15:0] ata_data; -input [2:0] ata_da; -input ata_cs0, ata_cs1; -input ata_dior_, ata_diow_; -output ata_iordy; -output ata_intrq; - -integer mode; -integer n; -reg ata_iordy; -reg iordy_enable; -integer iordy_delay; - -reg [15:0] mem[32:0]; -reg [15:0] dout; -reg dout_en; -wire ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4; -wire [4:0] addr; -wire ata_dior, ata_diow; - -initial - begin - dout_en = 0; - mode = 0; - iordy_enable = 0; - iordy_delay = 0; - ata_iordy = 1; - end - -assign ata_dior = !ata_dior_; -assign ata_diow = !ata_diow_; - -assign ata_intrq = 0; - -assign ata_data = dout_en ? dout : 16'hzzzz; - -assign addr = {~ata_cs1, ~ata_cs0, ata_da}; - -always @(posedge ata_rst_) - dout_en = 0; - -always @(posedge ata_dior) - begin - dout = mem[ addr ]; - dout_en = 1; - end - -always @(posedge ata_dior) - begin - dout_en = 0; - end - -always @(posedge ata_diow) - begin - mem[ addr ] = ata_data; - end - -always @(posedge ata_dior or posedge ata_diow) - begin - ata_iordy = 1'b0; - #(iordy_delay); - ata_iordy = 1'b1; - end - -task init_mem; - -begin - -for(n=0;n<32;n=n+1) - mem[n] = n; -end -endtask - -assign ata_rst_m0 = ata_rst_ & (mode==0); -assign ata_rst_m1 = ata_rst_ & (mode==1); -assign ata_rst_m2 = ata_rst_ & (mode==2); -assign ata_rst_m3 = ata_rst_ & (mode==3); -assign ata_rst_m4 = ata_rst_ & (mode==4); - -specify - specparam // ATA Mode 0 Timing - M0_DioCycle = 600, // T0 - M0_AddrSetup = 70, // T1 - M0_DioHigh = 290, // T2 - M0_WrSetup = 60, // T3 - M0_WrHold = 30, // T4 - M0_DoutSetup = 50, // T5 - M0_DoutHold = 5, // T6 - M0_AddrHold = 20, // T9 - - // ATA Mode 1 Timing - M1_DioCycle = 383, // T0 - M1_AddrSetup = 50, // T1 - M1_DioHigh = 290, // T2 - M1_WrSetup = 45, // T3 - M1_WrHold = 20, // T4 - M1_DoutSetup = 35, // T5 - M1_DoutHold = 5, // T6 - M1_AddrHold = 15, // T9 - - // ATA Mode 2 Timing - M2_DioCycle = 330, // T0 - M2_AddrSetup = 30, // T1 - M2_DioHigh = 290, // T2 - M2_WrSetup = 30, // T3 - M2_WrHold = 15, // T4 - M2_DoutSetup = 20, // T5 - M2_DoutHold = 5, // T6 - M2_AddrHold = 10, // T9 - - // ATA Mode 3 Timing - M3_DioCycle = 180, // T0 - M3_AddrSetup = 30, // T1 - M3_DioHigh = 80, // T2 - M3_DioLow = 70, // T2i - M3_WrSetup = 30, // T3 - M3_WrHold = 10, // T4 - M3_DoutSetup = 20, // T5 - M3_DoutHold = 5, // T6 - M3_AddrHold = 10, // T9 - - // ATA Mode 4 Timing - M4_DioCycle = 120, // T0 - M4_AddrSetup = 25, // T1 - M4_DioHigh = 70, // T2 - M4_DioLow = 25, // T2i - M4_WrSetup = 20, // T3 - M4_WrHold = 10, // T4 - M4_DoutSetup = 20, // T5 - M4_DoutHold = 5, // T6 - M4_AddrHold = 10; // T9 - - - - ///////////////////////////////////////////////////// - // ATA Mode 0 Timing // - ///////////////////////////////////////////////////// - - // Output Delay Path - if(mode==0) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) - (0,0, - M0_DoutHold, (M0_DioHigh - M0_DoutSetup), - M0_DoutHold, (M0_DioHigh - M0_DoutSetup) ); - - // Write Data Setup/Hold Check - $setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 ); - - // DioX Active time Check - $width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh ); - $width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh ); - - // DioX Min Cycle Width Check - $period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle ); - $period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle ); - - // Address Setup Hold Checks - $setup(ata_da, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup); - $setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup); - $setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup); - $setup(ata_da, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup); - $setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup); - $setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup); - - $hold(ata_da, negedge ata_dior &&& ata_rst_m0, M0_AddrHold); - $hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold); - $hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold); - $hold(ata_da, negedge ata_diow &&& ata_rst_m0, M0_AddrHold); - $hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold); - $hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold); - - - ///////////////////////////////////////////////////// - // ATA Mode 1 Timing // - ///////////////////////////////////////////////////// - - // Output Delay Path - if(mode==1) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) - (0,0, - M1_DoutHold, (M1_DioHigh - M1_DoutSetup), - M1_DoutHold, (M1_DioHigh - M1_DoutSetup) ); - - // Write Data Setup/Hold Check - $setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 ); - - // DioX Active time Check - $width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh ); - $width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh ); - - // DioX Min Cycle Width Check - $period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle ); - $period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle ); - - // Address Setup Hold Checks - $setup(ata_da, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup); - $setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup); - $setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup); - $setup(ata_da, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup); - $setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup); - $setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup); - - $hold(ata_da, negedge ata_dior &&& ata_rst_m1, M1_AddrHold); - $hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold); - $hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold); - $hold(ata_da, negedge ata_diow &&& ata_rst_m1, M1_AddrHold); - $hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold); - $hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold); - - - ///////////////////////////////////////////////////// - // ATA Mode 2 Timing // - ///////////////////////////////////////////////////// - - // Output Delay Path - if(mode==2) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) - (0,0, - M2_DoutHold, (M2_DioHigh - M2_DoutSetup), - M2_DoutHold, (M2_DioHigh - M2_DoutSetup) ); - - // Write Data Setup/Hold Check - $setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 ); - - // DioX Active time Check - $width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh ); - $width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh ); - - // DioX Min Cycle Width Check - $period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle ); - $period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle ); - - // Address Setup Hold Checks - $setup(ata_da, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup); - $setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup); - $setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup); - $setup(ata_da, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup); - $setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup); - $setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup); - - $hold(ata_da, negedge ata_dior &&& ata_rst_m2, M2_AddrHold); - $hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold); - $hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold); - $hold(ata_da, negedge ata_diow &&& ata_rst_m2, M2_AddrHold); - $hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold); - $hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold); - - ///////////////////////////////////////////////////// - // ATA Mode 3 Timing // - ///////////////////////////////////////////////////// - - // Output Delay Path - if(mode==3) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) - (0,0, - M3_DoutHold, (M3_DioHigh - M3_DoutSetup), - M3_DoutHold, (M3_DioHigh - M3_DoutSetup) ); - - // Write Data Setup/Hold Check - $setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 ); - - // DioX Active time Check - $width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh ); - $width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh ); - - $width(negedge ata_dior &&& ata_rst_m3, M3_DioLow ); - $width(negedge ata_diow &&& ata_rst_m3, M3_DioLow ); - - // DioX Min Cycle Width Check - $period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle ); - $period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle ); - - // Address Setup Hold Checks - $setup(ata_da, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup); - $setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup); - $setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup); - $setup(ata_da, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup); - $setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup); - $setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup); - - $hold(ata_da, negedge ata_dior &&& ata_rst_m3, M3_AddrHold); - $hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold); - $hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold); - $hold(ata_da, negedge ata_diow &&& ata_rst_m3, M3_AddrHold); - $hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold); - $hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold); - - - ///////////////////////////////////////////////////// - // ATA Mode 4 Timing // - ///////////////////////////////////////////////////// - - // Output Delay Path - if(mode==4) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) - (0,0, - M4_DoutHold, (M4_DioHigh - M4_DoutSetup), - M4_DoutHold, (M4_DioHigh - M4_DoutSetup) ); - - // Write Data Setup/Hold Check - $setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 ); - - // DioX Active time Check - $width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh ); - $width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh ); - - $width(negedge ata_dior &&& ata_rst_m4, M4_DioLow ); - $width(negedge ata_diow &&& ata_rst_m4, M4_DioLow ); - - // DioX Min Cycle Width Check - $period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle ); - $period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle ); - - // Address Setup Hold Checks - $setup(ata_da, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup); - $setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup); - $setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup); - $setup(ata_da, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup); - $setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup); - $setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup); - - $hold(ata_da, negedge ata_dior &&& ata_rst_m4, M4_AddrHold); - $hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold); - $hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold); - $hold(ata_da, negedge ata_diow &&& ata_rst_m4, M4_AddrHold); - $hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold); - $hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold); - - - -endspecify - - -endmodule - - Index: trunk/rtl/verilog/ocidec-1/timescale.v =================================================================== --- trunk/rtl/verilog/ocidec-1/timescale.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/timescale.v (nonexistent) @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - Index: trunk/rtl/verilog/ocidec-1/atahost_controller.v =================================================================== --- trunk/rtl/verilog/ocidec-1/atahost_controller.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/atahost_controller.v (nonexistent) @@ -1,266 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OCIDEC-1 ATA/ATAPI-5 Host Controller //// -//// PIO Controller //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: atahost_controller.v,v 1.4 2002-05-19 06:04:22 rherveille Exp $ -// -// $Date: 2002-05-19 06:04:22 $ -// $Revision: 1.4 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// rev.: 1.0 june 28th, 2001. Initial Verilog release -// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section. -// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite. -// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). -// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments. -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/02/16 10:42:17 rherveille -// Added disclaimer -// Added CVS information -// Changed core for new internal counter libraries (synthesis fixes). -// -// -// - -`include "timescale.v" - -module atahost_controller (clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, - PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, - PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe, - RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ); - // - // parameter declarations - // - parameter TWIDTH = 8; // counter width - // PIO mode 0 timing settings @100MHz master clock - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - // - // inputs & outputs - // - input clk; //master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - - output irq; // interrupt request signal - reg irq; - - // control bits - input IDEctrl_rst; - input IDEctrl_IDEen; - - // PIO timing registers - input [7:0] PIO_cmdport_T1; - input [7:0] PIO_cmdport_T2; - input [7:0] PIO_cmdport_T4; - input [7:0] PIO_cmdport_Teoc; - input PIO_cmdport_IORDYen; - - // PIO control signals - input PIOreq; // PIO transfer request - output PIOack; // PIO transfer ended - input [ 3:0] PIOa; // PIO address - input [15:0] PIOd; // PIO data in - output [15:0] PIOq; // PIO data out - input PIOwe; // PIO direction bit. 1'b1==write, 1'b0==read - - reg [15:0] PIOq; - reg PIOack; - - // ATA signals - output RESETn; - input [15:0] DDi; - output [15:0] DDo; - output DDoe; - output [ 2:0] DA; - output CS0n; - output CS1n; - output DIORn; - output DIOWn; - input IORDY; - input INTRQ; - - reg RESETn; - reg [15:0] DDo; - reg DDoe; - reg [ 2:0] DA; - reg CS0n; - reg CS1n; - reg DIORn; - reg DIOWn; - - // - // Variable declarations - // - - reg dPIOreq; - reg PIOgo; // start PIO timing controller - wire PIOdone; // PIO timing controller done - - // PIO signals - wire PIOdior, PIOdiow; - wire PIOoe; - - // Timing settings - wire dstrb; - wire [TWIDTH-1:0] T1, T2, T4, Teoc; - wire IORDYen; - - // synchronized ATA inputs - reg sIORDY; - - // - // Module body - // - - - // synchronize incoming signals - reg cIORDY; // capture IORDY - reg cINTRQ; // capture INTRQ - - always@(posedge clk) - begin : synch_incoming - cIORDY <= #1 IORDY; - cINTRQ <= #1 INTRQ; - - sIORDY <= #1 cIORDY; - irq <= #1 cINTRQ; - end - - // generate ATA signals - always@(posedge clk or negedge nReset) - if (~nReset) - begin - RESETn <= #1 1'b0; - DIORn <= #1 1'b1; - DIOWn <= #1 1'b1; - DA <= #1 0; - CS0n <= #1 1'b1; - CS1n <= #1 1'b1; - DDo <= #1 0; - DDoe <= #1 1'b0; - end - else if (rst) - begin - RESETn <= #1 1'b0; - DIORn <= #1 1'b1; - DIOWn <= #1 1'b1; - DA <= #1 0; - CS0n <= #1 1'b1; - CS1n <= #1 1'b1; - DDo <= #1 0; - DDoe <= #1 1'b0; - end - else - begin - RESETn <= #1 !IDEctrl_rst; - DA <= #1 PIOa[2:0]; - CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0' - CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1' - - DDo <= #1 PIOd; - DDoe <= #1 PIOoe; - DIORn <= #1 !PIOdior; - DIOWn <= #1 !PIOdiow; - end - - - // - ////////////////////////// - // PIO transfer control // - ////////////////////////// - // - // capture ATA data for PIO access - always@(posedge clk) - if (dstrb) - PIOq <= #1 DDi; - - // generate PIOgo signal - always @(posedge clk or negedge nReset) - if (~nReset) - begin - dPIOreq <= #1 1'b0; - PIOgo <= #1 1'b0; - end - else if (rst) - begin - dPIOreq <= #1 1'b0; - PIOgo <= #1 1'b0; - end - else - begin - dPIOreq <= #1 PIOreq & !PIOack; - PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen; - end - - // set Timing signals - assign T1 = PIO_cmdport_T1; - assign T2 = PIO_cmdport_T2; - assign T4 = PIO_cmdport_T4; - assign Teoc = PIO_cmdport_Teoc; - assign IORDYen = PIO_cmdport_IORDYen; - - // hookup timing controller - atahost_pio_tctrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) - PIO_timing_controller ( - .clk(clk), - .nReset(nReset), - .rst(rst), - .IORDY_en(IORDYen), - .T1(T1), - .T2(T2), - .T4(T4), - .Teoc(Teoc), - .go(PIOgo), - .we(PIOwe), - .oe(PIOoe), - .done(PIOdone), - .dstrb(dstrb), - .DIOR(PIOdior), - .DIOW(PIOdiow), - .IORDY(sIORDY) - ); - - always@(posedge clk) - PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) - -endmodule Index: trunk/rtl/verilog/ocidec-1/revision_history.txt =================================================================== --- trunk/rtl/verilog/ocidec-1/revision_history.txt (revision 32) +++ trunk/rtl/verilog/ocidec-1/revision_history.txt (nonexistent) @@ -1,93 +0,0 @@ ------------------------------ -Revision: 1.0 -Date: June 28th, 2001 -Author: Richard Herveille -- Initial Verilog release (beta) ------------------------------ - ------------------------------ -Revision: 1.1 -Date: June 18th, 2001 -Author: Richard Herveille -- Fixed some incomplete port lists and some Verilog related issues. - Design now completely compiles ------------------------------ - ------------------------------ -Revision: 1.1a -Date: July 3rd, 2001 -Author: Richard Herveille -- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues. ------------------------------ - ------------------------------ -Revision: 1.2 -Date: July 9th, 2001 -Author: Richard Herveille -- added 'timescale to all files -- fixed error where control registers latched data on all rising clock edges, instead of - when addressed. ------------------------------ - ------------------------------ -Revision: 1.3 -Date: July 11th, 2001 -Author: Richard Herveille -- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration. -- changed 'ata.v' into 'atahost.v' -- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous -- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). ------------------------------ - ------------------------------ -Revision: 1.4 -Date: July 26th, 2001 -Author: Richard Herveille -- Fixed some blocking versus non-blocking statement issues. ------------------------------ - ------------------------------ -Revision: 1.5 -Date: August 15th, 2001. -Author: Richard Herveille -- Changed filenames and top-level port names to be conform new OpenCores conventions ------------------------------ - ------------------------------ -Revision: 1.6 -Date: September 12th, 2001. -Author: Richard Herveille -- Made asynchronous input programmable (using atahost_define.v) ------------------------------ - ------------------------------ -Revision: 1.7 -Date: October 16th, 2001. -Author: Richard Herveille -- Changed programmable asynchronous level from define to parameter ------------------------------ - ------------------------------ -Revision: 1.8 -Date: Februar 16th, 2002. -Author: Richard Herveille -- Added disclaimer -- Added CVS information -- Changed core for new counter libraries -- Updated testbench ------------------------------ - ------------------------------ -Revision: 1.9 -Date: Februar 17th, 2002. -Author: Richard Herveille -- moved wishbone interface into 'atahost_wb_slave.v' ------------------------------ - ------------------------------ -Revision: 1.10 -Date: May 19th, 2002. -Author: Richard Herveille -- Fixed a potential bug that forced the core into an unknown state - when an asynchronous reset was given without a running clock ------------------------------ Index: trunk/rtl/verilog/ocidec-1/ud_cnt.v =================================================================== --- trunk/rtl/verilog/ocidec-1/ud_cnt.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/ud_cnt.v (nonexistent) @@ -1,100 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Generic Up/Down counter //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: ud_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $ -// -// $Date: 2002-02-16 10:42:17 $ -// $Revision: 1.2 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// - - -///////////////////////////// -// general purpose counter // -///////////////////////////// - -`include "timescale.v" - -module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco); - // parameter declaration - parameter SIZE = 8; - parameter RESD = {SIZE{1'b0}}; // data after reset - - // inputs & outputs - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - input cnt_en; // count enable - input ud; // up/not down - input nld; // synchronous active low load - input [SIZE-1:0] d; // load counter value - output [SIZE-1:0] q; // current counter value - input rci; // carry input - output rco; // carry output - - // variable declarations - reg [SIZE-1:0] Qi; // intermediate value - wire [SIZE:0] val; // carry+result - - // - // Module body - // - - assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci); - - always@(posedge clk or negedge nReset) - begin - if (~nReset) - Qi <= #1 RESD; - else if (rst) - Qi <= #1 RESD; - else if (~nld) - Qi <= #1 d; - else if (cnt_en) - Qi <= #1 val[SIZE-1:0]; - end - - // assign outputs - assign q = Qi; - assign rco = val[SIZE]; -endmodule - - Index: trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v =================================================================== --- trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v (nonexistent) @@ -1,265 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores ATA/ATAPI-5 Host Controller //// -//// PIO Timing Controller (common for all OCIDEC cores) //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: atahost_pio_tctrl.v,v 1.3 2002-02-18 14:25:43 rherveille Exp $ -// -// $Date: 2002-02-18 14:25:43 $ -// $Revision: 1.3 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// Rev. 1.0 June 27th, 2001. Initial Verilog release -// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues. -// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation. -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/02/16 10:42:17 rherveille -// Added disclaimer -// Added CVS information -// Changed core for new internal counter libraries (synthesis fixes). -// -// - - -// -// Timing PIO mode transfers -//-------------------------------------------- -// T0: cycle time -// T1: address valid to DIOR-/DIOW- -// T2: DIOR-/DIOW- pulse width -// T2i: DIOR-/DIOW- recovery time -// T3: DIOW- data setup -// T4: DIOW- data hold -// T5: DIOR- data setup -// T6: DIOR- data hold -// T9: address hold from DIOR-/DIOW- negated -// Trd: Read data valid to IORDY asserted -// Ta: IORDY setup time -// Tb: IORDY pulse width -// -// Transfer sequence -//-------------------------------- -// 1) set address (DA, CS0-, CS1-) -// 2) wait for T1 -// 3) assert DIOR-/DIOW- -// when write action present Data (timing spec. T3 always honored), enable output enable-signal -// 4) wait for T2 -// 5) check IORDY -// when not IORDY goto 5 -// when IORDY negate DIOW-/DIOR-, latch data (if read action) -// when write, hold data for T4, disable output-enable signal -// 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest -// 7) start new cycle - -`include "timescale.v" - -module atahost_pio_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY); - // parameter declarations - parameter TWIDTH = 8; - parameter PIO_MODE0_T1 = 6; // 70ns - parameter PIO_MODE0_T2 = 28; // 290ns - parameter PIO_MODE0_T4 = 2; // 30ns - parameter PIO_MODE0_Teoc = 23; // 240ns - - // inputs & outputs - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - - // timing & control register settings - input IORDY_en; // use IORDY (or not) - input [TWIDTH-1:0] T1; // T1 time (in clk-ticks) - input [TWIDTH-1:0] T2; // T1 time (in clk-ticks) - input [TWIDTH-1:0] T4; // T1 time (in clk-ticks) - input [TWIDTH-1:0] Teoc; // T1 time (in clk-ticks) - - // control signals - input go; // PIO controller selected (strobe signal) - input we; // write enable signal. 1'b0 == read, 1'b1 == write - - // return signals - output oe; // output enable signal - reg oe; - output done; // finished cycle - output dstrb; // data strobe, latch data (during read) - reg dstrb; - - // ata signals - output DIOR; // IOread signal, active high - reg DIOR; - output DIOW; // IOwrite signal, active high - reg DIOW; - input IORDY; // IOrDY signal - - - // - // constant declarations - // - // PIO mode 0 settings (@100MHz clock) - wire [TWIDTH-1:0] T1_m0 = PIO_MODE0_T1; - wire [TWIDTH-1:0] T2_m0 = PIO_MODE0_T2; - wire [TWIDTH-1:0] T4_m0 = PIO_MODE0_T4; - wire [TWIDTH-1:0] Teoc_m0 = PIO_MODE0_Teoc; - - // - // variable declaration - // - reg busy, hold_go; - wire igo; - wire T1done, T2done, T4done, Teoc_done, IORDY_done; - reg hT2done; - - // - // module body - // - - // generate internal go strobe - // strecht go until ready for new cycle - always@(posedge clk or negedge nReset) - if (~nReset) - begin - busy <= #1 1'b0; - hold_go <= #1 1'b0; - end - else if (rst) - begin - busy <= #1 1'b0; - hold_go <= #1 1'b0; - end - else - begin - busy <= #1 (igo | busy) & !Teoc_done; - hold_go <= #1 (go | (hold_go & busy)) & !igo; - end - - assign igo = (go | hold_go) & !busy; - - // 1) hookup T1 counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1) - t1_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(igo), - .d(T1), - .q(), - .done(T1done) - ); - - // 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device - always@(posedge clk or negedge nReset) - if (~nReset) - begin - DIOR <= #1 1'b0; - DIOW <= #1 1'b0; - oe <= #1 1'b0; - end - else if (rst) - begin - DIOR <= #1 1'b0; - DIOW <= #1 1'b0; - oe <= #1 1'b0; - end - else - begin - DIOR <= #1 (!we & T1done) | (DIOR & !IORDY_done); - DIOW <= #1 ( we & T1done) | (DIOW & !IORDY_done); - oe <= #1 ( (we & igo) | oe) & !T4done; // negate oe when t4-done - end - - // 3) hookup T2 counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2) - t2_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(T1done), - .d(T2), - .q(), - .done(T2done) - ); - - // 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) - // hold T2done - always@(posedge clk or negedge nReset) - if (~nReset) - hT2done <= #1 1'b0; - else if (rst) - hT2done <= #1 1'b0; - else - hT2done <= #1 (T2done | hT2done) & !IORDY_done; - - assign IORDY_done = (T2done | hT2done) & (IORDY | !IORDY_en); - - // generate datastrobe, capture data at rising DIOR- edge - always@(posedge clk) - dstrb <= #1 IORDY_done; - - // hookup data hold counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4) - dhold_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(IORDY_done), - .d(T4), - .q(), - .done(T4done) - ); - - assign done = T4done; // placing done here provides the fastest return possible, - // while still guaranteeing data and address hold-times - - // 5) hookup end_of_cycle counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc) - eoc_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(IORDY_done), - .d(Teoc), - .q(), - .done(Teoc_done) - ); - -endmodule Index: trunk/rtl/verilog/ocidec-1/ro_cnt.v =================================================================== --- trunk/rtl/verilog/ocidec-1/ro_cnt.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/ro_cnt.v (nonexistent) @@ -1,106 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Run-Once counter //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: ro_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $ -// -// $Date: 2002-02-16 10:42:17 $ -// $Revision: 1.2 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// - - -/////////////////////////// -// run-once down-counter // -/////////////////////////// - -// counts D+1 cycles before generating 'DONE' - -`include "timescale.v" - -module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q); - - // parameter declaration - parameter SIZE = 8; - - parameter UD = 1'b0; // default count down - parameter ID = {SIZE{1'b0}}; // initial data after reset - - // inputs & outputs - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - input cnt_en; // count enable - input go; // load counter and start sequence - output done; // done counting - input [SIZE-1:0] d; // load counter value - output [SIZE-1:0] q; // current counter value - - // variable declarations - reg rci; - wire nld, rco; - - // - // module body - // - - always@(posedge clk or negedge nReset) - if (~nReset) - rci <= #1 1'b0; - else if (rst) - rci <= #1 1'b0; - else //if (cnt_en) - rci <= #1 go | (rci & !rco); - - assign nld = !go; - - // hookup counter - ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en), - .ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco)); - - - // assign outputs - - assign done = rco; - -endmodule - - - Index: trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v =================================================================== --- trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v (nonexistent) @@ -1,482 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OCIDEC-1 ATA/ATAPI-5 Controller //// -//// Wishbone Slave interface (common for all OCIDEC cores) //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// -// CVS Log -// -// $Id: atahost_wb_slave.v,v 1.1 2002-02-18 14:25:43 rherveille Exp $ -// -// $Date: 2002-02-18 14:25:43 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// - -`include "timescale.v" - -module atahost_wb_slave ( - clk_i, arst_i, rst_i, cyc_i, stb_i, ack_o, rty_o, err_o, adr_i, dat_i, dat_o, sel_i, we_i, inta_o, - PIOsel, PIOtip, PIOack, PIOq, PIOpp_full, irq, - DMAsel, DMAtip, DMAack, DMARxEmpty, DMATxFull, DMA_dmarq, DMAq, - IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR1, IDEctrl_FATR0, IDEctrl_ppen, - DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1, - PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, - PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc, PIO_dport0_IORDYen, - PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc, PIO_dport1_IORDYen, - DMA_dev0_Tm, DMA_dev0_Td, DMA_dev0_Teoc, DMA_dev1_Tm, DMA_dev1_Td, DMA_dev1_Teoc - ); - - // - // Parameters - // - parameter DeviceId = 4'h0; - parameter RevisionNo = 4'h0; - - // PIO mode 0 settings (@100MHz clock) - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - // Multiword DMA mode 0 settings (@100MHz clock) - parameter DMA_mode0_Tm = 6; // 50ns - parameter DMA_mode0_Td = 21; // 215ns - parameter DMA_mode0_Teoc = 21; // 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - - // - // inputs & outputs - // - - // WISHBONE SYSCON signals - input clk_i; // master clock in - input arst_i; // asynchronous active low reset - input rst_i; // synchronous active high reset - - // WISHBONE SLAVE signals - input cyc_i; // valid bus cycle input - input stb_i; // strobe/core select input - output ack_o; // strobe acknowledge output - output rty_o; // retry output - output err_o; // error output - input [6:2] adr_i; // A6 = '1' ATA devices selected - // A5 = '1' CS1- asserted, '0' CS0- asserted - // A4..A2 ATA address lines - // A6 = '0' ATA controller selected - input [31:0] dat_i; // Databus in - output [31:0] dat_o; // Databus out - input [ 3:0] sel_i; // Byte select signals - input we_i; // Write enable input - output inta_o; // interrupt request signal IDE0 - - // PIO control input - output PIOsel; - input PIOtip; // PIO transfer in progress - input PIOack; // PIO acknowledge signal - input [15:0] PIOq; // PIO data input - input PIOpp_full; // PIO write-ping-pong buffers full - input irq; // interrupt signal input - - // DMA control inputs - output DMAsel; - input DMAtip; // DMA transfer in progress - input DMAack; // DMA transfer acknowledge - input DMARxEmpty; // DMA receive buffer empty - input DMATxFull; // DMA transmit buffer full - input DMA_dmarq; // wishbone DMA request - input [31:0] DMAq; - - // outputs - // control register outputs - output IDEctrl_rst; - output IDEctrl_IDEen; - output IDEctrl_FATR1; - output IDEctrl_FATR0; - output IDEctrl_ppen; - output DMActrl_DMAen; - output DMActrl_dir; - output DMActrl_BeLeC0; - output DMActrl_BeLeC1; - - // CMD port timing registers - output [7:0] PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc; - output PIO_cmdport_IORDYen; - - reg [7:0] PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc; - - // data-port0 timing registers - output [7:0] PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc; - output PIO_dport0_IORDYen; - - reg [7:0] PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc; - - // data-port1 timing registers - output [7:0] PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc; - output PIO_dport1_IORDYen; - - reg [7:0] PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc; - - // DMA device0 timing registers - output [7:0] DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc; - - reg [7:0] DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc; - - // DMA device1 timing registers - output [7:0] DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc; - - reg [7:0] DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc; - - - // - // constants - // - - // addresses - `define ATA_DEV_ADR adr_i[6] - `define ATA_ADR adr_i[5:2] - - `define ATA_CTRL_REG 4'b0000 - `define ATA_STAT_REG 4'b0001 - `define ATA_PIO_CMD 4'b0010 - `define ATA_PIO_DP0 4'b0011 - `define ATA_PIO_DP1 4'b0100 - `define ATA_DMA_DEV0 4'b0101 - `define ATA_DMA_DEV1 4'b0110 - // reserved // - `define ATA_DMA_PORT 4'b1111 - - - // - // signals - // - - // registers - reg [31:0] CtrlReg; // control register - wire [31:0] StatReg; // status register - - // store ping-pong-full signal - reg store_pp_full; - - - // - // generate bus cycle / address decoder - // - wire w_acc = &sel_i[1:0]; // word access - wire dw_acc = &sel_i; // double word access - - // bus error - wire berr = `ATA_DEV_ADR ? !w_acc : !dw_acc; - - // PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong-full - wire PIOsel = cyc_i & stb_i & `ATA_DEV_ADR & w_acc & !(DMAtip | store_pp_full); - - // CON accesses only 32bit wide - wire CONsel = cyc_i & stb_i & !(`ATA_DEV_ADR) & dw_acc; - wire DMAsel = CONsel & (`ATA_ADR == `ATA_DMA_PORT); - - // bus retry (OCIDEC-3 and above) - // store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle - always@(posedge clk_i) - if (!PIOsel) - store_pp_full <= #1 PIOpp_full; - - wire brty = (`ATA_DEV_ADR & w_acc) & (DMAtip | store_pp_full); - - // - // generate registers - // - - // generate register select signals - wire sel_ctrl = CONsel & we_i & (`ATA_ADR == `ATA_CTRL_REG); - wire sel_stat = CONsel & we_i & (`ATA_ADR == `ATA_STAT_REG); - wire sel_PIO_cmdport = CONsel & we_i & (`ATA_ADR == `ATA_PIO_CMD); - wire sel_PIO_dport0 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP0); - wire sel_PIO_dport1 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP1); - wire sel_DMA_dev0 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV0); - wire sel_DMA_dev1 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV1); - // reserved 0x1c-0x38 - // reserved 0x3c : DMA-port - - - // generate control register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - CtrlReg[31:1] <= #1 0; - CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) - end - else if (rst_i) - begin - CtrlReg[31:1] <= #1 0; - CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) - end - else if (sel_ctrl) - CtrlReg <= #1 dat_i; - - // assign bits - assign DMActrl_DMAen = CtrlReg[15]; - assign DMActrl_dir = CtrlReg[13]; - assign DMActrl_BeLeC1 = CtrlReg[9]; - assign DMActrl_BeLeC0 = CtrlReg[8]; - assign IDEctrl_IDEen = CtrlReg[7]; - assign IDEctrl_FATR1 = CtrlReg[6]; - assign IDEctrl_FATR0 = CtrlReg[5]; - assign IDEctrl_ppen = CtrlReg[4]; - assign PIO_dport1_IORDYen = CtrlReg[3]; - assign PIO_dport0_IORDYen = CtrlReg[2]; - assign PIO_cmdport_IORDYen = CtrlReg[1]; - assign IDEctrl_rst = CtrlReg[0]; - - - // generate status register clearable bits - reg dirq, int; - - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - int <= #1 1'b0; - dirq <= #1 1'b0; - end - else if (rst_i) - begin - int <= #1 1'b0; - dirq <= #1 1'b0; - end - else - begin - int <= #1 (int | (irq & !dirq)) & !(sel_stat & !dat_i[0]); - dirq <= #1 irq; - end - - // assign status bits - assign StatReg[31:28] = DeviceId; // set Device ID - assign StatReg[27:24] = RevisionNo; // set revision number - assign StatReg[23:16] = 0; // reserved - assign StatReg[15] = DMAtip; - assign StatReg[14:11] = 0; - assign StatReg[10] = DMARxEmpty; - assign StatReg[9] = DMATxFull; - assign StatReg[8] = DMA_dmarq; - assign StatReg[7] = PIOtip; - assign StatReg[6] = PIOpp_full; - assign StatReg[5:1] = 0; // reserved - assign StatReg[0] = int; - - - // generate PIO compatible / command-port timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - PIO_cmdport_T1 <= #1 PIO_mode0_T1; - PIO_cmdport_T2 <= #1 PIO_mode0_T2; - PIO_cmdport_T4 <= #1 PIO_mode0_T4; - PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; - end - else if (rst_i) - begin - PIO_cmdport_T1 <= #1 PIO_mode0_T1; - PIO_cmdport_T2 <= #1 PIO_mode0_T2; - PIO_cmdport_T4 <= #1 PIO_mode0_T4; - PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; - end - else if(sel_PIO_cmdport) - begin - PIO_cmdport_T1 <= #1 dat_i[ 7: 0]; - PIO_cmdport_T2 <= #1 dat_i[15: 8]; - PIO_cmdport_T4 <= #1 dat_i[23:16]; - PIO_cmdport_Teoc <= #1 dat_i[31:24]; - end - - // generate PIO device0 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - PIO_dport0_T1 <= #1 PIO_mode0_T1; - PIO_dport0_T2 <= #1 PIO_mode0_T2; - PIO_dport0_T4 <= #1 PIO_mode0_T4; - PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; - end - else if (rst_i) - begin - PIO_dport0_T1 <= #1 PIO_mode0_T1; - PIO_dport0_T2 <= #1 PIO_mode0_T2; - PIO_dport0_T4 <= #1 PIO_mode0_T4; - PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; - end - else if(sel_PIO_dport0) - begin - PIO_dport0_T1 <= #1 dat_i[ 7: 0]; - PIO_dport0_T2 <= #1 dat_i[15: 8]; - PIO_dport0_T4 <= #1 dat_i[23:16]; - PIO_dport0_Teoc <= #1 dat_i[31:24]; - end - - // generate PIO device1 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - PIO_dport1_T1 <= #1 PIO_mode0_T1; - PIO_dport1_T2 <= #1 PIO_mode0_T2; - PIO_dport1_T4 <= #1 PIO_mode0_T4; - PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; - end - else if (rst_i) - begin - PIO_dport1_T1 <= #1 PIO_mode0_T1; - PIO_dport1_T2 <= #1 PIO_mode0_T2; - PIO_dport1_T4 <= #1 PIO_mode0_T4; - PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; - end - else if(sel_PIO_dport1) - begin - PIO_dport1_T1 <= #1 dat_i[ 7: 0]; - PIO_dport1_T2 <= #1 dat_i[15: 8]; - PIO_dport1_T4 <= #1 dat_i[23:16]; - PIO_dport1_Teoc <= #1 dat_i[31:24]; - end - - // generate DMA device0 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - DMA_dev0_Tm <= #1 DMA_mode0_Tm; - DMA_dev0_Td <= #1 DMA_mode0_Td; - DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; - end - else if (rst_i) - begin - DMA_dev0_Tm <= #1 DMA_mode0_Tm; - DMA_dev0_Td <= #1 DMA_mode0_Td; - DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; - end - else if(sel_DMA_dev0) - begin - DMA_dev0_Tm <= #1 dat_i[ 7: 0]; - DMA_dev0_Td <= #1 dat_i[15: 8]; - DMA_dev0_Teoc <= #1 dat_i[31:24]; - end - - // generate DMA device1 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - DMA_dev1_Tm <= #1 DMA_mode0_Tm; - DMA_dev1_Td <= #1 DMA_mode0_Td; - DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; - end - else if (rst_i) - begin - DMA_dev1_Tm <= #1 DMA_mode0_Tm; - DMA_dev1_Td <= #1 DMA_mode0_Td; - DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; - end - else if(sel_DMA_dev1) - begin - DMA_dev1_Tm <= #1 dat_i[ 7: 0]; - DMA_dev1_Td <= #1 dat_i[15: 8]; - DMA_dev1_Teoc <= #1 dat_i[31:24]; - end - - // - // generate WISHBONE interconnect signals - // - reg [31:0] Q; - - // generate acknowledge signal - assign ack_o = PIOack | CONsel; // | DMAack; // since DMAack is derived from CONsel this is OK - - // generate error signal - assign err_o = cyc_i & stb_i & berr; - - // generate retry signal (for OCIDEC-3 and above only) - assign rty_o = cyc_i & stb_i & brty; - - // generate interrupt signal - assign inta_o = StatReg[0]; - - // generate output multiplexor - always@(`ATA_ADR or CtrlReg or StatReg or - PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc or - PIO_dport0_T1 or PIO_dport0_T2 or PIO_dport0_T4 or PIO_dport0_Teoc or - PIO_dport1_T1 or PIO_dport1_T2 or PIO_dport1_T4 or PIO_dport1_Teoc or - DMA_dev0_Tm or DMA_dev0_Td or DMA_dev0_Teoc or - DMA_dev1_Tm or DMA_dev1_Td or DMA_dev1_Teoc or - DMAq - ) - case (`ATA_ADR) // synopsis full_case parallel_case - `ATA_CTRL_REG: Q = CtrlReg; - `ATA_STAT_REG: Q = StatReg; - `ATA_PIO_CMD : Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1}; - `ATA_PIO_DP0 : Q = {PIO_dport0_Teoc, PIO_dport0_T4, PIO_dport0_T2, PIO_dport0_T1}; - `ATA_PIO_DP1 : Q = {PIO_dport1_Teoc, PIO_dport1_T4, PIO_dport1_T2, PIO_dport1_T1}; - `ATA_DMA_DEV0: Q = {DMA_dev0_Teoc, 8'h0, DMA_dev0_Td, DMA_dev0_Tm}; - `ATA_DMA_DEV1: Q = {DMA_dev1_Teoc, 8'h0, DMA_dev1_Td, DMA_dev1_Tm}; - `ATA_DMA_PORT: Q = DMAq; - default: Q = 0; - endcase - - // assign DAT_O output - assign dat_o = `ATA_DEV_ADR ? {16'h0, PIOq} : Q; - -endmodule Index: trunk/rtl/verilog/ocidec-1/atahost_top.v =================================================================== --- trunk/rtl/verilog/ocidec-1/atahost_top.v (revision 32) +++ trunk/rtl/verilog/ocidec-1/atahost_top.v (nonexistent) @@ -1,292 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OCIDEC-1 ATA/ATAPI-5 Controller //// -//// Top Level //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: atahost_top.v,v 1.7 2002-02-18 14:25:43 rherveille Exp $ -// -// $Date: 2002-02-18 14:25:43 $ -// $Revision: 1.7 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// rev.: 1.0 June 29th, 2001. Initial Verilog release -// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list. -// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected. -// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration. -// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments. -// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention. -// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter -// -// $Log: not supported by cvs2svn $ -// Revision 1.6 2002/02/16 10:42:17 rherveille -// Added disclaimer -// Added CVS information -// Changed core for new internal counter libraries (synthesis fixes). -// -// -// -// - -///////////////////////////////////////////////////////////// -// -// DeviceType: OCIDEC-1: OpenCores IDE Controller type1 -// Features: PIO Compatible Timing -// DeviceID: 0x01 -// RevNo : 0x00 -// - -// -// Host signals: -// Reset -// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. -// DIOW- write strobe. The rising edge latches data from DD into the device. -// DA(2:0) 3bit binary coded adress -// CS0- select command block registers -// CS1- select control block registers - -`include "timescale.v" - -module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, - wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o, - resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o, - cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i); - // - // Parameter declarations - // - parameter ARST_LVL = 1'b0; // asynchronous reset level - - parameter TWIDTH = 8; // counter width - // PIO mode 0 settings (@100MHz clock) - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - // - // inputs & outputs - // - - // WISHBONE SYSCON signals - input wb_clk_i; // master clock in - input arst_i; // asynchronous reset - input wb_rst_i; // synchronous reset - - // WISHBONE SLAVE signals - input wb_cyc_i; // valid bus cycle input - input wb_stb_i; // strobe/core select input - output wb_ack_o; // strobe acknowledge output - output wb_err_o; // error output - input [6:2] wb_adr_i; // A6 = '1' ATA devices selected - // A5 = '1' CS1- asserted, '0' CS0- asserted - // A4..A2 ATA address lines - // A6 = '0' ATA controller selected - input [31:0] wb_dat_i; // Databus in - output [31:0] wb_dat_o; // Databus out - input [ 3:0] wb_sel_i; // Byte select signals - input wb_we_i; // Write enable input - output wb_inta_o; // interrupt request signal - - // ATA signals - output resetn_pad_o; - input [15:0] dd_pad_i; - output [15:0] dd_pad_o; - output dd_padoe_o; - output [ 2:0] da_pad_o; - output cs0n_pad_o; - output cs1n_pad_o; - - output diorn_pad_o; - output diown_pad_o; - input iordy_pad_i; - input intrq_pad_i; - - // - // constant declarations - // - parameter [3:0] DeviceId = 4'h1; - parameter [3:0] RevisionNo = 4'h0; - - // - // Variable declarations - // - - // registers - wire IDEctrl_IDEen, IDEctrl_rst; - wire [ 7:0] PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc; - wire PIO_cmdport_IORDYen; - - wire PIOack; - wire [15:0] PIOq; - - wire irq; // ATA bus IRQ signal - - - ///////////////// - // Module body // - ///////////////// - - // generate asynchronous reset level - // arst_signal is either a wire or a NOT-gate - wire arst_signal = arst_i ^ ARST_LVL; - - // - // hookup wishbone slave - // - atahost_wb_slave #(DeviceId, RevisionNo, PIO_mode0_T1, - PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc, 0, 0, 0) - u0 ( - // WISHBONE SYSCON signals - .clk_i(wb_clk_i), - .arst_i(arst_signal), - .rst_i(wb_rst_i), - - // WISHBONE SLAVE signals - .cyc_i(wb_cyc_i), - .stb_i(wb_stb_i), - .ack_o(wb_ack_o), - .rty_o(), - .err_o(wb_err_o), - .adr_i(wb_adr_i), - .dat_i(wb_dat_i), - .dat_o(wb_dat_o), - .sel_i(wb_sel_i), - .we_i(wb_we_i), - .inta_o(wb_inta_o), - - // PIO control inputs - .PIOsel(PIOsel), - // PIOtip is only asserted during a PIO transfer (No shit! ;) - // Since it is impossible to read the status register and access the PIO registers at the same time - // this bit is useless (besides using-up resources) - .PIOtip(1'b0), - .PIOack(PIOack), - .PIOq(PIOq), - .PIOpp_full(1'b0), // OCIDEC-1 does not support PIO-write pingpong, negate signal - .irq(irq), - - // DMA control inputs (negate all of them, OCIDEC-1 does not support DMA) - .DMAsel(), - .DMAtip(1'b0), - .DMAack(1'b0), - .DMARxEmpty(1'b0), - .DMATxFull(1'b0), - .DMA_dmarq(1'b0), - .DMAq(32'h0), - - // outputs - // control register outputs - .IDEctrl_rst(IDEctrl_rst), - .IDEctrl_IDEen(IDEctrl_IDEen), - .IDEctrl_FATR0(), - .IDEctrl_FATR1(), - .IDEctrl_ppen(), - - .DMActrl_DMAen(), - .DMActrl_dir(), - .DMActrl_BeLeC0(), - .DMActrl_BeLeC1(), - - // CMD port timing registers - .PIO_cmdport_T1(PIO_cmdport_T1), - .PIO_cmdport_T2(PIO_cmdport_T2), - .PIO_cmdport_T4(PIO_cmdport_T4), - .PIO_cmdport_Teoc(PIO_cmdport_Teoc), - .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen), - - // data-port0 timing registers - .PIO_dport0_T1(), - .PIO_dport0_T2(), - .PIO_dport0_T4(), - .PIO_dport0_Teoc(), - .PIO_dport0_IORDYen(), - - // data-port1 timing registers - .PIO_dport1_T1(), - .PIO_dport1_T2(), - .PIO_dport1_T4(), - .PIO_dport1_Teoc(), - .PIO_dport1_IORDYen(), - - // DMA device0 timing registers - .DMA_dev0_Tm(), - .DMA_dev0_Td(), - .DMA_dev0_Teoc(), - - // DMA device1 timing registers - .DMA_dev1_Tm(), - .DMA_dev1_Td(), - .DMA_dev1_Teoc() - ); - - - // - // hookup controller section - // - atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) - u1 ( - .clk(wb_clk_i), - .nReset(arst_signal), - .rst(wb_rst_i), - .irq(irq), - .IDEctrl_rst(IDEctrl_rst), - .IDEctrl_IDEen(IDEctrl_IDEen), - .PIO_cmdport_T1(PIO_cmdport_T1), - .PIO_cmdport_T2(PIO_cmdport_T2), - .PIO_cmdport_T4(PIO_cmdport_T4), - .PIO_cmdport_Teoc(PIO_cmdport_Teoc), - .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen), - .PIOreq(PIOsel), - .PIOack(PIOack), - .PIOa(wb_adr_i[5:2]), - .PIOd(wb_dat_i[15:0]), - .PIOq(PIOq), - .PIOwe(wb_we_i), - .RESETn(resetn_pad_o), - .DDi(dd_pad_i), - .DDo(dd_pad_o), - .DDoe(dd_padoe_o), - .DA(da_pad_o), - .CS0n(cs0n_pad_o), - .CS1n(cs1n_pad_o), - .DIORn(diorn_pad_o), - .DIOWn(diown_pad_o), - .IORDY(iordy_pad_i), - .INTRQ(intrq_pad_i) - ); - -endmodule Index: trunk/rtl/verilog/ocidec-2/revision_history.txt =================================================================== --- trunk/rtl/verilog/ocidec-2/revision_history.txt (revision 32) +++ trunk/rtl/verilog/ocidec-2/revision_history.txt (nonexistent) @@ -1,14 +0,0 @@ ------------------------------ -Revision: 1.0 -Date: februar 18th, 2002 -Author: Richard Herveille -- initial Verilog release ------------------------------ - ------------------------------ -Revision: 1.1 -Date: May 19th, 2002. -Author: Richard Herveille -- Fixed a potential bug that forced the core into an unknown state - when an asynchronous reset was given without a running clock ------------------------------ Index: trunk/rtl/verilog/ocidec-2/ud_cnt.v =================================================================== --- trunk/rtl/verilog/ocidec-2/ud_cnt.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/ud_cnt.v (nonexistent) @@ -1,105 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Generic Up/Down counter //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: ud_cnt.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ -// -// $Date: 2002-02-18 14:26:46 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/02/16 10:42:17 rherveille -// Added disclaimer -// Added CVS information -// Changed core for new internal counter libraries (synthesis fixes). -// -// - - -///////////////////////////// -// general purpose counter // -///////////////////////////// - -`include "timescale.v" - -module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco); - // parameter declaration - parameter SIZE = 8; - parameter RESD = {SIZE{1'b0}}; // data after reset - - // inputs & outputs - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - input cnt_en; // count enable - input ud; // up/not down - input nld; // synchronous active low load - input [SIZE-1:0] d; // load counter value - output [SIZE-1:0] q; // current counter value - input rci; // carry input - output rco; // carry output - - // variable declarations - reg [SIZE-1:0] Qi; // intermediate value - wire [SIZE:0] val; // carry+result - - // - // Module body - // - - assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci); - - always@(posedge clk or negedge nReset) - begin - if (~nReset) - Qi <= #1 RESD; - else if (rst) - Qi <= #1 RESD; - else if (~nld) - Qi <= #1 d; - else if (cnt_en) - Qi <= #1 val[SIZE-1:0]; - end - - // assign outputs - assign q = Qi; - assign rco = val[SIZE]; -endmodule - - Index: trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v =================================================================== --- trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v (nonexistent) @@ -1,197 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores ATA/ATAPI-5 Host Controller //// -//// PIO Access Controller (common for OCIDEC 2 and above) //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// -// CVS Log -// -// $Id: atahost_pio_actrl.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ -// -// $Date: 2002-02-18 14:26:46 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ - -`include "timescale.v" - -module atahost_pio_actrl ( - clk, nReset, rst, IDEctrl_FATR0, IDEctrl_FATR1, - cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen, - dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen, - dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen, - SelDev, go, done, dir, a, q, DDi, oe, DIOR, DIOW, IORDY - ); - - // - // parameters - // - parameter TWIDTH = 8; - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns - - // - // inputs & outputs - // - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - - input IDEctrl_FATR0; - input IDEctrl_FATR1; - - input [7:0] cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc; - input cmdport_IORDYen; // PIO command port / non-fast timing - - input [7:0] dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc; - input dport0_IORDYen; // PIO mode data-port / fast timing device 0 - - input [7:0] dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc; - input dport1_IORDYen; // PIO mode data-port / fast timing device 1 - - input SelDev; // Selected device - - input go; // Start transfer sequence - output done; // Transfer sequence done - input dir; // Transfer direction '1'=write, '0'=read - input [ 3:0] a; // PIO transfer address - output [15:0] q; // Data read from ATA devices - reg [15:0] q; - - input [15:0] DDi; // Data from ATA DD bus - output oe; // DDbus output-enable signal - - output DIOR; - output DIOW; - input IORDY; - - // - // signals & variables - // - wire dstrb; - reg [7:0] T1, T2, T4, Teoc; - reg IORDYen; - - - // - // Module body - // - - // PIO transfer control - // - // capture ATA data for PIO access - always@(posedge clk) - if (dstrb) - q <= DDi; - - - // PIO timing controllers - // - // select timing settings for the addressed port - always@(posedge clk) - if (|a) // command ports accessed ? - begin - T1 <= #1 cmdport_T1; - T2 <= #1 cmdport_T2; - T4 <= #1 cmdport_T4; - Teoc <= #1 cmdport_Teoc; - IORDYen <= #1 cmdport_IORDYen; - end - else // data ports accessed - begin - if (SelDev & IDEctrl_FATR1) - begin - T1 <= #1 dport1_T1; - T2 <= #1 dport1_T2; - T4 <= #1 dport1_T4; - Teoc <= #1 dport1_Teoc; - IORDYen <= #1 dport1_IORDYen; - end - else if (!SelDev & IDEctrl_FATR0) - begin - T1 <= #1 dport0_T1; - T2 <= #1 dport0_T2; - T4 <= #1 dport0_T4; - Teoc <= #1 dport0_Teoc; - IORDYen <= #1 dport0_IORDYen; - end - else - begin - T1 <= #1 cmdport_T1; - T2 <= #1 cmdport_T2; - T4 <= #1 cmdport_T4; - Teoc <= #1 cmdport_Teoc; - IORDYen <= #1 cmdport_IORDYen; - end - end - - // - // hookup timing controller - // - atahost_pio_tctrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) - PIO_timing_controller ( - .clk(clk), - .nReset(nReset), - .rst(rst), - .IORDY_en(IORDYen), - .T1(T1), - .T2(T2), - .T4(T4), - .Teoc(Teoc), - .go(go), - .we(dir), - .oe(oe), - .done(done), - .dstrb(dstrb), - .DIOR(DIOR), - .DIOW(DIOW), - .IORDY(IORDY) - ); - -endmodule - Index: trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v =================================================================== --- trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v (nonexistent) @@ -1,265 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores ATA/ATAPI-5 Host Controller //// -//// PIO Timing Controller (common for all OCIDEC cores) //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: atahost_pio_tctrl.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ -// -// $Date: 2002-02-18 14:26:46 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// Rev. 1.0 June 27th, 2001. Initial Verilog release -// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues. -// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation. -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/02/16 10:42:17 rherveille -// Added disclaimer -// Added CVS information -// Changed core for new internal counter libraries (synthesis fixes). -// -// - - -// -// Timing PIO mode transfers -//-------------------------------------------- -// T0: cycle time -// T1: address valid to DIOR-/DIOW- -// T2: DIOR-/DIOW- pulse width -// T2i: DIOR-/DIOW- recovery time -// T3: DIOW- data setup -// T4: DIOW- data hold -// T5: DIOR- data setup -// T6: DIOR- data hold -// T9: address hold from DIOR-/DIOW- negated -// Trd: Read data valid to IORDY asserted -// Ta: IORDY setup time -// Tb: IORDY pulse width -// -// Transfer sequence -//-------------------------------- -// 1) set address (DA, CS0-, CS1-) -// 2) wait for T1 -// 3) assert DIOR-/DIOW- -// when write action present Data (timing spec. T3 always honored), enable output enable-signal -// 4) wait for T2 -// 5) check IORDY -// when not IORDY goto 5 -// when IORDY negate DIOW-/DIOR-, latch data (if read action) -// when write, hold data for T4, disable output-enable signal -// 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest -// 7) start new cycle - -`include "timescale.v" - -module atahost_pio_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY); - // parameter declarations - parameter TWIDTH = 8; - parameter PIO_MODE0_T1 = 6; // 70ns - parameter PIO_MODE0_T2 = 28; // 290ns - parameter PIO_MODE0_T4 = 2; // 30ns - parameter PIO_MODE0_Teoc = 23; // 240ns - - // inputs & outputs - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - - // timing & control register settings - input IORDY_en; // use IORDY (or not) - input [TWIDTH-1:0] T1; // T1 time (in clk-ticks) - input [TWIDTH-1:0] T2; // T1 time (in clk-ticks) - input [TWIDTH-1:0] T4; // T1 time (in clk-ticks) - input [TWIDTH-1:0] Teoc; // T1 time (in clk-ticks) - - // control signals - input go; // PIO controller selected (strobe signal) - input we; // write enable signal. 1'b0 == read, 1'b1 == write - - // return signals - output oe; // output enable signal - reg oe; - output done; // finished cycle - output dstrb; // data strobe, latch data (during read) - reg dstrb; - - // ata signals - output DIOR; // IOread signal, active high - reg DIOR; - output DIOW; // IOwrite signal, active high - reg DIOW; - input IORDY; // IOrDY signal - - - // - // constant declarations - // - // PIO mode 0 settings (@100MHz clock) - wire [TWIDTH-1:0] T1_m0 = PIO_MODE0_T1; - wire [TWIDTH-1:0] T2_m0 = PIO_MODE0_T2; - wire [TWIDTH-1:0] T4_m0 = PIO_MODE0_T4; - wire [TWIDTH-1:0] Teoc_m0 = PIO_MODE0_Teoc; - - // - // variable declaration - // - reg busy, hold_go; - wire igo; - wire T1done, T2done, T4done, Teoc_done, IORDY_done; - reg hT2done; - - // - // module body - // - - // generate internal go strobe - // strecht go until ready for new cycle - always@(posedge clk or negedge nReset) - if (~nReset) - begin - busy <= #1 1'b0; - hold_go <= #1 1'b0; - end - else if (rst) - begin - busy <= #1 1'b0; - hold_go <= #1 1'b0; - end - else - begin - busy <= #1 (igo | busy) & !Teoc_done; - hold_go <= #1 (go | (hold_go & busy)) & !igo; - end - - assign igo = (go | hold_go) & !busy; - - // 1) hookup T1 counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1) - t1_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(igo), - .d(T1), - .q(), - .done(T1done) - ); - - // 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device - always@(posedge clk or negedge nReset) - if (~nReset) - begin - DIOR <= #1 1'b0; - DIOW <= #1 1'b0; - oe <= #1 1'b0; - end - else if (rst) - begin - DIOR <= #1 1'b0; - DIOW <= #1 1'b0; - oe <= #1 1'b0; - end - else - begin - DIOR <= #1 (!we & T1done) | (DIOR & !IORDY_done); - DIOW <= #1 ( we & T1done) | (DIOW & !IORDY_done); - oe <= #1 ( (we & igo) | oe) & !T4done; // negate oe when t4-done - end - - // 3) hookup T2 counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2) - t2_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(T1done), - .d(T2), - .q(), - .done(T2done) - ); - - // 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) - // hold T2done - always@(posedge clk or negedge nReset) - if (~nReset) - hT2done <= #1 1'b0; - else if (rst) - hT2done <= #1 1'b0; - else - hT2done <= #1 (T2done | hT2done) & !IORDY_done; - - assign IORDY_done = (T2done | hT2done) & (IORDY | !IORDY_en); - - // generate datastrobe, capture data at rising DIOR- edge - always@(posedge clk) - dstrb <= #1 IORDY_done; - - // hookup data hold counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4) - dhold_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(IORDY_done), - .d(T4), - .q(), - .done(T4done) - ); - - assign done = T4done; // placing done here provides the fastest return possible, - // while still guaranteeing data and address hold-times - - // 5) hookup end_of_cycle counter - ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc) - eoc_cnt( - .clk(clk), - .rst(rst), - .nReset(nReset), - .cnt_en(1'b1), - .go(IORDY_done), - .d(Teoc), - .q(), - .done(Teoc_done) - ); - -endmodule Index: trunk/rtl/verilog/ocidec-2/ro_cnt.v =================================================================== --- trunk/rtl/verilog/ocidec-2/ro_cnt.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/ro_cnt.v (nonexistent) @@ -1,111 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// Run-Once counter //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: ro_cnt.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ -// -// $Date: 2002-02-18 14:26:46 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2002/02/16 10:42:17 rherveille -// Added disclaimer -// Added CVS information -// Changed core for new internal counter libraries (synthesis fixes). -// -// - - -/////////////////////////// -// run-once down-counter // -/////////////////////////// - -// counts D+1 cycles before generating 'DONE' - -`include "timescale.v" - -module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q); - - // parameter declaration - parameter SIZE = 8; - - parameter UD = 1'b0; // default count down - parameter ID = {SIZE{1'b0}}; // initial data after reset - - // inputs & outputs - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - input cnt_en; // count enable - input go; // load counter and start sequence - output done; // done counting - input [SIZE-1:0] d; // load counter value - output [SIZE-1:0] q; // current counter value - - // variable declarations - reg rci; - wire nld, rco; - - // - // module body - // - - always@(posedge clk or negedge nReset) - if (~nReset) - rci <= #1 1'b0; - else if (rst) - rci <= #1 1'b0; - else //if (cnt_en) - rci <= #1 go | (rci & !rco); - - assign nld = !go; - - // hookup counter - ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en), - .ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco)); - - - // assign outputs - - assign done = rco; - -endmodule - - - Index: trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v =================================================================== --- trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v (nonexistent) @@ -1,484 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OCIDEC-1 ATA/ATAPI-5 Controller //// -//// Wishbone Slave interface (common for all OCIDEC cores) //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// -// CVS Log -// -// $Id: atahost_wb_slave.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ -// -// $Date: 2002-02-18 14:26:46 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// - -`include "timescale.v" - -module atahost_wb_slave ( - clk_i, arst_i, rst_i, cyc_i, stb_i, ack_o, rty_o, err_o, adr_i, dat_i, dat_o, sel_i, we_i, inta_o, - PIOsel, PIOtip, PIOack, PIOq, PIOpp_full, irq, - DMAsel, DMAtip, DMAack, DMARxEmpty, DMATxFull, DMA_dmarq, DMAq, - IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR1, IDEctrl_FATR0, IDEctrl_ppen, - DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1, - PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, - PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc, PIO_dport0_IORDYen, - PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc, PIO_dport1_IORDYen, - DMA_dev0_Tm, DMA_dev0_Td, DMA_dev0_Teoc, DMA_dev1_Tm, DMA_dev1_Td, DMA_dev1_Teoc - ); - - // - // Parameters - // - parameter DeviceId = 4'h0; - parameter RevisionNo = 4'h0; - - // PIO mode 0 settings (@100MHz clock) - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - // Multiword DMA mode 0 settings (@100MHz clock) - parameter DMA_mode0_Tm = 6; // 50ns - parameter DMA_mode0_Td = 21; // 215ns - parameter DMA_mode0_Teoc = 21; // 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - - // - // inputs & outputs - // - - // WISHBONE SYSCON signals - input clk_i; // master clock in - input arst_i; // asynchronous active low reset - input rst_i; // synchronous active high reset - - // WISHBONE SLAVE signals - input cyc_i; // valid bus cycle input - input stb_i; // strobe/core select input - output ack_o; // strobe acknowledge output - output rty_o; // retry output - output err_o; // error output - input [6:2] adr_i; // A6 = '1' ATA devices selected - // A5 = '1' CS1- asserted, '0' CS0- asserted - // A4..A2 ATA address lines - // A6 = '0' ATA controller selected - input [31:0] dat_i; // Databus in - output [31:0] dat_o; // Databus out - input [ 3:0] sel_i; // Byte select signals - input we_i; // Write enable input - output inta_o; // interrupt request signal IDE0 - - // PIO control input - output PIOsel; - input PIOtip; // PIO transfer in progress - input PIOack; // PIO acknowledge signal - input [15:0] PIOq; // PIO data input - input PIOpp_full; // PIO write-ping-pong buffers full - input irq; // interrupt signal input - - // DMA control inputs - output DMAsel; - input DMAtip; // DMA transfer in progress - input DMAack; // DMA transfer acknowledge - input DMARxEmpty; // DMA receive buffer empty - input DMATxFull; // DMA transmit buffer full - input DMA_dmarq; // wishbone DMA request - input [31:0] DMAq; - - // outputs - // control register outputs - output IDEctrl_rst; - output IDEctrl_IDEen; - output IDEctrl_FATR1; - output IDEctrl_FATR0; - output IDEctrl_ppen; - output DMActrl_DMAen; - output DMActrl_dir; - output DMActrl_BeLeC0; - output DMActrl_BeLeC1; - - // CMD port timing registers - output [7:0] PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc; - output PIO_cmdport_IORDYen; - - reg [7:0] PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc; - - // data-port0 timing registers - output [7:0] PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc; - output PIO_dport0_IORDYen; - - reg [7:0] PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc; - - // data-port1 timing registers - output [7:0] PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc; - output PIO_dport1_IORDYen; - - reg [7:0] PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc; - - // DMA device0 timing registers - output [7:0] DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc; - - reg [7:0] DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc; - - // DMA device1 timing registers - output [7:0] DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc; - - reg [7:0] DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc; - - - // - // constants - // - - // addresses - `define ATA_DEV_ADR adr_i[6] - `define ATA_ADR adr_i[5:2] - - `define ATA_CTRL_REG 4'b0000 - `define ATA_STAT_REG 4'b0001 - `define ATA_PIO_CMD 4'b0010 - `define ATA_PIO_DP0 4'b0011 - `define ATA_PIO_DP1 4'b0100 - `define ATA_DMA_DEV0 4'b0101 - `define ATA_DMA_DEV1 4'b0110 - // reserved // - `define ATA_DMA_PORT 4'b1111 - - - // - // signals - // - - // registers - reg [31:0] CtrlReg; // control register - wire [31:0] StatReg; // status register - - // store ping-pong-full signal - reg store_pp_full; - - - // - // generate bus cycle / address decoder - // - wire w_acc = &sel_i[1:0]; // word access - wire dw_acc = &sel_i; // double word access - - // bus error - wire berr = `ATA_DEV_ADR ? !w_acc : !dw_acc; - - // PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong-full - wire PIOsel = cyc_i & stb_i & `ATA_DEV_ADR & w_acc & !(DMAtip | store_pp_full); - - // CON accesses only 32bit wide - wire CONsel = cyc_i & stb_i & !(`ATA_DEV_ADR) & dw_acc; - wire DMAsel = CONsel & (`ATA_ADR == `ATA_DMA_PORT); - - // bus retry (OCIDEC-3 and above) - // store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle - always@(posedge clk_i) - if (!PIOsel) - store_pp_full <= #1 PIOpp_full; - - wire brty = (`ATA_DEV_ADR & w_acc) & (DMAtip | store_pp_full); - - // - // generate registers - // - - // generate register select signals - wire sel_ctrl = CONsel & we_i & (`ATA_ADR == `ATA_CTRL_REG); - wire sel_stat = CONsel & we_i & (`ATA_ADR == `ATA_STAT_REG); - wire sel_PIO_cmdport = CONsel & we_i & (`ATA_ADR == `ATA_PIO_CMD); - wire sel_PIO_dport0 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP0); - wire sel_PIO_dport1 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP1); - wire sel_DMA_dev0 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV0); - wire sel_DMA_dev1 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV1); - // reserved 0x1c-0x38 - // reserved 0x3c : DMA-port - - - // generate control register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - CtrlReg[31:1] <= #1 0; - CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) - end - else if (rst_i) - begin - CtrlReg[31:1] <= #1 0; - CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) - end - else if (sel_ctrl) - CtrlReg <= #1 dat_i; - - // assign bits - assign DMActrl_DMAen = CtrlReg[15]; - assign DMActrl_dir = CtrlReg[13]; - assign DMActrl_BeLeC1 = CtrlReg[9]; - assign DMActrl_BeLeC0 = CtrlReg[8]; - assign IDEctrl_IDEen = CtrlReg[7]; - assign IDEctrl_FATR1 = CtrlReg[6]; - assign IDEctrl_FATR0 = CtrlReg[5]; - assign IDEctrl_ppen = CtrlReg[4]; - assign PIO_dport1_IORDYen = CtrlReg[3]; - assign PIO_dport0_IORDYen = CtrlReg[2]; - assign PIO_cmdport_IORDYen = CtrlReg[1]; - assign IDEctrl_rst = CtrlReg[0]; - - - // generate status register clearable bits - reg dirq, int; - - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - int <= #1 1'b0; - dirq <= #1 1'b0; - end - else if (rst_i) - begin - int <= #1 1'b0; - dirq <= #1 1'b0; - end - else - begin - int <= #1 (int | (irq & !dirq)) & !(sel_stat & !dat_i[0]); - dirq <= #1 irq; - end - - // assign status bits - assign StatReg[31:28] = DeviceId; // set Device ID - assign StatReg[27:24] = RevisionNo; // set revision number - assign StatReg[23:16] = 0; // reserved - assign StatReg[15] = DMAtip; - assign StatReg[14:11] = 0; - assign StatReg[10] = DMARxEmpty; - assign StatReg[9] = DMATxFull; - assign StatReg[8] = DMA_dmarq; - assign StatReg[7] = PIOtip; - assign StatReg[6] = PIOpp_full; - assign StatReg[5:1] = 0; // reserved - assign StatReg[0] = int; - - - // generate PIO compatible / command-port timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - PIO_cmdport_T1 <= #1 PIO_mode0_T1; - PIO_cmdport_T2 <= #1 PIO_mode0_T2; - PIO_cmdport_T4 <= #1 PIO_mode0_T4; - PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; - end - else if (rst_i) - begin - PIO_cmdport_T1 <= #1 PIO_mode0_T1; - PIO_cmdport_T2 <= #1 PIO_mode0_T2; - PIO_cmdport_T4 <= #1 PIO_mode0_T4; - PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; - end - else if(sel_PIO_cmdport) - begin - PIO_cmdport_T1 <= #1 dat_i[ 7: 0]; - PIO_cmdport_T2 <= #1 dat_i[15: 8]; - PIO_cmdport_T4 <= #1 dat_i[23:16]; - PIO_cmdport_Teoc <= #1 dat_i[31:24]; - end - - // generate PIO device0 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - PIO_dport0_T1 <= #1 PIO_mode0_T1; - PIO_dport0_T2 <= #1 PIO_mode0_T2; - PIO_dport0_T4 <= #1 PIO_mode0_T4; - PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; - end - else if (rst_i) - begin - PIO_dport0_T1 <= #1 PIO_mode0_T1; - PIO_dport0_T2 <= #1 PIO_mode0_T2; - PIO_dport0_T4 <= #1 PIO_mode0_T4; - PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; - end - else if(sel_PIO_dport0) - begin - PIO_dport0_T1 <= #1 dat_i[ 7: 0]; - PIO_dport0_T2 <= #1 dat_i[15: 8]; - PIO_dport0_T4 <= #1 dat_i[23:16]; - PIO_dport0_Teoc <= #1 dat_i[31:24]; - end - - // generate PIO device1 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - PIO_dport1_T1 <= #1 PIO_mode0_T1; - PIO_dport1_T2 <= #1 PIO_mode0_T2; - PIO_dport1_T4 <= #1 PIO_mode0_T4; - PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; - end - else if (rst_i) - begin - PIO_dport1_T1 <= #1 PIO_mode0_T1; - PIO_dport1_T2 <= #1 PIO_mode0_T2; - PIO_dport1_T4 <= #1 PIO_mode0_T4; - PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; - end - else if(sel_PIO_dport1) - begin - PIO_dport1_T1 <= #1 dat_i[ 7: 0]; - PIO_dport1_T2 <= #1 dat_i[15: 8]; - PIO_dport1_T4 <= #1 dat_i[23:16]; - PIO_dport1_Teoc <= #1 dat_i[31:24]; - end - - // generate DMA device0 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - DMA_dev0_Tm <= #1 DMA_mode0_Tm; - DMA_dev0_Td <= #1 DMA_mode0_Td; - DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; - end - else if (rst_i) - begin - DMA_dev0_Tm <= #1 DMA_mode0_Tm; - DMA_dev0_Td <= #1 DMA_mode0_Td; - DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; - end - else if(sel_DMA_dev0) - begin - DMA_dev0_Tm <= #1 dat_i[ 7: 0]; - DMA_dev0_Td <= #1 dat_i[15: 8]; - DMA_dev0_Teoc <= #1 dat_i[31:24]; - end - - // generate DMA device1 timing register - always@(posedge clk_i or negedge arst_i) - if (~arst_i) - begin - DMA_dev1_Tm <= #1 DMA_mode0_Tm; - DMA_dev1_Td <= #1 DMA_mode0_Td; - DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; - end - else if (rst_i) - begin - DMA_dev1_Tm <= #1 DMA_mode0_Tm; - DMA_dev1_Td <= #1 DMA_mode0_Td; - DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; - end - else if(sel_DMA_dev1) - begin - DMA_dev1_Tm <= #1 dat_i[ 7: 0]; - DMA_dev1_Td <= #1 dat_i[15: 8]; - DMA_dev1_Teoc <= #1 dat_i[31:24]; - end - - // - // generate WISHBONE interconnect signals - // - reg [31:0] Q; - - // generate acknowledge signal - assign ack_o = PIOack | CONsel; // | DMAack; // since DMAack is derived from CONsel this is OK - - // generate error signal - assign err_o = cyc_i & stb_i & berr; - - // generate retry signal (for OCIDEC-3 and above only) - assign rty_o = cyc_i & stb_i & brty; - - // generate interrupt signal - assign inta_o = StatReg[0]; - - // generate output multiplexor - always@(`ATA_ADR or CtrlReg or StatReg or - PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc or - PIO_dport0_T1 or PIO_dport0_T2 or PIO_dport0_T4 or PIO_dport0_Teoc or - PIO_dport1_T1 or PIO_dport1_T2 or PIO_dport1_T4 or PIO_dport1_Teoc or - DMA_dev0_Tm or DMA_dev0_Td or DMA_dev0_Teoc or - DMA_dev1_Tm or DMA_dev1_Td or DMA_dev1_Teoc or - DMAq - ) - case (`ATA_ADR) // synopsis full_case parallel_case - `ATA_CTRL_REG: Q = CtrlReg; - `ATA_STAT_REG: Q = StatReg; - `ATA_PIO_CMD : Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1}; - `ATA_PIO_DP0 : Q = {PIO_dport0_Teoc, PIO_dport0_T4, PIO_dport0_T2, PIO_dport0_T1}; - `ATA_PIO_DP1 : Q = {PIO_dport1_Teoc, PIO_dport1_T4, PIO_dport1_T2, PIO_dport1_T1}; - `ATA_DMA_DEV0: Q = {DMA_dev0_Teoc, 8'h0, DMA_dev0_Td, DMA_dev0_Tm}; - `ATA_DMA_DEV1: Q = {DMA_dev1_Teoc, 8'h0, DMA_dev1_Td, DMA_dev1_Tm}; - `ATA_DMA_PORT: Q = DMAq; - default: Q = 0; - endcase - - // assign DAT_O output - assign dat_o = `ATA_DEV_ADR ? {16'h0, PIOq} : Q; - -endmodule - - Index: trunk/rtl/verilog/ocidec-2/atahost_top.v =================================================================== --- trunk/rtl/verilog/ocidec-2/atahost_top.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/atahost_top.v (nonexistent) @@ -1,296 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores ATA/ATAPI-5 Host Controller //// -//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) Top Level //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// -// CVS Log -// -// $Id: atahost_top.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ -// -// $Date: 2002-02-18 14:26:46 $ -// $Revision: 1.1 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// - -// -// DeviceType: OCIDEC-2: OpenCores IDE Controller type2 -// Features: PIO Compatible Timing, PIO Fast Timing 0/1 -// DeviceID: 0x02 -// RevNo : 0x00 -// - -// -// Host signals: -// Reset -// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. -// DIOW- write strobe. The rising edge latches data from DD into the device. -// DA(2:0) 3bit binary coded adress -// CS0- select command block registers -// CS1- select control block registers -// - -`include "timescale.v" - -module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, - wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o, - resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o, - cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i); - // - // Parameter declarations - // - parameter ARST_LVL = 1'b0; // asynchronous reset level - - parameter TWIDTH = 8; // counter width - // PIO mode 0 settings (@100MHz clock) - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - // - // inputs & outputs - // - - // WISHBONE SYSCON signals - input wb_clk_i; // master clock in - input arst_i; // asynchronous reset - input wb_rst_i; // synchronous reset - - // WISHBONE SLAVE signals - input wb_cyc_i; // valid bus cycle input - input wb_stb_i; // strobe/core select input - output wb_ack_o; // strobe acknowledge output - output wb_err_o; // error output - input [6:2] wb_adr_i; // A6 = '1' ATA devices selected - // A5 = '1' CS1- asserted, '0' CS0- asserted - // A4..A2 ATA address lines - // A6 = '0' ATA controller selected - input [31:0] wb_dat_i; // Databus in - output [31:0] wb_dat_o; // Databus out - input [ 3:0] wb_sel_i; // Byte select signals - input wb_we_i; // Write enable input - output wb_inta_o; // interrupt request signal - - // ATA signals - output resetn_pad_o; - input [15:0] dd_pad_i; - output [15:0] dd_pad_o; - output dd_padoe_o; - output [ 2:0] da_pad_o; - output cs0n_pad_o; - output cs1n_pad_o; - - output diorn_pad_o; - output diown_pad_o; - input iordy_pad_i; - input intrq_pad_i; - - // - // constant declarations - // - parameter [3:0] DeviceId = 4'h2; - parameter [3:0] RevisionNo = 4'h0; - - // - // Variable declarations - // - - // registers - wire IDEctrl_IDEen, IDEctrl_rst; - wire IDEctrl_FATR0, IDEctrl_FATR1; - wire [ 7:0] PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc; - wire PIO_cmdport_IORDYen; - wire [ 7:0] PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc; - wire PIO_dport0_IORDYen; - wire [ 7:0] PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc; - wire PIO_dport1_IORDYen; - - wire PIOack; - wire [15:0] PIOq; - - wire irq; // ATA bus IRQ signal - - - ///////////////// - // Module body // - ///////////////// - - // generate asynchronous reset level - // arst_signal is either a wire or a NOT-gate - wire arst_signal = arst_i ^ ARST_LVL; - - // - // hookup wishbone slave - // - atahost_wb_slave #(DeviceId, RevisionNo, PIO_mode0_T1, - PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc, 0, 0, 0) - u0 ( - // WISHBONE SYSCON signals - .clk_i(wb_clk_i), - .arst_i(arst_signal), - .rst_i(wb_rst_i), - - // WISHBONE SLAVE signals - .cyc_i(wb_cyc_i), - .stb_i(wb_stb_i), - .ack_o(wb_ack_o), - .rty_o(), - .err_o(wb_err_o), - .adr_i(wb_adr_i), - .dat_i(wb_dat_i), - .dat_o(wb_dat_o), - .sel_i(wb_sel_i), - .we_i(wb_we_i), - .inta_o(wb_inta_o), - - // PIO control inputs - .PIOsel(PIOsel), - // PIOtip is only asserted during a PIO transfer (No shit! ;) - // Since it is impossible to read the status register and access the PIO registers at the same time - // this bit is useless (besides using-up resources) - .PIOtip(1'b0), - .PIOack(PIOack), - .PIOq(PIOq), - .PIOpp_full(1'b0), // OCIDEC-2 does not support PIO-write pingpong, negate signal - .irq(irq), - - // DMA control inputs (negate all of them, OCIDEC-2 does not support DMA) - .DMAsel(), - .DMAtip(1'b0), - .DMAack(1'b0), - .DMARxEmpty(1'b0), - .DMATxFull(1'b0), - .DMA_dmarq(1'b0), - .DMAq(32'h0), - - // outputs - // control register outputs - .IDEctrl_rst(IDEctrl_rst), - .IDEctrl_IDEen(IDEctrl_IDEen), - .IDEctrl_FATR0(IDEctrl_FATR0), - .IDEctrl_FATR1(IDEctrl_FATR1), - .IDEctrl_ppen(), - - .DMActrl_DMAen(), - .DMActrl_dir(), - .DMActrl_BeLeC0(), - .DMActrl_BeLeC1(), - - // CMD port timing registers - .PIO_cmdport_T1(PIO_cmdport_T1), - .PIO_cmdport_T2(PIO_cmdport_T2), - .PIO_cmdport_T4(PIO_cmdport_T4), - .PIO_cmdport_Teoc(PIO_cmdport_Teoc), - .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen), - - // data-port0 timing registers - .PIO_dport0_T1(PIO_dport0_T1), - .PIO_dport0_T2(PIO_dport0_T2), - .PIO_dport0_T4(PIO_dport0_T4), - .PIO_dport0_Teoc(PIO_dport0_Teoc), - .PIO_dport0_IORDYen(PIO_dport0_IORDYen), - - // data-port1 timing registers - .PIO_dport1_T1(PIO_dport1_T1), - .PIO_dport1_T2(PIO_dport1_T2), - .PIO_dport1_T4(PIO_dport1_T4), - .PIO_dport1_Teoc(PIO_dport1_Teoc), - .PIO_dport1_IORDYen(PIO_dport1_IORDYen), - - // DMA device0 timing registers - .DMA_dev0_Tm(), - .DMA_dev0_Td(), - .DMA_dev0_Teoc(), - - // DMA device1 timing registers - .DMA_dev1_Tm(), - .DMA_dev1_Td(), - .DMA_dev1_Teoc() - ); - - - // - // hookup controller section - // - atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) - u1 ( - .clk(wb_clk_i), - .nReset(arst_signal), - .rst(wb_rst_i), - .irq(irq), - .IDEctrl_rst(IDEctrl_rst), - .IDEctrl_IDEen(IDEctrl_IDEen), - .IDEctrl_FATR0(IDEctrl_FATR0), - .IDEctrl_FATR1(IDEctrl_FATR1), - .cmdport_T1(PIO_cmdport_T1), - .cmdport_T2(PIO_cmdport_T2), - .cmdport_T4(PIO_cmdport_T4), - .cmdport_Teoc(PIO_cmdport_Teoc), - .cmdport_IORDYen(PIO_cmdport_IORDYen), - .dport0_T1(PIO_dport0_T1), - .dport0_T2(PIO_dport0_T2), - .dport0_T4(PIO_dport0_T4), - .dport0_Teoc(PIO_dport0_Teoc), - .dport0_IORDYen(PIO_dport0_IORDYen), - .dport1_T1(PIO_dport1_T1), - .dport1_T2(PIO_dport1_T2), - .dport1_T4(PIO_dport1_T4), - .dport1_Teoc(PIO_dport1_Teoc), - .dport1_IORDYen(PIO_dport1_IORDYen), - .PIOreq(PIOsel), - .PIOack(PIOack), - .PIOa(wb_adr_i[5:2]), - .PIOd(wb_dat_i[15:0]), - .PIOq(PIOq), - .PIOwe(wb_we_i), - .RESETn(resetn_pad_o), - .DDi(dd_pad_i), - .DDo(dd_pad_o), - .DDoe(dd_padoe_o), - .DA(da_pad_o), - .CS0n(cs0n_pad_o), - .CS1n(cs1n_pad_o), - .DIORn(diorn_pad_o), - .DIOWn(diown_pad_o), - .IORDY(iordy_pad_i), - .INTRQ(intrq_pad_i) - ); - -endmodule - Index: trunk/rtl/verilog/ocidec-2/timescale.v =================================================================== --- trunk/rtl/verilog/ocidec-2/timescale.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/timescale.v (nonexistent) @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - Index: trunk/rtl/verilog/ocidec-2/atahost_controller.v =================================================================== --- trunk/rtl/verilog/ocidec-2/atahost_controller.v (revision 32) +++ trunk/rtl/verilog/ocidec-2/atahost_controller.v (nonexistent) @@ -1,275 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores ATA/ATAPI-5 Host Controller //// -//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// -// CVS Log -// -// $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $ -// -// $Date: 2002-05-19 06:05:28 $ -// $Revision: 1.2 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ - -// -// OCIDEC2 supports: -// -Common Compatible timing access to all connected devices -// -Separate timing accesses to data port -// -No DMA support -// - -`include "timescale.v" - -module atahost_controller ( - clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1, - cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen, - dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen, - dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen, - PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe, - RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ - ); - - // - // parameters - // - parameter TWIDTH = 8; - parameter PIO_mode0_T1 = 6; // 70ns - parameter PIO_mode0_T2 = 28; // 290ns - parameter PIO_mode0_T4 = 2; // 30ns - parameter PIO_mode0_Teoc = 23; // 240ns - - // - // inputs & outputs - // - input clk; // master clock - input nReset; // asynchronous active low reset - input rst; // synchronous active high reset - - output irq; // interrupt request signal - reg irq; - - // control / registers - input IDEctrl_rst; - input IDEctrl_IDEen; - input IDEctrl_FATR0; - input IDEctrl_FATR1; - - input [7:0] cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc; - input cmdport_IORDYen; // PIO command port / non-fast timing - - input [7:0] dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc; - input dport0_IORDYen; // PIO mode data-port / fast timing device 0 - - input [7:0] dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc; - input dport1_IORDYen; // PIO mode data-port / fast timing device 1 - - input PIOreq; // PIO transfer request - output PIOack; // PIO transfer ended - input [ 3:0] PIOa; // PIO address - input [15:0] PIOd; // PIO data in - output [15:0] PIOq; // PIO data out - input PIOwe; // PIO direction bit '1'=write, '0'=read - - reg PIOack; - - // ATA signals - output RESETn; - input [15:0] DDi; - output [15:0] DDo; - output DDoe; - output [ 2:0] DA; - output CS0n; - output CS1n; - output DIORn; - output DIOWn; - input IORDY; - input INTRQ; - - reg RESETn; - reg [15:0] DDo; - reg DDoe; - reg [ 2:0] DA; - reg CS0n; - reg CS1n; - reg DIORn; - reg DIOWn; - - - // - // signals & variables - // - wire PIOdone; // PIO timing controller done - - // PIO signals - wire PIOdior, PIOdiow, PIOoe; - - // synchronized ATA inputs - reg sIORDY; - - // - // module body - // - - - // synchronize incoming signals - reg cIORDY; // capture IORDY - reg cINTRQ; // capture INTRQ - - always @(posedge clk) - begin : synch_incoming - - cIORDY <= #1 IORDY; - cINTRQ <= #1 INTRQ; - - sIORDY <= #1 cIORDY; - irq <= #1 cINTRQ; - end - - // generate ATA signals - always @(posedge clk or negedge nReset) - if (~nReset) - begin - RESETn <= #1 1'b0; - DIORn <= #1 1'b1; - DIOWn <= #1 1'b1; - DA <= #1 0; - CS0n <= #1 1'b1; - CS1n <= #1 1'b1; - DDo <= #1 0; - DDoe <= #1 1'b0; - end - else if (rst) - begin - RESETn <= #1 1'b0; - DIORn <= #1 1'b1; - DIOWn <= #1 1'b1; - DA <= #1 0; - CS0n <= #1 1'b1; - CS1n <= #1 1'b1; - DDo <= #1 0; - DDoe <= #1 1'b0; - end - else - begin - RESETn <= #1 !IDEctrl_rst; - DA <= #1 PIOa[2:0]; - CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0' - CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1' - - DDo <= #1 PIOd; - DDoe <= #1 PIOoe; - DIORn <= #1 !PIOdior; - DIOWn <= #1 !PIOdiow; - end - - // generate selected device - reg SelDev; - always @(posedge clk) - if (PIOdone & (PIOa == 4'b0110) & PIOwe) - SelDev <= #1 PIOd[4]; - - // generate PIOgo signal - always @(posedge clk or negedge nReset) - if (~nReset) - begin - dPIOreq <= #1 1'b0; - PIOgo <= #1 1'b0; - end - else if (rst) - begin - dPIOreq <= #1 1'b0; - PIOgo <= #1 1'b0; - end - else - begin - dPIOreq <= #1 PIOreq & !PIOack; - PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen; - end - - // - // Hookup PIO access controller - // - atahost_pio_actrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) - PIO_access_control ( - .clk(clk), - .nReset(nReset), - .rst(rst), - .IDEctrl_FATR0(IDEctrl_FATR0), - .IDEctrl_FATR1(IDEctrl_FATR1), - .cmdport_T1(cmdport_T1), - .cmdport_T2(cmdport_T2), - .cmdport_T4(cmdport_T4), - .cmdport_Teoc(cmdport_Teoc), - .cmdport_IORDYen(cmdport_IORDYen), - .dport0_T1(dport0_T1), - .dport0_T2(dport0_T2), - .dport0_T4(dport0_T4), - .dport0_Teoc(dport0_Teoc), - .dport0_IORDYen(dport0_IORDYen), - .dport1_T1(dport1_T1), - .dport1_T2(dport1_T2), - .dport1_T4(dport1_T4), - .dport1_Teoc(dport1_Teoc), - .dport1_IORDYen(dport1_IORDYen), - .SelDev(SelDev), - .go(PIOgo), - .done(PIOdone), - .dir(PIOwe), - .a(PIOa), - .q(PIOq), - .DDi(DDi), - .oe(PIOoe), - .DIOR(PIOdior), - .DIOW(PIOdiow), - .IORDY(sIORDY) - ); - - always @(posedge clk) - PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) - -endmodule Index: trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd (nonexistent) @@ -1,285 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores ATA/ATAPI-5 Host Controller ---- ----- PIO Timing Controller (common for all OCIDEC cores) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 7th, 2001. Initial release --- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation. --- --- --- CVS Log --- --- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $ --- --- $Date: 2002-02-18 14:29:38 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- --- - --- ---------------------------- --- PIO Timing controller -- ---------------------------- --- - --- --- Timing PIO mode transfers ----------------------------------------------- --- T0: cycle time --- T1: address valid to DIOR-/DIOW- --- T2: DIOR-/DIOW- pulse width --- T2i: DIOR-/DIOW- recovery time --- T3: DIOW- data setup --- T4: DIOW- data hold --- T5: DIOR- data setup --- T6: DIOR- data hold --- T9: address hold from DIOR-/DIOW- negated --- Trd: Read data valid to IORDY asserted --- Ta: IORDY setup time --- Tb: IORDY pulse width --- --- Transfer sequence ----------------------------------- --- 1) set address (DA, CS0-, CS1-) --- 2) wait for T1 --- 3) assert DIOR-/DIOW- --- when write action present Data (timing spec. T3 always honored), enable output enable-signal --- 4) wait for T2 --- 5) check IORDY --- when not IORDY goto 5 --- when IORDY negate DIOW-/DIOR-, latch data (if read action) --- when write, hold data for T4, disable output-enable signal --- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest --- 7) start new cycle - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_pio_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing/control register settings - IORDY_en : in std_logic; -- use IORDY (or not) - T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) - T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) - T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- PIO controller selected (strobe signal) - we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device - - -- return signals - oe : buffer std_logic; -- output enable signal - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe, latch data (during read) - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic; -- IOwrite signal, active high - IORDY : in std_logic -- IORDY signal - ); -end entity atahost_pio_tctrl; - -architecture structural of atahost_pio_tctrl is - component ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); - end component ro_cnt; - - signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic; - signal busy, hold_go, igo, hT2done : std_logic; -begin - -- generate internal go strobe - -- strecht go until ready for new cycle - process(clk, nReset) - begin - if (nReset = '0') then - busy <= '0'; - hold_go <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - busy <= '0'; - hold_go <= '0'; - else - busy <= (igo or busy) and not Teoc_done; - hold_go <= (go or (hold_go and busy)) and not igo; - end if; - end if; - end process; - igo <= (go or hold_go) and not busy; - - -- 1) hookup T1 counter - t1_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T1 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => igo, - D => T1, - done => T1done - ); - - -- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device - T2proc: process(clk, nReset) - begin - if (nReset = '0') then - DIOR <= '0'; - DIOW <= '0'; - oe <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - DIOR <= '0'; - DIOW <= '0'; - oe <= '0'; - else - DIOR <= (not we and T1done) or (DIOR and not IORDY_done); - DIOW <= ( we and T1done) or (DIOW and not IORDY_done); - oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done - end if; - end if; - end process T2proc; - - -- 3) hookup T2 counter - t2_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T2 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => T1done, - D => T2, - done => T2done - ); - - -- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) - -- hold T2done - gen_hT2done: process(clk, nReset) - begin - if (nReset = '0') then - hT2done <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - hT2done <= '0'; - else - hT2done <= (T2done or hT2done) and not IORDY_done; - end if; - end if; - end process gen_hT2done; - IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en); - - -- generate datastrobe, capture data at rising DIOR- edge - gen_dstrb: process(clk) - begin - if (clk'event and clk = '1') then - dstrb <= IORDY_done; - end if; - end process gen_dstrb; - - -- hookup data hold counter - dhold_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T4 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => IORDY_done, - D => T4, - done => T4done - ); - done <= T4done; -- placing done here provides the fastest return possible, - -- while still guaranteeing data and address hold-times - - -- 5) hookup end_of_cycle counter - eoc_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => IORDY_done, - D => Teoc, - done => Teoc_done - ); - -end architecture structural; Index: trunk/rtl/vhdl/ocidec1/ro_cnt.vhd =================================================================== --- trunk/rtl/vhdl/ocidec1/ro_cnt.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec1/ro_cnt.vhd (nonexistent) @@ -1,131 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- Run-Once Counter ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:48:22 rherveille Exp $ --- --- $Date: 2002-03-01 03:48:22 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); -end entity ro_cnt; - -architecture structural of ro_cnt is - component ud_cnt is - generic( - SIZE : natural := 8; - RESD : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - ud : in std_logic := '0'; -- up / not down - nld : in std_logic := '1'; -- synchronous active low load - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0); -- current counter value - - rci : in std_logic := '1'; -- carry input - rco : out std_logic -- carry output - ); - end component ud_cnt; - - signal rci, rco, nld : std_logic; -begin - gen_ctrl: process(clk, nReset) - begin - if (nReset = '0') then - rci <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - rci <= '0'; - else - rci <= go or (rci and not rco); - end if; - end if; - end process; - - nld <= not go; - - -- hookup counter - cnt : ud_cnt - generic map ( - SIZE => SIZE, - RESD => ID - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - cnt_en => cnt_en, - ud => UD, - nld => nld, - D => D, - Q => Q, - rci => rci, - rco => rco - ); - - done <= rco; -end architecture structural; Index: trunk/rtl/vhdl/ocidec1/atahost_top.vhd =================================================================== --- trunk/rtl/vhdl/ocidec1/atahost_top.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec1/atahost_top.vhd (nonexistent) @@ -1,426 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ATA/ATAPI-5 (OCIDEC-1) ---- ----- Top Level ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 22nd, 2001. Initial release --- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools --- rev.: 1.1 june 18th, 2001. Changed wishbone address-input from (A4..A0) to (A6..A2) --- rev.: 1.1a june 19th, 2001. Missed a reference to ADR_I(4). Simplified DAT_O output multiplexor. --- --- --- CVS Log --- --- $Id: atahost_top.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $ --- --- $Date: 2002-02-18 14:29:38 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- --- --- - --- DeviceType: OCIDEC-1: OpenCores IDE Controller type1 --- Features: PIO Compatible Timing --- DeviceID: 0x01 --- RevNo : 0x00 - --- --- Host signals: --- Reset --- DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. --- DIOW- write strobe. The rising edge latches data from DD into the device. --- DA(2:0) 3bit binary coded adress --- CS0- select command block registers --- CS1- select control block registers - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_top is - generic( - ARST_LVL : std_logic := '0'; -- asynchronous reset level - - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - -- WISHBONE SYSCON signals - wb_clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - wb_rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - wb_cyc_i : in std_logic; -- valid bus cycle input - wb_stb_i : in std_logic; -- strobe/core select input - wb_ack_o : out std_logic; -- strobe acknowledge output - wb_err_o : out std_logic; -- error output - wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in - wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out - wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - wb_we_i : in std_logic; -- Write enable input - wb_inta_o : out std_logic; -- interrupt request signal IDE0 - - -- ATA signals - resetn_pad_o : out std_logic; - dd_pad_i : in std_logic_vector(15 downto 0); - dd_pad_o : out std_logic_vector(15 downto 0); - dd_padoe_o : out std_logic; - da_pad_o : out unsigned(2 downto 0); - cs0n_pad_o : out std_logic; - cs1n_pad_o : out std_logic; - - diorn_pad_o : out std_logic; - diown_pad_o : out std_logic; - iordy_pad_i : in std_logic; - intrq_pad_i : in std_logic - ); -end entity atahost_top; - -architecture structural of atahost_top is - -- - -- constants - -- - - -- Device ID - constant DeviceId : unsigned(3 downto 0) := x"1"; - constant RevisionNo : unsigned(3 downto 0) := x"0"; - - -- - -- component declarations - -- - component atahost_wb_slave is - generic( - DeviceID : unsigned(3 downto 0) := x"0"; - RevisionNo : unsigned(3 downto 0) := x"0"; - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - cyc_i : in std_logic; -- valid bus cycle input - stb_i : in std_logic; -- strobe/core select input - ack_o : out std_logic; -- strobe acknowledge output - rty_o : out std_logic; -- retry output - err_o : out std_logic; -- error output - adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - dat_i : in std_logic_vector(31 downto 0); -- Databus in - dat_o : out std_logic_vector(31 downto 0); -- Databus out - sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - we_i : in std_logic; -- Write enable input - inta_o : out std_logic; -- interrupt request signal IDE0 - - -- PIO control input - PIOsel : buffer std_logic; - PIOtip, -- PIO transfer in progress - PIOack : in std_logic; -- PIO acknowledge signal - PIOq : in std_logic_vector(15 downto 0); -- PIO data input - PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full - irq : in std_logic; -- interrupt signal input - - -- DMA control inputs - DMAsel : out std_logic; - DMAtip, -- DMA transfer in progress - DMAack, -- DMA transfer acknowledge - DMARxEmpty, -- DMA receive buffer empty - DMATxFull, -- DMA transmit buffer full - DMA_dmarq : in std_logic; -- wishbone DMA request - DMAq : in std_logic_vector(31 downto 0); - - -- outputs - -- control register outputs - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR1, - IDEctrl_FATR0, - IDEctrl_ppen, - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : out std_logic; - - -- CMD port timing registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : buffer unsigned(7 downto 0); - PIO_cmdport_IORDYen : out std_logic; - - -- data-port0 timing registers - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : buffer unsigned(7 downto 0); - PIO_dport0_IORDYen : out std_logic; - - -- data-port1 timing registers - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : buffer unsigned(7 downto 0); - PIO_dport1_IORDYen : out std_logic; - - -- DMA device0 timing registers - DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc : buffer unsigned(7 downto 0); - - -- DMA device1 timing registers - DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc : buffer unsigned(7 downto 0) - ); - end component atahost_wb_slave; - - - component atahost_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - irq : out std_logic; -- interrupt request signal - - -- control / registers - IDEctrl_rst, - IDEctrl_IDEen : in std_logic; - - -- PIO registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : in unsigned(7 downto 0); -- PIO command timing - PIO_cmdport_IORDYen : in std_logic; - - PIOreq : in std_logic; -- PIO transfer request - PIOack : buffer std_logic; -- PIO transfer ended - PIOa : in unsigned(3 downto 0); -- PIO address - PIOd : in std_logic_vector(15 downto 0); -- PIO data in - PIOq : out std_logic_vector(15 downto 0); -- PIO data out - PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read - - -- ATA signals - RESETn : out std_logic; - DDi : in std_logic_vector(15 downto 0); - DDo : out std_logic_vector(15 downto 0); - DDoe : out std_logic; - DA : out unsigned(2 downto 0); - CS0n : out std_logic; - CS1n : out std_logic; - - DIORn : out std_logic; - DIOWn : out std_logic; - IORDY : in std_logic; - INTRQ : in std_logic - ); - end component atahost_controller; - - -- asynchronous reset signal - signal arst_signal : std_logic; - - -- primary address decoder - signal PIOsel : std_logic; -- controller select, IDE devices select - - -- registers - signal IDEctrl_IDEen, IDEctrl_rst: std_logic; - signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0); - signal PIO_cmdport_IORDYen : std_logic; - signal PIOack : std_logic; - signal PIOq : std_logic_vector(15 downto 0); - - signal irq : std_logic; -- ATA bus IRQ signal - -begin - -- generate asynchronous reset level - arst_signal <= arst_i xor ARST_LVL; - - -- - -- hookup wishbone slave - -- - u0: atahost_wb_slave - generic map( - DeviceID => DeviceID, - RevisionNo => RevisionNo, - - -- PIO mode 0 settings - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc, - - -- Multiword DMA mode 0 settings - -- OCIDEC-1 does not support DMA, set registers to zero - DMA_mode0_Tm => 0, - DMA_mode0_Td => 0, - DMA_mode0_Teoc => 0 - ) - port map( - -- WISHBONE SYSCON signals - clk_i => wb_clk_i, - arst_i => arst_signal, - rst_i => wb_rst_i, - - -- WISHBONE SLAVE signals - cyc_i => wb_cyc_i, - stb_i => wb_stb_i, - ack_o => wb_ack_o, - err_o => wb_err_o, - adr_i => wb_adr_i, - dat_i => wb_dat_i, - dat_o => wb_dat_o, - sel_i => wb_sel_i, - we_i => wb_we_i, - inta_o => wb_inta_o, - - -- PIO control input - -- PIOtip is only asserted during a PIO transfer (No shit! ;) - -- Since it is impossible to read the status register and access the PIO registers at the same time - -- this bit is useless (besides using-up resources) - PIOtip => '0', - PIOack => PIOack, - PIOq => PIOq, - PIOsel => PIOsel, - PIOpp_full => '0', -- OCIDEC-1 does not support PIO-write PingPong, negate signal - irq => irq, - - -- DMA control inputs (negate all of them) - DMAtip => '0', - DMAack => '0', - DMARxEmpty => '0', - DMATxFull => '0', - DMA_dmarq => '0', - DMAq => x"00000000", - - -- outputs - -- control register outputs - IDEctrl_rst => IDEctrl_rst, - IDEctrl_IDEen => IDEctrl_IDEen, - - -- CMD port timing registers - PIO_cmdport_T1 => PIO_cmdport_T1, - PIO_cmdport_T2 => PIO_cmdport_T2, - PIO_cmdport_T4 => PIO_cmdport_T4, - PIO_cmdport_Teoc => PIO_cmdport_Teoc, - PIO_cmdport_IORDYen => PIO_cmdport_IORDYen - ); - - -- - -- hookup controller section - -- - u1: atahost_controller - generic map( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map( - clk => wb_clk_i, - nReset => arst_signal, - rst => wb_rst_i, - irq => irq, - IDEctrl_rst => IDEctrl_rst, - IDEctrl_IDEen => IDEctrl_IDEen, - PIO_cmdport_T1 => PIO_cmdport_T1, - PIO_cmdport_T2 => PIO_cmdport_T2, - PIO_cmdport_T4 => PIO_cmdport_T4, - PIO_cmdport_Teoc => PIO_cmdport_Teoc, - PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, - PIOreq => PIOsel, - PIOack => PIOack, - PIOa => wb_adr_i(5 downto 2), - PIOd => wb_dat_i(15 downto 0), - PIOq => PIOq, - PIOwe => wb_we_i, - RESETn => resetn_pad_o, - DDi => dd_pad_i, - DDo => dd_pad_o, - DDoe => dd_padoe_o, - DA => da_pad_o, - CS0n => cs0n_pad_o, - CS1n => cs1n_pad_o, - DIORn => diorn_pad_o, - DIOWn => diown_pad_o, - IORDY => iordy_pad_i, - INTRQ => intrq_pad_i - ); - -end architecture structural; - - - - - - Index: trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd =================================================================== --- trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd (nonexistent) @@ -1,467 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- Wishbone Slave (common for all OCIDEC cores) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $ --- --- $Date: 2002-02-18 14:29:38 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_wb_slave is - generic( - DeviceID : unsigned(3 downto 0) := x"0"; - RevisionNo : unsigned(3 downto 0) := x"0"; - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - cyc_i : in std_logic; -- valid bus cycle input - stb_i : in std_logic; -- strobe/core select input - ack_o : out std_logic; -- strobe acknowledge output - rty_o : out std_logic; -- retry output - err_o : out std_logic; -- error output - adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - dat_i : in std_logic_vector(31 downto 0); -- Databus in - dat_o : out std_logic_vector(31 downto 0); -- Databus out - sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - we_i : in std_logic; -- Write enable input - inta_o : out std_logic; -- interrupt request signal IDE0 - - -- PIO control input - PIOsel : buffer std_logic; - PIOtip, -- PIO transfer in progress - PIOack : in std_logic; -- PIO acknowledge signal - PIOq : in std_logic_vector(15 downto 0); -- PIO data input - PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full - irq : in std_logic; -- interrupt signal input - - -- DMA control inputs - DMAsel : out std_logic; - DMAtip, -- DMA transfer in progress - DMAack, -- DMA transfer acknowledge - DMARxEmpty, -- DMA receive buffer empty - DMATxFull, -- DMA transmit buffer full - DMA_dmarq : in std_logic; -- wishbone DMA request - DMAq : in std_logic_vector(31 downto 0); - - -- outputs - -- control register outputs - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR1, - IDEctrl_FATR0, - IDEctrl_ppen, - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : out std_logic; - - -- CMD port timing registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : buffer unsigned(7 downto 0); - PIO_cmdport_IORDYen : out std_logic; - - -- data-port0 timing registers - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : buffer unsigned(7 downto 0); - PIO_dport0_IORDYen : out std_logic; - - -- data-port1 timing registers - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : buffer unsigned(7 downto 0); - PIO_dport1_IORDYen : out std_logic; - - -- DMA device0 timing registers - DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc : buffer unsigned(7 downto 0); - - -- DMA device1 timing registers - DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc : buffer unsigned(7 downto 0) - ); -end entity atahost_wb_slave; - -architecture structural of atahost_wb_slave is - -- - -- constants - -- - - -- addresses - alias ATA_DEV_ADR : std_logic is adr_i(6); - alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2); - - constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000"; - constant ATA_STAT_REG : unsigned(3 downto 0) := "0001"; - constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010"; - constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011"; - constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100"; - constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101"; - constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110"; - -- reserved -- - constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111"; - - -- - -- function declarations - -- - -- overload '=' to compare two unsigned numbers - function "=" (a, b : unsigned) return std_logic is - alias la: unsigned(1 to a'length) is a; - alias lb: unsigned(1 to b'length) is b; - variable result : std_logic; - begin - -- check vector length - assert a'length = b'length - report "std_logic_vector comparison: operands of unequal lengths" - severity FAILURE; - - result := '1'; - for n in 1 to a'length loop - result := result and not (la(n) xor lb(n)); - end loop; - - return result; - end; - - -- primary address decoder - signal CONsel : std_logic; -- controller select, IDE devices select - signal berr, brty : std_logic; -- bus error, bus retry - - -- registers - signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers - -begin - -- - -- generate bus cycle / address decoder - -- - gen_bc_dec: block - signal w_acc, dw_acc : std_logic; -- word access, double word access - signal store_pp_full : std_logic; - begin - -- word / double word - w_acc <= sel_i(1) and sel_i(0); - dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0); - - -- bus error - berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc; - - -- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full - PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full); - - -- CON accesses only 32bit wide - CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc; - DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT); - - -- bus retry (OCIDEC-3 and above) - -- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle - process(clk_i) - begin - if (clk_i'event and clk_i = '1') then - if (PIOsel = '0') then - store_pp_full <= PIOpp_full; - end if; - end if; - end process; - brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full); - end block gen_bc_dec; - - -- - -- generate registers - -- - register_block : block - signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers - signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers - signal sel_ctrl, sel_stat : std_logic; -- control / status register - begin - -- generate register select signals - sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG); - sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG); - sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD); - sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0); - sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1); - sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0); - sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1); - -- reserved 0x1C-0x38 -- - -- reserved 0x3C : DMA port -- - - -- generate control register - gen_ctrl_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - CtrlReg(31 downto 1) <= (others => '0'); - CtrlReg(0) <= '1'; -- set reset bit - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - CtrlReg(31 downto 1) <= (others => '0'); - CtrlReg(0) <= '1'; -- set reset bit - elsif (sel_ctrl = '1') then - CtrlReg <= dat_i; - end if; - end if; - end process gen_ctrl_reg; - -- assign bits - DMActrl_DMAen <= CtrlReg(15); - DMActrl_dir <= CtrlReg(13); - DMActrl_BeLeC1 <= CtrlReg(9); - DMActrl_BeLeC0 <= CtrlReg(8); - IDEctrl_IDEen <= CtrlReg(7); - IDEctrl_FATR1 <= CtrlReg(6); - IDEctrl_FATR0 <= CtrlReg(5); - IDEctrl_ppen <= CtrlReg(4); - PIO_dport1_IORDYen <= CtrlReg(3); - PIO_dport0_IORDYen <= CtrlReg(2); - PIO_cmdport_IORDYen <= CtrlReg(1); - IDEctrl_rst <= CtrlReg(0); - - -- generate status register clearable bits - gen_stat_reg: block - signal dirq, int : std_logic; - begin - gen_irq: process(clk_i, arst_i) - begin - if (arst_i = '0') then - int <= '0'; - dirq <= '0'; - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - int <= '0'; - dirq <= '0'; - else - int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0)); - dirq <= irq; - end if; - end if; - end process gen_irq; - - gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full) - begin - StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0') - - StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID - StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number - StatReg(15) <= DMAtip; - StatReg(10) <= DMARxEmpty; - StatReg(9) <= DMATxFull; - StatReg(8) <= DMA_dmarq; - StatReg(7) <= PIOtip; - StatReg(6) <= PIOpp_full; - StatReg(0) <= int; - end process; - end block gen_stat_reg; - - -- generate PIO compatible / command-port timing register - gen_PIO_cmdport_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_cmdport = '1') then - PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8)); - PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16)); - PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_cmdport_reg; - - -- generate PIO device0 timing register - gen_PIO_dport0_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_dport0 = '1') then - PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_dport0_T2 <= unsigned(dat_i(15 downto 8)); - PIO_dport0_T4 <= unsigned(dat_i(23 downto 16)); - PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_dport0_reg; - - -- generate PIO device1 timing register - gen_PIO_dport1_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_dport1 = '1') then - PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_dport1_T2 <= unsigned(dat_i(15 downto 8)); - PIO_dport1_T4 <= unsigned(dat_i(23 downto 16)); - PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_dport1_reg; - - -- generate DMA device0 timing register - gen_DMA_dev0_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (sel_DMA_dev0 = '1') then - DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0)); - DMA_dev0_Td <= unsigned(dat_i(15 downto 8)); - DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_DMA_dev0_reg; - - -- generate DMA device1 timing register - gen_DMA_dev1_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (sel_DMA_dev1 = '1') then - DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0)); - DMA_dev1_Td <= unsigned(dat_i(15 downto 8)); - DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_DMA_dev1_reg; - - end block register_block; - - -- - -- generate WISHBONE interconnect signals - -- - gen_WB_sigs: block - signal Q : std_logic_vector(31 downto 0); - begin - -- generate acknowledge signal - ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK - - -- generate error signal - err_o <= cyc_i and stb_i and berr; - - -- generate retry signal - rty_o <= cyc_i and stb_i and brty; - - -- assign interrupt signal - inta_o <= StatReg(0); - - -- generate output multiplexor - with ATA_ADR select - Q <= CtrlReg when ATA_CTRL_REG, -- control register - StatReg when ATA_STAT_REG, -- status register - std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register - std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0 - std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1 - std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0 - std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1 - DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register - (others => '0') when others; - - dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q; - end block gen_WB_sigs; - -end architecture structural; \ No newline at end of file Index: trunk/rtl/vhdl/ocidec1/atahost_controller.vhd =================================================================== --- trunk/rtl/vhdl/ocidec1/atahost_controller.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec1/atahost_controller.vhd (nonexistent) @@ -1,318 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller (OCIDEC-1) ---- ----- PIO Contoller ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 18th, 2001 --- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools --- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0' --- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device. --- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). --- --- --- CVS Log --- --- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:06:48 rherveille Exp $ --- --- $Date: 2002-05-19 06:06:48 $ --- $Revision: 1.2 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - - --- OCIDEC1 supports: --- -Common Compatible timing access to all connected devices --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - irq : out std_logic; -- interrupt request signal - - -- control / registers - IDEctrl_rst, - IDEctrl_IDEen : in std_logic; - - -- PIO registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : in unsigned(7 downto 0); -- PIO command timing - PIO_cmdport_IORDYen : in std_logic; - - PIOreq : in std_logic; -- PIO transfer request - PIOack : buffer std_logic; -- PIO transfer ended - PIOa : in unsigned(3 downto 0); -- PIO address - PIOd : in std_logic_vector(15 downto 0); -- PIO data in - PIOq : out std_logic_vector(15 downto 0); -- PIO data out - PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read - - -- ATA signals - RESETn : out std_logic; - DDi : in std_logic_vector(15 downto 0); - DDo : out std_logic_vector(15 downto 0); - DDoe : out std_logic; - DA : out unsigned(2 downto 0); - CS0n : out std_logic; - CS1n : out std_logic; - - DIORn : out std_logic; - DIOWn : out std_logic; - IORDY : in std_logic; - INTRQ : in std_logic - ); -end entity atahost_controller; - -architecture structural of atahost_controller is - -- - -- Component declarations - -- - component atahost_pio_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing/control register settings - IORDY_en : in std_logic; -- use IORDY (or not) - T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) - T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) - T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- PIO controller selected (strobe signal) - we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device - - -- return signals - oe : buffer std_logic; -- output enable signal - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe, latch data (during read) - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic; -- IOwrite signal, active high - IORDY : in std_logic -- IORDY signal - ); - end component atahost_pio_tctrl; - - -- - -- signals - -- - signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller - signal PIOdone : std_logic; -- PIO timing controller done - - -- PIO signals - signal PIOdior, PIOdiow : std_logic; - signal PIOoe : std_logic; - - -- Timing settings - signal dstrb : std_logic; - signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0); - signal IORDYen : std_logic; - - -- synchronized ATA inputs - signal sIORDY : std_logic; - -begin - - -- - -- synchronize incoming signals - -- - synch_incoming: block - signal cIORDY : std_logic; -- capture IORDY - signal cINTRQ : std_logic; -- capture INTRQ - begin - process(clk) - begin - if (clk'event and clk = '1') then - cIORDY <= IORDY; - cINTRQ <= INTRQ; - - sIORDY <= cIORDY; - irq <= cINTRQ; - end if; - end process; - end block synch_incoming; - - -- - -- generate ATA signals - -- - gen_ata_sigs: block - begin - -- generate registers for ATA signals - gen_regs: process(clk, nReset) - begin - if (nReset = '0') then - RESETn <= '0'; - DIORn <= '1'; - DIOWn <= '1'; - DA <= (others => '0'); - CS0n <= '1'; - CS1n <= '1'; - DDo <= (others => '0'); - DDoe <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - RESETn <= '0'; - DIORn <= '1'; - DIOWn <= '1'; - DA <= (others => '0'); - CS0n <= '1'; - CS1n <= '1'; - DDo <= (others => '0'); - DDoe <= '0'; - else - RESETn <= not IDEctrl_rst; - DA <= PIOa(2 downto 0); - CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0' - CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1' - - DDo <= PIOd; - DDoe <= PIOoe; - DIORn <= not PIOdior; - DIOWn <= not PIOdiow; - end if; - end if; - end process gen_regs; - end block gen_ata_sigs; - - - -- - -------------------------- - -- PIO transfer control -- - -------------------------- - -- - -- capture ATA data for PIO access - gen_PIOq: process(clk) - begin - if (clk'event and clk = '1') then - if (dstrb = '1') then - PIOq <= DDi; - end if; - end if; - end process gen_PIOq; - - -- generate PIOgo signal - gen_PIOgo: process(clk, nReset) - begin - if (nReset = '0') then - dPIOreq <= '0'; - PIOgo <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - dPIOreq <= '0'; - PIOgo <= '0'; - else - dPIOreq <= PIOreq and not PIOack; - PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen; - end if; - end - end process gen_PIOgo; - - -- set Timing signals - T1 <= PIO_cmdport_T1; - T2 <= PIO_cmdport_T2; - T4 <= PIO_cmdport_T4; - Teoc <= PIO_cmdport_Teoc; - IORDYen <= PIO_cmdport_IORDYen; - - -- - -- hookup timing controller - -- - PIO_timing_controller: atahost_pio_tctrl - generic map ( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - IORDY_en => IORDYen, - T1 => T1, - T2 => T2, - T4 => T4, - Teoc => Teoc, - go => PIOgo, - we => PIOwe, - oe => PIOoe, - done => PIOdone, - dstrb => dstrb, - DIOR => PIOdior, - DIOW => PIOdiow, - IORDY => sIORDY - ); - - -- generate acknowledge - gen_ack: process(clk) - begin - if (clk'event and clk = '1') then - PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request) - end if; - end process gen_ack; -end architecture structural; - Index: trunk/rtl/vhdl/ocidec1/ud_cnt.vhd =================================================================== --- trunk/rtl/vhdl/ocidec1/ud_cnt.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec1/ud_cnt.vhd (nonexistent) @@ -1,102 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- Generic Up/Down counter (ripple carry architecture) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: ud_cnt.vhd,v 1.1 2002-03-01 03:48:22 rherveille Exp $ --- --- $Date: 2002-03-01 03:48:22 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity ud_cnt is - generic( - SIZE : natural := 8; - RESD : natural := 0 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - ud : in std_logic := '0'; -- up / not down - nld : in std_logic := '1'; -- synchronous active low load - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0); -- current counter value - - rci : in std_logic := '1'; -- carry input - rco : out std_logic -- carry output - ); -end entity ud_cnt; - -architecture structural of ud_cnt is - signal Qi : unsigned(SIZE -1 downto 0); - signal val : unsigned(SIZE downto 0); -begin - val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); - - regs: process(clk, nReset) - begin - if (nReset = '0') then - Qi <= conv_unsigned(RESD, SIZE); - elsif (clk'event and clk = '1') then - if (rst = '1') then - Qi <= conv_unsigned(RESD, SIZE); - else - if (nld = '0') then - Qi <= D; - elsif (cnt_en = '1') then - Qi <= val(SIZE -1 downto 0); - end if; - end if; - end if; - end process regs; - - -- assign outputs - Q <= Qi; - rco <= val(SIZE); -end architecture structural; - Index: trunk/rtl/vhdl/ocidec1/revision_history.txt =================================================================== --- trunk/rtl/vhdl/ocidec1/revision_history.txt (revision 32) +++ trunk/rtl/vhdl/ocidec1/revision_history.txt (nonexistent) @@ -1,77 +0,0 @@ ------------------------------ -Revision: 1.0 -Date: march 22nd, 2001 -Author: Richard Herveille -- initial release ------------------------------ - ------------------------------ -Revision: 1.0a -Date: april 12th, 2001 -Author: Richard Herveille -- removed records.vhd -- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools -- fixed a minor bug where core didn't respond to IDEen bit. ------------------------------ - ------------------------------ -Revision: 1.1 -Date: June 18th, 2001 -Author: Richard Herveille -- Changed PIOack generation. Avoid asserting PIOack continuosly when IDEen = '0' -- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) ------------------------------ - - ------------------------------ -Revision: 1.1a -Date: June 19th, 2001 -Author: Richard Herveille -- Missed a reference to ADR_I(4). Simplified DAT_O output multiplexor. ------------------------------ - ------------------------------ -Revision: 1.2 -Date: June 26th, 2001 -Author: Richard Herveille -- Changed dPIOreq generation (controller.vhd). Wishbone burst accesses to ata device were not handled correctly -- Change PIOack from "out" to "buffer" (controller.vhd + ata.vhd) ------------------------------ - ------------------------------ -Revision: 1.3 -Date: July 11th, 2001 -Author: Richard Herveille -- renamed 'ata.vhd' to 'atahost.vhd' -- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous -- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). ------------------------------ - ------------------------------ -Revision: 1.4 -Date: Februar 17th, 2002 -Author: Richard Herveille -- renamed 'atahost.vhd' to 'atahost_top.vhd' -- renamed 'controller.vhd' to 'atahost_controller.vhd' -- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' -- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' -- changed resD input to generic RESD in ud_cnt.vhd -- changed ID input to generic ID in ro_cnt.vhd -- changed core to reflect changes in ro_cnt.vhd -- removed references to 'count' library -- changed IO names -- added disclaimer -- added CVS log -- moved registers and wishbone signals into 'atahost_wb_slave.vhd' -- core is now equivalent to verilog version ------------------------------ - - ------------------------------ -Revision: 1.5 -Date: May 19th, 2002. -Author: Richard Herveille -- Fixed a potential bug that forced the core into an unknown state - when an asynchronous reset was given without a running clock ------------------------------ - Index: trunk/rtl/vhdl/ocidec2/ud_cnt.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/ud_cnt.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/ud_cnt.vhd (nonexistent) @@ -1,102 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- Generic Up/Down counter (ripple carry architecture) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: ud_cnt.vhd,v 1.1 2002-03-01 03:49:03 rherveille Exp $ --- --- $Date: 2002-03-01 03:49:03 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity ud_cnt is - generic( - SIZE : natural := 8; - RESD : natural := 0 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - ud : in std_logic := '0'; -- up / not down - nld : in std_logic := '1'; -- synchronous active low load - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0); -- current counter value - - rci : in std_logic := '1'; -- carry input - rco : out std_logic -- carry output - ); -end entity ud_cnt; - -architecture structural of ud_cnt is - signal Qi : unsigned(SIZE -1 downto 0); - signal val : unsigned(SIZE downto 0); -begin - val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); - - regs: process(clk, nReset) - begin - if (nReset = '0') then - Qi <= conv_unsigned(RESD, SIZE); - elsif (clk'event and clk = '1') then - if (rst = '1') then - Qi <= conv_unsigned(RESD, SIZE); - else - if (nld = '0') then - Qi <= D; - elsif (cnt_en = '1') then - Qi <= val(SIZE -1 downto 0); - end if; - end if; - end if; - end process regs; - - -- assign outputs - Q <= Qi; - rco <= val(SIZE); -end architecture structural; - Index: trunk/rtl/vhdl/ocidec2/revision_history.txt =================================================================== --- trunk/rtl/vhdl/ocidec2/revision_history.txt (revision 32) +++ trunk/rtl/vhdl/ocidec2/revision_history.txt (nonexistent) @@ -1,74 +0,0 @@ ------------------------------ -Revision: 1.0 -Date: march 22nd, 2001 -Author: Richard Herveille -- initial release ------------------------------ - ------------------------------ -Revision: 1.0a -Date: april 12th, 2001 -Author: Richard Herveille -- removed records.vhd -- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools -- fixed a minor bug where core didn't respond to IDEen bit. ------------------------------ - ------------------------------ -Revision: 1.1 -Date: June 18th, 2001 -Author: Richard Herveille -- Changed PIOack generation. Avoid asserting PIOack continuosly when IDEen = '0' -- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) ------------------------------ - ------------------------------ -Revision: 1.1a -Date: June 19th, 2001 -Author: Richard Herveille -- Simplified DAT_O output multiplexor ------------------------------ - ------------------------------ -Revision: 1.2 -Date: June 26th, 2001 -Author: Richard Herveille -- Changed dPIOreq generation (controller.vhd). Wishbone burst accesses to ata device were not handled correctly -- Change PIOack from "out" to "buffer" (controller.vhd + ata.vhd) ------------------------------ - ------------------------------ -Revision: 1.3 -Date: July 11th, 2001 -Author: Richard Herveille -- renamed 'ata.vhd' to 'atahost.vhd' -- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous -- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). ------------------------------ - ------------------------------ -Revision: 1.4 -Date: Februar 17th, 2002 -Author: Richard Herveille -- renamed 'atahost.vhd' to 'atahost_top.vhd' -- renamed 'controller.vhd' to 'atahost_controller.vhd' -- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' -- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' -- changed resD input to generic RESD in ud_cnt.vhd -- changed ID input to generic ID in ro_cnt.vhd -- changed core to reflect changes in ro_cnt.vhd -- removed references to 'count' library -- changed IO names -- added disclaimer -- added CVS log -- moved registers and wishbone signals into 'atahost_wb_slave.vhd' ------------------------------ - ------------------------------ -Revision: 1.5 -Date: May 19th, 2002. -Author: Richard Herveille -- Fixed a potential bug that forced the core into an unknown state - when an asynchronous reset was given without a running clock ------------------------------ - Index: trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd (nonexistent) @@ -1,252 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- PIO Access Controller (common for OCIDEC 2 and above) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws --- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 9th, 2001 --- rev.: 1.0a april 12th, 2001 Removed references to records.vhd --- --- --- CVS Log --- --- $Id: atahost_pio_actrl.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $ --- --- $Date: 2002-05-19 06:07:09 $ --- $Revision: 1.2 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - --- ---------------------------- --- PIO Access controller -- ---------------------------- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_pio_actrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - SelDev : in std_logic; -- Selected device - - go : in std_logic; -- Start transfer sequence - done : out std_logic; -- Transfer sequence done - dir : in std_logic; -- Transfer direction '1'=write, '0'=read - a : in unsigned(3 downto 0); -- PIO transfer address - q : out std_logic_vector(15 downto 0); -- Data read from ATA devices - - DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus - oe : buffer std_logic; -- DDbus output-enable signal - - DIOR, - DIOW : buffer std_logic; - IORDY : in std_logic - ); -end entity atahost_pio_actrl; - -architecture structural of atahost_pio_actrl is - -- - -- Component declarations - -- - component atahost_pio_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing/control register settings - IORDY_en : in std_logic; -- use IORDY (or not) - T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) - T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) - T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- PIO controller selected (strobe signal) - we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device - - -- return signals - oe : buffer std_logic; -- output enable signal - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe, latch data (during read) - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic; -- IOwrite signal, active high - IORDY : in std_logic -- IORDY signal - ); - end component atahost_pio_tctrl; - - signal dstrb : std_logic; - signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0); - signal IORDYen : std_logic; - -begin - -- - -------------------------- - -- PIO transfer control -- - -------------------------- - -- - -- capture ATA data for PIO access - gen_PIOq: process(clk) - begin - if (clk'event and clk = '1') then - if (dstrb = '1') then - q <= DDi; - end if; - end if; - end process gen_PIOq; - - -- - -- PIO timing controllers - -- - - -- select timing settings for the addressed port - sel_port_t: process(clk) - variable Asel : std_logic; -- address selected - variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0); - variable iIORDYen : std_logic; - begin - -- initially set timing registers to compatible timing - iT1 := cmdport_T1; - iT2 := cmdport_T2; - iT4 := cmdport_T4; - iTeoc := cmdport_Teoc; - iIORDYen := cmdport_IORDYen; - - -- detect data-port access - Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port - if (Asel = '1') then -- data port selected, 16bit transfers - if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ? - iT1 := dport1_T1; - iT2 := dport1_T2; - iT4 := dport1_T4; - iTeoc := dport1_Teoc; - iIORDYen := dport1_IORDYen; - elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ? - iT1 := dport0_T1; - iT2 := dport0_T2; - iT4 := dport0_T4; - iTeoc := dport0_Teoc; - iIORDYen := dport0_IORDYen; - end if; - end if; - - if (clk'event and clk = '1') then - T1 <= iT1; - T2 <= iT2; - T4 <= iT4; - Teoc <= iTeoc; - IORDYen <= iIORDYen; - end if; - end process sel_port_t; - - -- - -- hookup timing controller - -- - PIO_timing_controller: atahost_pio_tctrl - generic map ( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - IORDY_en => IORDYen, - T1 => T1, - T2 => T2, - T4 => T4, - Teoc => Teoc, - go => go, - we => dir, - oe => oe, - done => done, - dstrb => dstrb, - DIOR => dior, - DIOW => diow, - IORDY => IORDY - ); -end architecture structural; - Index: trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd (nonexistent) @@ -1,285 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores ATA/ATAPI-5 Host Controller ---- ----- PIO Timing Controller (common for all OCIDEC cores) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 7th, 2001. Initial release --- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation. --- --- --- CVS Log --- --- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:30:48 rherveille Exp $ --- --- $Date: 2002-02-18 14:30:48 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- --- - --- ---------------------------- --- PIO Timing controller -- ---------------------------- --- - --- --- Timing PIO mode transfers ----------------------------------------------- --- T0: cycle time --- T1: address valid to DIOR-/DIOW- --- T2: DIOR-/DIOW- pulse width --- T2i: DIOR-/DIOW- recovery time --- T3: DIOW- data setup --- T4: DIOW- data hold --- T5: DIOR- data setup --- T6: DIOR- data hold --- T9: address hold from DIOR-/DIOW- negated --- Trd: Read data valid to IORDY asserted --- Ta: IORDY setup time --- Tb: IORDY pulse width --- --- Transfer sequence ----------------------------------- --- 1) set address (DA, CS0-, CS1-) --- 2) wait for T1 --- 3) assert DIOR-/DIOW- --- when write action present Data (timing spec. T3 always honored), enable output enable-signal --- 4) wait for T2 --- 5) check IORDY --- when not IORDY goto 5 --- when IORDY negate DIOW-/DIOR-, latch data (if read action) --- when write, hold data for T4, disable output-enable signal --- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest --- 7) start new cycle - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_pio_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing/control register settings - IORDY_en : in std_logic; -- use IORDY (or not) - T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) - T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) - T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- PIO controller selected (strobe signal) - we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device - - -- return signals - oe : buffer std_logic; -- output enable signal - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe, latch data (during read) - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic; -- IOwrite signal, active high - IORDY : in std_logic -- IORDY signal - ); -end entity atahost_pio_tctrl; - -architecture structural of atahost_pio_tctrl is - component ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); - end component ro_cnt; - - signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic; - signal busy, hold_go, igo, hT2done : std_logic; -begin - -- generate internal go strobe - -- strecht go until ready for new cycle - process(clk, nReset) - begin - if (nReset = '0') then - busy <= '0'; - hold_go <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - busy <= '0'; - hold_go <= '0'; - else - busy <= (igo or busy) and not Teoc_done; - hold_go <= (go or (hold_go and busy)) and not igo; - end if; - end if; - end process; - igo <= (go or hold_go) and not busy; - - -- 1) hookup T1 counter - t1_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T1 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => igo, - D => T1, - done => T1done - ); - - -- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device - T2proc: process(clk, nReset) - begin - if (nReset = '0') then - DIOR <= '0'; - DIOW <= '0'; - oe <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - DIOR <= '0'; - DIOW <= '0'; - oe <= '0'; - else - DIOR <= (not we and T1done) or (DIOR and not IORDY_done); - DIOW <= ( we and T1done) or (DIOW and not IORDY_done); - oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done - end if; - end if; - end process T2proc; - - -- 3) hookup T2 counter - t2_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T2 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => T1done, - D => T2, - done => T2done - ); - - -- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) - -- hold T2done - gen_hT2done: process(clk, nReset) - begin - if (nReset = '0') then - hT2done <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - hT2done <= '0'; - else - hT2done <= (T2done or hT2done) and not IORDY_done; - end if; - end if; - end process gen_hT2done; - IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en); - - -- generate datastrobe, capture data at rising DIOR- edge - gen_dstrb: process(clk) - begin - if (clk'event and clk = '1') then - dstrb <= IORDY_done; - end if; - end process gen_dstrb; - - -- hookup data hold counter - dhold_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T4 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => IORDY_done, - D => T4, - done => T4done - ); - done <= T4done; -- placing done here provides the fastest return possible, - -- while still guaranteeing data and address hold-times - - -- 5) hookup end_of_cycle counter - eoc_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => IORDY_done, - D => Teoc, - done => Teoc_done - ); - -end architecture structural; Index: trunk/rtl/vhdl/ocidec2/ro_cnt.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/ro_cnt.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/ro_cnt.vhd (nonexistent) @@ -1,131 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- Run-Once Counter ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:49:03 rherveille Exp $ --- --- $Date: 2002-03-01 03:49:03 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); -end entity ro_cnt; - -architecture structural of ro_cnt is - component ud_cnt is - generic( - SIZE : natural := 8; - RESD : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - ud : in std_logic := '0'; -- up / not down - nld : in std_logic := '1'; -- synchronous active low load - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0); -- current counter value - - rci : in std_logic := '1'; -- carry input - rco : out std_logic -- carry output - ); - end component ud_cnt; - - signal rci, rco, nld : std_logic; -begin - gen_ctrl: process(clk, nReset) - begin - if (nReset = '0') then - rci <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - rci <= '0'; - else - rci <= go or (rci and not rco); - end if; - end if; - end process; - - nld <= not go; - - -- hookup counter - cnt : ud_cnt - generic map ( - SIZE => SIZE, - RESD => ID - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - cnt_en => cnt_en, - ud => UD, - nld => nld, - D => D, - Q => Q, - rci => rci, - rco => rco - ); - - done <= rco; -end architecture structural; Index: trunk/rtl/vhdl/ocidec2/atahost_top.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/atahost_top.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/atahost_top.vhd (nonexistent) @@ -1,469 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- ATA/ATAPI-5 Controller (OCIDEC-2) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0a Removed references to records.vhd, make core compatible with VHDL to Verilog translator tools --- rev.: 1.1 june 18th, 2001. Changed wishbone address input from ADR_I(4 downto 0) to ADR_I(6 downto 2) --- rev.: 1.1a june 19th, 2001. Simplified DAT_O output multiplexor. --- --- CVS Log --- --- $Id: atahost_top.vhd,v 1.1 2002-02-18 14:30:48 rherveille Exp $ --- --- $Date: 2002-02-18 14:30:48 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - - --- --- DeviceType: OCIDEC-2: OpenCores IDE Controller type2 --- Features: PIO Compatible Timing, PIO Fast Timing 0/1 --- DeviceID: 0x02 --- RevNo : 0x00 - --- --- Host signals: --- Reset --- DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. --- DIOW- write strobe. The rising edge latches data from DD into the device. --- DA(2:0) 3bit binary coded adress --- CS0- select command block registers --- CS1- select control block registers - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_top is - generic( - ARST_LVL : std_logic := '0'; -- asynchronous reset level - - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - -- WISHBONE SYSCON signals - wb_clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - wb_rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - wb_cyc_i : in std_logic; -- valid bus cycle input - wb_stb_i : in std_logic; -- strobe/core select input - wb_ack_o : out std_logic; -- strobe acknowledge output - wb_err_o : out std_logic; -- error output - wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in - wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out - wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - wb_we_i : in std_logic; -- Write enable input - wb_inta_o : out std_logic; -- interrupt request signal IDE0 - - -- ATA signals - resetn_pad_o : out std_logic; - dd_pad_i : in std_logic_vector(15 downto 0); - dd_pad_o : out std_logic_vector(15 downto 0); - dd_padoe_o : out std_logic; - da_pad_o : out unsigned(2 downto 0); - cs0n_pad_o : out std_logic; - cs1n_pad_o : out std_logic; - - diorn_pad_o : out std_logic; - diown_pad_o : out std_logic; - iordy_pad_i : in std_logic; - intrq_pad_i : in std_logic - ); -end entity atahost_top; - -architecture structural of atahost_top is - -- - -- constants - -- - - -- Device ID - constant DeviceId : unsigned(3 downto 0) := x"2"; - constant RevisionNo : unsigned(3 downto 0) := x"0"; - - -- - -- component declarations - -- - component atahost_wb_slave is - generic( - DeviceID : unsigned(3 downto 0) := x"0"; - RevisionNo : unsigned(3 downto 0) := x"0"; - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - cyc_i : in std_logic; -- valid bus cycle input - stb_i : in std_logic; -- strobe/core select input - ack_o : out std_logic; -- strobe acknowledge output - rty_o : out std_logic; -- retry output - err_o : out std_logic; -- error output - adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - dat_i : in std_logic_vector(31 downto 0); -- Databus in - dat_o : out std_logic_vector(31 downto 0); -- Databus out - sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - we_i : in std_logic; -- Write enable input - inta_o : out std_logic; -- interrupt request signal IDE0 - - -- PIO control input - PIOsel : buffer std_logic; - PIOtip, -- PIO transfer in progress - PIOack : in std_logic; -- PIO acknowledge signal - PIOq : in std_logic_vector(15 downto 0); -- PIO data input - PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full - irq : in std_logic; -- interrupt signal input - - -- DMA control inputs - DMAsel : out std_logic; - DMAtip, -- DMA transfer in progress - DMAack, -- DMA transfer acknowledge - DMARxEmpty, -- DMA receive buffer empty - DMATxFull, -- DMA transmit buffer full - DMA_dmarq : in std_logic; -- wishbone DMA request - DMAq : in std_logic_vector(31 downto 0); - - -- outputs - -- control register outputs - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR1, - IDEctrl_FATR0, - IDEctrl_ppen, - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : out std_logic; - - -- CMD port timing registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : buffer unsigned(7 downto 0); - PIO_cmdport_IORDYen : out std_logic; - - -- data-port0 timing registers - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : buffer unsigned(7 downto 0); - PIO_dport0_IORDYen : out std_logic; - - -- data-port1 timing registers - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : buffer unsigned(7 downto 0); - PIO_dport1_IORDYen : out std_logic; - - -- DMA device0 timing registers - DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc : buffer unsigned(7 downto 0); - - -- DMA device1 timing registers - DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc : buffer unsigned(7 downto 0) - ); - end component atahost_wb_slave; - - - component atahost_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - irq : out std_logic; -- interrupt request signal - - -- control / registers - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - -- PIO registers - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - PIOreq : in std_logic; -- PIO transfer request - PIOack : buffer std_logic; -- PIO transfer ended - PIOa : in unsigned(3 downto 0); -- PIO address - PIOd : in std_logic_vector(15 downto 0); -- PIO data in - PIOq : out std_logic_vector(15 downto 0); -- PIO data out - PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read - - -- ATA signals - RESETn : out std_logic; - DDi : in std_logic_vector(15 downto 0); - DDo : out std_logic_vector(15 downto 0); - DDoe : out std_logic; - DA : out unsigned(2 downto 0); - CS0n : out std_logic; - CS1n : out std_logic; - - DIORn : out std_logic; - DIOWn : out std_logic; - IORDY : in std_logic; - INTRQ : in std_logic - ); - end component atahost_controller; - - -- asynchronous reset signal - signal arst_signal : std_logic; - - -- primary address decoder - signal PIOsel : std_logic; -- controller select, IDE devices select - - -- registers - -- control register - signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic; - -- compatible mode timing register - signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0); - signal PIO_cmdport_IORDYen : std_logic; - -- data port0 timing register - signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : unsigned(7 downto 0); - signal PIO_dport0_IORDYen : std_logic; - -- data port1 timing register - signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : unsigned(7 downto 0); - signal PIO_dport1_IORDYen : std_logic; - - signal PIOack : std_logic; - signal PIOq : std_logic_vector(15 downto 0); - - signal irq : std_logic; -- ATA bus IRQ signal - -begin - -- generate asynchronous reset level - arst_signal <= arst_i xor ARST_LVL; - - -- - -- hookup wishbone slave - -- - u0: atahost_wb_slave - generic map( - DeviceID => DeviceID, - RevisionNo => RevisionNo, - - -- PIO mode 0 settings - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc, - - -- Multiword DMA mode 0 settings - -- OCIDEC-1 does not support DMA, set registers to zero - DMA_mode0_Tm => 0, - DMA_mode0_Td => 0, - DMA_mode0_Teoc => 0 - ) - port map( - -- WISHBONE SYSCON signals - clk_i => wb_clk_i, - arst_i => arst_signal, - rst_i => wb_rst_i, - - -- WISHBONE SLAVE signals - cyc_i => wb_cyc_i, - stb_i => wb_stb_i, - ack_o => wb_ack_o, - err_o => wb_err_o, - adr_i => wb_adr_i, - dat_i => wb_dat_i, - dat_o => wb_dat_o, - sel_i => wb_sel_i, - we_i => wb_we_i, - inta_o => wb_inta_o, - - -- PIO control input - -- PIOtip is only asserted during a PIO transfer (No shit! ;) - -- Since it is impossible to read the status register and access the PIO registers at the same time - -- this bit is useless (besides using-up resources) - PIOtip => '0', - PIOack => PIOack, - PIOq => PIOq, - PIOsel => PIOsel, - PIOpp_full => '0', -- OCIDEC-1 does not support PIO-write PingPong, negate signal - irq => irq, - - -- DMA control inputs (negate all of them) - DMAtip => '0', - DMAack => '0', - DMARxEmpty => '0', - DMATxFull => '0', - DMA_dmarq => '0', - DMAq => x"00000000", - - -- outputs - -- control register outputs - IDEctrl_rst => IDEctrl_rst, - IDEctrl_IDEen => IDEctrl_IDEen, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - - -- CMD port timing registers - PIO_cmdport_T1 => PIO_cmdport_T1, - PIO_cmdport_T2 => PIO_cmdport_T2, - PIO_cmdport_T4 => PIO_cmdport_T4, - PIO_cmdport_Teoc => PIO_cmdport_Teoc, - PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, - - -- data-port0 timing registers - PIO_dport0_T1 => PIO_dport0_T1, - PIO_dport0_T2 => PIO_dport0_T2, - PIO_dport0_T4 => PIO_dport0_T4, - PIO_dport0_Teoc => PIO_dport0_Teoc, - PIO_dport0_IORDYen => PIO_dport0_IORDYen, - - -- data-port1 timing registers - PIO_dport1_T1 => PIO_dport1_T1, - PIO_dport1_T2 => PIO_dport1_T2, - PIO_dport1_T4 => PIO_dport1_T4, - PIO_dport1_Teoc => PIO_dport1_Teoc, - PIO_dport1_IORDYen => PIO_dport1_IORDYen - ); - - -- - -- hookup controller section - -- - u1: atahost_controller - generic map( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map( - clk => wb_clk_i, - nReset => arst_signal, - rst => wb_rst_i, - irq => irq, - IDEctrl_rst => IDEctrl_rst, - IDEctrl_IDEen => IDEctrl_IDEen, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - cmdport_T1 => PIO_cmdport_T1, - cmdport_T2 => PIO_cmdport_T2, - cmdport_T4 => PIO_cmdport_T4, - cmdport_Teoc => PIO_cmdport_Teoc, - cmdport_IORDYen => PIO_cmdport_IORDYen, - dport0_T1 => PIO_dport0_T1, - dport0_T2 => PIO_dport0_T2, - dport0_T4 => PIO_dport0_T4, - dport0_Teoc => PIO_dport0_Teoc, - dport0_IORDYen => PIO_dport0_IORDYen, - dport1_T1 => PIO_dport1_T1, - dport1_T2 => PIO_dport1_T2, - dport1_T4 => PIO_dport1_T4, - dport1_Teoc => PIO_dport1_Teoc, - dport1_IORDYen => PIO_dport1_IORDYen, - PIOreq => PIOsel, - PIOack => PIOack, - PIOa => wb_adr_i(5 downto 2), - PIOd => wb_dat_i(15 downto 0), - PIOq => PIOq, - PIOwe => wb_we_i, - RESETn => resetn_pad_o, - DDi => dd_pad_i, - DDo => dd_pad_o, - DDoe => dd_padoe_o, - DA => da_pad_o, - CS0n => cs0n_pad_o, - CS1n => cs1n_pad_o, - DIORn => diorn_pad_o, - DIOWn => diown_pad_o, - IORDY => iordy_pad_i, - INTRQ => intrq_pad_i - ); -end architecture structural; - Index: trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd (nonexistent) @@ -1,467 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- Wishbone Slave (common for all OCIDEC cores) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:30:48 rherveille Exp $ --- --- $Date: 2002-02-18 14:30:48 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_wb_slave is - generic( - DeviceID : unsigned(3 downto 0) := x"0"; - RevisionNo : unsigned(3 downto 0) := x"0"; - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - cyc_i : in std_logic; -- valid bus cycle input - stb_i : in std_logic; -- strobe/core select input - ack_o : out std_logic; -- strobe acknowledge output - rty_o : out std_logic; -- retry output - err_o : out std_logic; -- error output - adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - dat_i : in std_logic_vector(31 downto 0); -- Databus in - dat_o : out std_logic_vector(31 downto 0); -- Databus out - sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - we_i : in std_logic; -- Write enable input - inta_o : out std_logic; -- interrupt request signal IDE0 - - -- PIO control input - PIOsel : buffer std_logic; - PIOtip, -- PIO transfer in progress - PIOack : in std_logic; -- PIO acknowledge signal - PIOq : in std_logic_vector(15 downto 0); -- PIO data input - PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full - irq : in std_logic; -- interrupt signal input - - -- DMA control inputs - DMAsel : out std_logic; - DMAtip, -- DMA transfer in progress - DMAack, -- DMA transfer acknowledge - DMARxEmpty, -- DMA receive buffer empty - DMATxFull, -- DMA transmit buffer full - DMA_dmarq : in std_logic; -- wishbone DMA request - DMAq : in std_logic_vector(31 downto 0); - - -- outputs - -- control register outputs - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR1, - IDEctrl_FATR0, - IDEctrl_ppen, - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : out std_logic; - - -- CMD port timing registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : buffer unsigned(7 downto 0); - PIO_cmdport_IORDYen : out std_logic; - - -- data-port0 timing registers - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : buffer unsigned(7 downto 0); - PIO_dport0_IORDYen : out std_logic; - - -- data-port1 timing registers - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : buffer unsigned(7 downto 0); - PIO_dport1_IORDYen : out std_logic; - - -- DMA device0 timing registers - DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc : buffer unsigned(7 downto 0); - - -- DMA device1 timing registers - DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc : buffer unsigned(7 downto 0) - ); -end entity atahost_wb_slave; - -architecture structural of atahost_wb_slave is - -- - -- constants - -- - - -- addresses - alias ATA_DEV_ADR : std_logic is adr_i(6); - alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2); - - constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000"; - constant ATA_STAT_REG : unsigned(3 downto 0) := "0001"; - constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010"; - constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011"; - constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100"; - constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101"; - constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110"; - -- reserved -- - constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111"; - - -- - -- function declarations - -- - -- overload '=' to compare two unsigned numbers - function "=" (a, b : unsigned) return std_logic is - alias la: unsigned(1 to a'length) is a; - alias lb: unsigned(1 to b'length) is b; - variable result : std_logic; - begin - -- check vector length - assert a'length = b'length - report "std_logic_vector comparison: operands of unequal lengths" - severity FAILURE; - - result := '1'; - for n in 1 to a'length loop - result := result and not (la(n) xor lb(n)); - end loop; - - return result; - end; - - -- primary address decoder - signal CONsel : std_logic; -- controller select, IDE devices select - signal berr, brty : std_logic; -- bus error, bus retry - - -- registers - signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers - -begin - -- - -- generate bus cycle / address decoder - -- - gen_bc_dec: block - signal w_acc, dw_acc : std_logic; -- word access, double word access - signal store_pp_full : std_logic; - begin - -- word / double word - w_acc <= sel_i(1) and sel_i(0); - dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0); - - -- bus error - berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc; - - -- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full - PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full); - - -- CON accesses only 32bit wide - CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc; - DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT); - - -- bus retry (OCIDEC-3 and above) - -- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle - process(clk_i) - begin - if (clk_i'event and clk_i = '1') then - if (PIOsel = '0') then - store_pp_full <= PIOpp_full; - end if; - end if; - end process; - brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full); - end block gen_bc_dec; - - -- - -- generate registers - -- - register_block : block - signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers - signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers - signal sel_ctrl, sel_stat : std_logic; -- control / status register - begin - -- generate register select signals - sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG); - sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG); - sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD); - sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0); - sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1); - sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0); - sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1); - -- reserved 0x1C-0x38 -- - -- reserved 0x3C : DMA port -- - - -- generate control register - gen_ctrl_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - CtrlReg(31 downto 1) <= (others => '0'); - CtrlReg(0) <= '1'; -- set reset bit - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - CtrlReg(31 downto 1) <= (others => '0'); - CtrlReg(0) <= '1'; -- set reset bit - elsif (sel_ctrl = '1') then - CtrlReg <= dat_i; - end if; - end if; - end process gen_ctrl_reg; - -- assign bits - DMActrl_DMAen <= CtrlReg(15); - DMActrl_dir <= CtrlReg(13); - DMActrl_BeLeC1 <= CtrlReg(9); - DMActrl_BeLeC0 <= CtrlReg(8); - IDEctrl_IDEen <= CtrlReg(7); - IDEctrl_FATR1 <= CtrlReg(6); - IDEctrl_FATR0 <= CtrlReg(5); - IDEctrl_ppen <= CtrlReg(4); - PIO_dport1_IORDYen <= CtrlReg(3); - PIO_dport0_IORDYen <= CtrlReg(2); - PIO_cmdport_IORDYen <= CtrlReg(1); - IDEctrl_rst <= CtrlReg(0); - - -- generate status register clearable bits - gen_stat_reg: block - signal dirq, int : std_logic; - begin - gen_irq: process(clk_i, arst_i) - begin - if (arst_i = '0') then - int <= '0'; - dirq <= '0'; - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - int <= '0'; - dirq <= '0'; - else - int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0)); - dirq <= irq; - end if; - end if; - end process gen_irq; - - gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full) - begin - StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0') - - StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID - StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number - StatReg(15) <= DMAtip; - StatReg(10) <= DMARxEmpty; - StatReg(9) <= DMATxFull; - StatReg(8) <= DMA_dmarq; - StatReg(7) <= PIOtip; - StatReg(6) <= PIOpp_full; - StatReg(0) <= int; - end process; - end block gen_stat_reg; - - -- generate PIO compatible / command-port timing register - gen_PIO_cmdport_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_cmdport = '1') then - PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8)); - PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16)); - PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_cmdport_reg; - - -- generate PIO device0 timing register - gen_PIO_dport0_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_dport0 = '1') then - PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_dport0_T2 <= unsigned(dat_i(15 downto 8)); - PIO_dport0_T4 <= unsigned(dat_i(23 downto 16)); - PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_dport0_reg; - - -- generate PIO device1 timing register - gen_PIO_dport1_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_dport1 = '1') then - PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_dport1_T2 <= unsigned(dat_i(15 downto 8)); - PIO_dport1_T4 <= unsigned(dat_i(23 downto 16)); - PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_dport1_reg; - - -- generate DMA device0 timing register - gen_DMA_dev0_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (sel_DMA_dev0 = '1') then - DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0)); - DMA_dev0_Td <= unsigned(dat_i(15 downto 8)); - DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_DMA_dev0_reg; - - -- generate DMA device1 timing register - gen_DMA_dev1_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (sel_DMA_dev1 = '1') then - DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0)); - DMA_dev1_Td <= unsigned(dat_i(15 downto 8)); - DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_DMA_dev1_reg; - - end block register_block; - - -- - -- generate WISHBONE interconnect signals - -- - gen_WB_sigs: block - signal Q : std_logic_vector(31 downto 0); - begin - -- generate acknowledge signal - ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK - - -- generate error signal - err_o <= cyc_i and stb_i and berr; - - -- generate retry signal - rty_o <= cyc_i and stb_i and brty; - - -- assign interrupt signal - inta_o <= StatReg(0); - - -- generate output multiplexor - with ATA_ADR select - Q <= CtrlReg when ATA_CTRL_REG, -- control register - StatReg when ATA_STAT_REG, -- status register - std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register - std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0 - std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1 - std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0 - std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1 - DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register - (others => '0') when others; - - dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q; - end block gen_WB_sigs; - -end architecture structural; \ No newline at end of file Index: trunk/rtl/vhdl/ocidec2/atahost_controller.vhd =================================================================== --- trunk/rtl/vhdl/ocidec2/atahost_controller.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec2/atahost_controller.vhd (nonexistent) @@ -1,350 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- ATA/ATAPI-5 Controller (OCIDEC-2) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 18th, 2001. Initial release --- rev.: 1.0a april 12th, 2001. Removed references to records.vhd --- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0' --- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device. --- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). --- --- CVS Log --- --- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $ --- --- $Date: 2002-05-19 06:07:09 $ --- $Revision: 1.2 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - --- --- OCIDEC2 supports: --- -Common Compatible timing access to all connected devices --- -Separate timing accesses to data port --- -No DMA support - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - irq : out std_logic; -- interrupt request signal - - -- control / registers - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - -- PIO registers - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - PIOreq : in std_logic; -- PIO transfer request - PIOack : buffer std_logic; -- PIO transfer ended - PIOa : in unsigned(3 downto 0); -- PIO address - PIOd : in std_logic_vector(15 downto 0); -- PIO data in - PIOq : out std_logic_vector(15 downto 0); -- PIO data out - PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read - - -- ATA signals - RESETn : out std_logic; - DDi : in std_logic_vector(15 downto 0); - DDo : out std_logic_vector(15 downto 0); - DDoe : out std_logic; - DA : out unsigned(2 downto 0); - CS0n : out std_logic; - CS1n : out std_logic; - - DIORn : out std_logic; - DIOWn : out std_logic; - IORDY : in std_logic; - INTRQ : in std_logic - ); -end entity atahost_controller; - -architecture structural of atahost_controller is - -- - -- component declarations - -- - component atahost_pio_actrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - SelDev : in std_logic; -- Selected device - - go : in std_logic; -- Start transfer sequence - done : out std_logic; -- Transfer sequence done - dir : in std_logic; -- Transfer direction '1'=write, '0'=read - a : in unsigned(3 downto 0); -- PIO transfer address - q : out std_logic_vector(15 downto 0); -- Data read from ATA devices - - DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus - oe : buffer std_logic; -- DDbus output-enable signal - - DIOR, - DIOW : buffer std_logic; - IORDY : in std_logic - ); - end component atahost_pio_actrl; - - -- - -- signals - -- - signal SelDev : std_logic; -- selected device - - signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller - signal PIOdone : std_logic; -- PIO timing controller done - - -- PIO signals - signal PIOdior, PIOdiow : std_logic; - signal PIOoe : std_logic; - - -- synchronized ATA inputs - signal sIORDY : std_logic; - -begin - - -- - -- synchronize incoming signals - -- - synch_incoming: block - signal cIORDY : std_logic; -- capture IORDY - signal cINTRQ : std_logic; -- capture INTRQ - begin - process(clk) - begin - if (clk'event and clk = '1') then - cIORDY <= IORDY; - cINTRQ <= INTRQ; - - sIORDY <= cIORDY; - irq <= cINTRQ; - end if; - end process; - end block synch_incoming; - - -- - -- generate ATA signals - -- - gen_ata_sigs: block - begin - -- generate registers for ATA signals - gen_regs: process(clk, nReset) - begin - if (nReset = '0') then - RESETn <= '0'; - DIORn <= '1'; - DIOWn <= '1'; - DA <= (others => '0'); - CS0n <= '1'; - CS1n <= '1'; - DDo <= (others => '0'); - DDoe <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - RESETn <= '0'; - DIORn <= '1'; - DIOWn <= '1'; - DA <= (others => '0'); - CS0n <= '1'; - CS1n <= '1'; - DDo <= (others => '0'); - DDoe <= '0'; - else - RESETn <= not IDEctrl_rst; - DA <= PIOa(2 downto 0); - CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0' - CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1' - - DDo <= PIOd; - DDoe <= PIOoe; - DIORn <= not PIOdior; - DIOWn <= not PIOdiow; - end if; - end if; - end process gen_regs; - end block gen_ata_sigs; - - -- - -- generate selected device - -- - gen_seldev: process(clk) - variable Asel : std_logic; -- address selected - begin - Asel := not PIOa(3) and PIOa(2) and PIOa(1) and not PIOa(0); -- header/device register - - if (clk'event and clk = '1') then - if ( (PIOdone = '1') and (Asel = '1') and (PIOwe = '1') ) then - SelDev <= PIOd(4); - end if; - end if; - end process gen_seldev; - - -- generate PIOgo signal - gen_PIOgo: process(clk, nReset) - begin - if (nReset = '0') then - dPIOreq <= '0'; - PIOgo <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - dPIOreq <= '0'; - PIOgo <= '0'; - else - dPIOreq <= PIOreq and not PIOack; - PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen; - end if; - end - end process gen_PIOgo; - -- - -- Hookup PIO access controller - -- - PIO_access_control: atahost_pio_actrl - generic map( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map( - clk => clk, - nReset => nReset, - rst => rst, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - cmdport_T1 => cmdport_T1, - cmdport_T2 => cmdport_T2, - cmdport_T4 => cmdport_T4, - cmdport_Teoc => cmdport_Teoc, - cmdport_IORDYen => cmdport_IORDYen, - dport0_T1 => dport0_T1, - dport0_T2 => dport0_T2, - dport0_T4 => dport0_T4, - dport0_Teoc => dport0_Teoc, - dport0_IORDYen => dport0_IORDYen, - dport1_T1 => dport1_T1, - dport1_T2 => dport1_T2, - dport1_T4 => dport1_T4, - dport1_Teoc => dport1_Teoc, - dport1_IORDYen => dport1_IORDYen, - SelDev => SelDev, - go => PIOgo, - done => PIOdone, - dir => PIOwe, - a => PIOa, - q => PIOq, - DDi => DDi, - oe => PIOoe, - DIOR => PIOdior, - DIOW => PIOdiow, - IORDY => sIORDY - ); - - -- generate acknowledge - gen_ack: process(clk) - begin - if (clk'event and clk = '1') the - PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request) - end if; - end process gen_ack; -end architecture structural; - Index: trunk/rtl/vhdl/ocidec3/ro_cnt.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/ro_cnt.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/ro_cnt.vhd (nonexistent) @@ -1,131 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- Run-Once Counter ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:49:25 rherveille Exp $ --- --- $Date: 2002-03-01 03:49:25 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); -end entity ro_cnt; - -architecture structural of ro_cnt is - component ud_cnt is - generic( - SIZE : natural := 8; - RESD : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - ud : in std_logic := '0'; -- up / not down - nld : in std_logic := '1'; -- synchronous active low load - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0); -- current counter value - - rci : in std_logic := '1'; -- carry input - rco : out std_logic -- carry output - ); - end component ud_cnt; - - signal rci, rco, nld : std_logic; -begin - gen_ctrl: process(clk, nReset) - begin - if (nReset = '0') then - rci <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - rci <= '0'; - else - rci <= go or (rci and not rco); - end if; - end if; - end process; - - nld <= not go; - - -- hookup counter - cnt : ud_cnt - generic map ( - SIZE => SIZE, - RESD => ID - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - cnt_en => cnt_en, - ud => UD, - nld => nld, - D => D, - Q => Q, - rci => rci, - rco => rco - ); - - done <= rco; -end architecture structural; Index: trunk/rtl/vhdl/ocidec3/atahost_top.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_top.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_top.vhd (nonexistent) @@ -1,577 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- ATA/ATAPI-5 IDE controller with DMA support ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- rev.: 1.0 Alpha version Januar 1st, 2001 --- rev.: 1.0a Removed all references to records.vhd. Make core compatible with VHDL to Verilog translator tools --- Changed DMA_req signal generation. Make the core compatible with the latest version of the OpenCores DMA engine --- rev.: 1.1 june 18th, 2001. Changed wishbone address-input from ADR_I(4 downto 0) to ADR(6 downto 2) --- rev.: 1.1a june 19th, 2001. Simplified DAT_O output multiplexor --- --- CVS Log --- --- $Id: atahost_top.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - --- --- DeviceType: OCIDEC-3: OpenCores IDE Controller type3 --- Features: PIO Compatible Timing, PIO Fast Timing 0/1, Single/Multiword DMA Timing 0/1 --- DeviceID: 0x03 --- RevNo : 0x00 - --- --- Host signals: --- Reset --- DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. --- DIOW- write strobe. The rising edge latches data from DD into the device. --- DMACK- DMA acknowledge --- DA(2:0) 3bit binary coded adress --- CS0- select command block registers --- CS1- select control block registers - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_top is - generic( - ARST_LVL : std_logic := '0'; -- asynchronous reset level - - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - wb_clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - wb_rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - wb_cyc_i : in std_logic; -- valid bus cycle input - wb_stb_i : in std_logic; -- strobe/core select input - wb_ack_o : out std_logic; -- strobe acknowledge output - wb_rty_o : out std_logic; -- retry output - wb_err_o : out std_logic; -- error output - wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in - wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out - wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - wb_we_i : in std_logic; -- Write enable input - wb_inta_o : out std_logic; -- interrupt request signal IDE0 - - -- DMA engine signals - DMA_req : out std_logic; -- DMA request - DMA_Ack : in std_logic; -- DMA acknowledge - - -- ATA signals - resetn_pad_o : out std_logic; - dd_pad_i : in std_logic_vector(15 downto 0); - dd_pad_o : out std_logic_vector(15 downto 0); - dd_padoe_o : out std_logic; - da_pad_o : out unsigned(2 downto 0); - cs0n_pad_o : out std_logic; - cs1n_pad_o : out std_logic; - - diorn_pad_o : out std_logic; - diown_pad_o : out std_logic; - iordy_pad_i : in std_logic; - intrq_pad_i : in std_logic; - - dmarq_pad_i : in std_logic; - dmackn_pad_o : out std_logic - ); -end entity atahost_top; - -architecture structural of atahost_top is - -- - -- Device ID - -- - constant DeviceId : unsigned(3 downto 0) := x"3"; - constant RevisionNo : unsigned(3 downto 0) := x"0"; - - -- - -- component declarations - -- - component atahost_wb_slave is - generic( - DeviceID : unsigned(3 downto 0) := x"0"; - RevisionNo : unsigned(3 downto 0) := x"0"; - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - cyc_i : in std_logic; -- valid bus cycle input - stb_i : in std_logic; -- strobe/core select input - ack_o : out std_logic; -- strobe acknowledge output - rty_o : out std_logic; -- retry output - err_o : out std_logic; -- error output - adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - dat_i : in std_logic_vector(31 downto 0); -- Databus in - dat_o : out std_logic_vector(31 downto 0); -- Databus out - sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - we_i : in std_logic; -- Write enable input - inta_o : out std_logic; -- interrupt request signal IDE0 - - -- PIO control input - PIOsel : buffer std_logic; - PIOtip, -- PIO transfer in progress - PIOack : in std_logic; -- PIO acknowledge signal - PIOq : in std_logic_vector(15 downto 0); -- PIO data input - PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full - irq : in std_logic; -- interrupt signal input - - -- DMA control inputs - DMAsel : out std_logic; - DMAtip, -- DMA transfer in progress - DMAack, - DMARxEmpty, -- DMA receive buffer empty - DMATxFull, -- DMA transmit buffer full - DMA_dmarq : in std_logic; -- wishbone DMA request - DMAq : in std_logic_vector(31 downto 0); - - -- outputs - -- control register outputs - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR1, - IDEctrl_FATR0, - IDEctrl_ppen, - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : out std_logic; - - -- CMD port timing registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : buffer unsigned(7 downto 0); - PIO_cmdport_IORDYen : out std_logic; - - -- data-port0 timing registers - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : buffer unsigned(7 downto 0); - PIO_dport0_IORDYen : out std_logic; - - -- data-port1 timing registers - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : buffer unsigned(7 downto 0); - PIO_dport1_IORDYen : out std_logic; - - -- DMA device0 timing registers - DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc : buffer unsigned(7 downto 0); - - -- DMA device1 timing registers - DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc : buffer unsigned(7 downto 0) - ); - end component atahost_wb_slave; - - component atahost_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - irq : out std_logic; -- interrupt request signal - - -- control / registers - IDEctrl_IDEen, - IDEctrl_rst, - IDEctrl_ppen, - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; -- control register settings - - a : in unsigned(3 downto 0); -- address input - d : in std_logic_vector(31 downto 0); -- data input - we : in std_logic; -- write enable input '1'=write, '0'=read - - -- PIO registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : in unsigned(7 downto 0); - PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings - - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : in unsigned(7 downto 0); - PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings - - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : in unsigned(7 downto 0); - PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings - - PIOsel : in std_logic; -- PIO controller select - PIOack : out std_logic; -- PIO controller acknowledge - PIOq : out std_logic_vector(15 downto 0); -- PIO data out - PIOtip : buffer std_logic; -- PIO transfer in progress - PIOpp_full : out std_logic; -- PIO Write PingPong full - - -- DMA registers - DMA_dev0_Td, - DMA_dev0_Tm, - DMA_dev0_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device0 - - DMA_dev1_Td, - DMA_dev1_Tm, - DMA_dev1_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device1 - - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : in std_logic; -- DMA settings - - DMAsel : in std_logic; -- DMA controller select - DMAack : out std_logic; -- DMA controller acknowledge - DMAq : out std_logic_vector(31 downto 0); -- DMA data out - DMAtip : buffer std_logic; -- DMA transfer in progress - DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line - - DMATxFull : buffer std_logic; -- DMA transmit buffer full - DMARxEmpty : buffer std_logic; -- DMA receive buffer empty - - DMA_req : out std_logic; -- DMA request to external DMA engine - DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine - - -- ATA signals - RESETn : out std_logic; - DDi : in std_logic_vector(15 downto 0); - DDo : out std_logic_vector(15 downto 0); - DDoe : out std_logic; - DA : out unsigned(2 downto 0); - CS0n : out std_logic; - CS1n : out std_logic; - - DMARQ : in std_logic; - DMACKn : out std_logic; - DIORn : out std_logic; - DIOWn : out std_logic; - IORDY : in std_logic; - INTRQ : in std_logic - ); - end component atahost_controller; - - -- asynchronous reset signal - signal arst_signal : std_logic; - - -- primary address decoder - signal PIOsel, DMAsel : std_logic; -- controller select, IDE devices select - - -- registers - -- IDE control register - signal IDEctrl_IDEen, IDEctrl_rst, IDEctrl_ppen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic; - -- PIO compatible timing settings - signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0); - signal PIO_cmdport_IORDYen : std_logic; - -- PIO data register device0 timing settings - signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : unsigned(7 downto 0); - signal PIO_dport0_IORDYen : std_logic; - -- PIO data register device1 timing settings - signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : unsigned(7 downto 0); - signal PIO_dport1_IORDYen : std_logic; - -- DMA control register - signal DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1 : std_logic; - -- DMA data port device0 timing settings - signal DMA_dev0_Td, DMA_dev0_Tm, DMA_dev0_Teoc : unsigned(7 downto 0); - -- DMA data port device1 timing settings - signal DMA_dev1_Td, DMA_dev1_Tm, DMA_dev1_Teoc : unsigned(7 downto 0); - - signal PIOack, DMAack, PIOtip, DMAtip : std_logic; - signal PIOq : std_logic_vector(15 downto 0); - signal PIOpp_full : std_logic; - signal DMAq : std_logic_vector(31 downto 0); - signal DMA_dmarq : std_logic; -- synchronized version of DMARQ - - signal DMATxFull, DMARxEmpty : std_logic; - - signal irq : std_logic; -- ATA bus IRQ signal - -begin - -- generate asynchronous reset level - arst_signal <= arst_i xor ARST_LVL; - - -- - -- hookup wishbone slave - -- - u0: atahost_wb_slave - generic map( - DeviceID => DeviceID, - RevisionNo => RevisionNo, - - -- PIO mode 0 settings - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc, - - -- Multiword DMA mode 0 settings - -- OCIDEC-1 does not support DMA, set registers to zero - DMA_mode0_Tm => 0, - DMA_mode0_Td => 0, - DMA_mode0_Teoc => 0 - ) - port map( - -- WISHBONE SYSCON signals - clk_i => wb_clk_i, - arst_i => arst_signal, - rst_i => wb_rst_i, - - -- WISHBONE SLAVE signals - cyc_i => wb_cyc_i, - stb_i => wb_stb_i, - ack_o => wb_ack_o, - rty_o => wb_rty_o, - err_o => wb_err_o, - adr_i => wb_adr_i, - dat_i => wb_dat_i, - dat_o => wb_dat_o, - sel_i => wb_sel_i, - we_i => wb_we_i, - inta_o => wb_inta_o, - - -- PIO control inputs - PIOsel => PIOsel, - PIOtip => PIOtip, - PIOack => PIOack, - PIOq => PIOq, - PIOpp_full => PIOpp_full, - irq => irq, - - -- DMA control inputs - DMAsel => DMAsel, - DMAtip => DMAtip, - DMAack => DMAack, - DMARxEmpty => DMARxEmpty, - DMATxFull => DMATxFull, - DMA_dmarq => DMA_dmarq, - DMAq => DMAq, - - -- outputs - -- control register outputs - IDEctrl_rst => IDEctrl_rst, - IDEctrl_IDEen => IDEctrl_IDEen, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - IDEctrl_ppen => IDEctrl_ppen, - - DMActrl_DMAen => DMActrl_DMAen, - DMActrl_dir => DMActrl_dir, - DMActrl_BeLeC0 => DMActrl_BeLeC0, - DMActrl_BeLeC1 => DMActrl_BeLeC1, - - -- CMD port timing registers - PIO_cmdport_T1 => PIO_cmdport_T1, - PIO_cmdport_T2 => PIO_cmdport_T2, - PIO_cmdport_T4 => PIO_cmdport_T4, - PIO_cmdport_Teoc => PIO_cmdport_Teoc, - PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, - - -- data-port0 timing registers - PIO_dport0_T1 => PIO_dport0_T1, - PIO_dport0_T2 => PIO_dport0_T2, - PIO_dport0_T4 => PIO_dport0_T4, - PIO_dport0_Teoc => PIO_dport0_Teoc, - PIO_dport0_IORDYen => PIO_dport0_IORDYen, - - -- data-port1 timing registers - PIO_dport1_T1 => PIO_dport1_T1, - PIO_dport1_T2 => PIO_dport1_T2, - PIO_dport1_T4 => PIO_dport1_T4, - PIO_dport1_Teoc => PIO_dport1_Teoc, - PIO_dport1_IORDYen => PIO_dport1_IORDYen, - - -- DMA device0 timing registers - DMA_dev0_Tm => DMA_dev0_Tm, - DMA_dev0_Td => DMA_dev0_Td, - DMA_dev0_Teoc => DMA_dev0_Teoc, - - -- DMA device1 timing registers - DMA_dev1_Tm => DMA_dev1_Tm, - DMA_dev1_Td => DMA_dev1_Td, - DMA_dev1_Teoc => DMA_dev1_Teoc - ); - - - -- - -- hookup controller section - -- - u1: atahost_controller - generic map( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc, - DMA_mode0_Tm => DMA_mode0_Tm, - DMA_mode0_Td => DMA_mode0_Td, - DMA_mode0_Teoc => DMA_mode0_Teoc - ) - port map( - clk => wb_clk_i, - nReset => arst_signal, - rst => wb_rst_i, - irq => irq, - IDEctrl_IDEen => IDEctrl_IDEen, - IDEctrl_rst => IDEctrl_rst, - IDEctrl_ppen => IDEctrl_ppen, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - a => wb_adr_i(5 downto 2), - d => wb_dat_i, - we => wb_we_i, - PIO_cmdport_T1 => PIO_cmdport_T1, - PIO_cmdport_T2 => PIO_cmdport_T2, - PIO_cmdport_T4 => PIO_cmdport_T4, - PIO_cmdport_Teoc => PIO_cmdport_Teoc, - PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, - PIO_dport0_T1 => PIO_dport0_T1, - PIO_dport0_T2 => PIO_dport0_T2, - PIO_dport0_T4 => PIO_dport0_T4, - PIO_dport0_Teoc => PIO_dport0_Teoc, - PIO_dport0_IORDYen => PIO_dport0_IORDYen, - PIO_dport1_T1 => PIO_dport1_T1, - PIO_dport1_T2 => PIO_dport1_T2, - PIO_dport1_T4 => PIO_dport1_T4, - PIO_dport1_Teoc => PIO_dport1_Teoc, - PIO_dport1_IORDYen => PIO_dport1_IORDYen, - PIOsel => PIOsel, - PIOack => PIOack, - PIOq => PIOq, - PIOtip => PIOtip, - PIOpp_full => PIOpp_full, - DMActrl_DMAen => DMActrl_DMAen, - DMActrl_dir => DMActrl_dir, - DMActrl_BeLeC0 => DMActrl_BeLeC0, - DMActrl_BeLeC1 => DMActrl_BeLeC1, - DMA_dev0_Td => DMA_dev0_Td, - DMA_dev0_Tm => DMA_dev0_Tm, - DMA_dev0_Teoc => DMA_dev0_Teoc, - DMA_dev1_Td => DMA_dev1_Td, - DMA_dev1_Tm => DMA_dev1_Tm, - DMA_dev1_Teoc => DMA_dev1_Teoc, - DMAsel => DMAsel, - DMAack => DMAack, - DMAq => DMAq, - DMAtip => DMAtip, - DMA_dmarq => DMA_dmarq, - DMATxFull => DMATxFull, - DMARxEmpty => DMARxEmpty, - DMA_req => DMA_req, - DMA_ack => DMA_ack, - RESETn => resetn_pad_o, - DDi => dd_pad_i, - DDo => dd_pad_o, - DDoe => dd_padoe_o, - DA => da_pad_o, - CS0n => cs0n_pad_o, - CS1n => cs1n_pad_o, - DIORn => diorn_pad_o, - DIOWn => diown_pad_o, - IORDY => iordy_pad_i, - INTRQ => intrq_pad_i, - DMARQ => dmarq_pad_i, - DMACKn => dmackn_pad_o - ); - -end architecture structural; - - - Index: trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd (nonexistent) @@ -1,467 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- Wishbone Slave (common for all OCIDEC cores) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_wb_slave is - generic( - DeviceID : unsigned(3 downto 0) := x"0"; - RevisionNo : unsigned(3 downto 0) := x"0"; - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - -- WISHBONE SYSCON signals - clk_i : in std_logic; -- master clock in - arst_i : in std_logic := '1'; -- asynchronous active low reset - rst_i : in std_logic := '0'; -- synchronous active high reset - - -- WISHBONE SLAVE signals - cyc_i : in std_logic; -- valid bus cycle input - stb_i : in std_logic; -- strobe/core select input - ack_o : out std_logic; -- strobe acknowledge output - rty_o : out std_logic; -- retry output - err_o : out std_logic; -- error output - adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected - -- A5 = '1' CS1- asserted, '0' CS0- asserted - -- A4..A2 ATA address lines - -- A6 = '0' ATA controller selected - dat_i : in std_logic_vector(31 downto 0); -- Databus in - dat_o : out std_logic_vector(31 downto 0); -- Databus out - sel_i : in std_logic_vector(3 downto 0); -- Byte select signals - we_i : in std_logic; -- Write enable input - inta_o : out std_logic; -- interrupt request signal IDE0 - - -- PIO control input - PIOsel : buffer std_logic; - PIOtip, -- PIO transfer in progress - PIOack : in std_logic; -- PIO acknowledge signal - PIOq : in std_logic_vector(15 downto 0); -- PIO data input - PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full - irq : in std_logic; -- interrupt signal input - - -- DMA control inputs - DMAsel : out std_logic; - DMAtip, -- DMA transfer in progress - DMAack, -- DMA transfer acknowledge - DMARxEmpty, -- DMA receive buffer empty - DMATxFull, -- DMA transmit buffer full - DMA_dmarq : in std_logic; -- wishbone DMA request - DMAq : in std_logic_vector(31 downto 0); - - -- outputs - -- control register outputs - IDEctrl_rst, - IDEctrl_IDEen, - IDEctrl_FATR1, - IDEctrl_FATR0, - IDEctrl_ppen, - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : out std_logic; - - -- CMD port timing registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : buffer unsigned(7 downto 0); - PIO_cmdport_IORDYen : out std_logic; - - -- data-port0 timing registers - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : buffer unsigned(7 downto 0); - PIO_dport0_IORDYen : out std_logic; - - -- data-port1 timing registers - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : buffer unsigned(7 downto 0); - PIO_dport1_IORDYen : out std_logic; - - -- DMA device0 timing registers - DMA_dev0_Tm, - DMA_dev0_Td, - DMA_dev0_Teoc : buffer unsigned(7 downto 0); - - -- DMA device1 timing registers - DMA_dev1_Tm, - DMA_dev1_Td, - DMA_dev1_Teoc : buffer unsigned(7 downto 0) - ); -end entity atahost_wb_slave; - -architecture structural of atahost_wb_slave is - -- - -- constants - -- - - -- addresses - alias ATA_DEV_ADR : std_logic is adr_i(6); - alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2); - - constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000"; - constant ATA_STAT_REG : unsigned(3 downto 0) := "0001"; - constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010"; - constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011"; - constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100"; - constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101"; - constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110"; - -- reserved -- - constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111"; - - -- - -- function declarations - -- - -- overload '=' to compare two unsigned numbers - function "=" (a, b : unsigned) return std_logic is - alias la: unsigned(1 to a'length) is a; - alias lb: unsigned(1 to b'length) is b; - variable result : std_logic; - begin - -- check vector length - assert a'length = b'length - report "std_logic_vector comparison: operands of unequal lengths" - severity FAILURE; - - result := '1'; - for n in 1 to a'length loop - result := result and not (la(n) xor lb(n)); - end loop; - - return result; - end; - - -- primary address decoder - signal CONsel : std_logic; -- controller select, IDE devices select - signal berr, brty : std_logic; -- bus error, bus retry - - -- registers - signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers - -begin - -- - -- generate bus cycle / address decoder - -- - gen_bc_dec: block - signal w_acc, dw_acc : std_logic; -- word access, double word access - signal store_pp_full : std_logic; - begin - -- word / double word - w_acc <= sel_i(1) and sel_i(0); - dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0); - - -- bus error - berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc; - - -- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full - PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full); - - -- CON accesses only 32bit wide - CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc; - DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT); - - -- bus retry (OCIDEC-3 and above) - -- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle - process(clk_i) - begin - if (clk_i'event and clk_i = '1') then - if (PIOsel = '0') then - store_pp_full <= PIOpp_full; - end if; - end if; - end process; - brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full); - end block gen_bc_dec; - - -- - -- generate registers - -- - register_block : block - signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers - signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers - signal sel_ctrl, sel_stat : std_logic; -- control / status register - begin - -- generate register select signals - sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG); - sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG); - sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD); - sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0); - sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1); - sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0); - sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1); - -- reserved 0x1C-0x38 -- - -- reserved 0x3C : DMA port -- - - -- generate control register - gen_ctrl_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - CtrlReg(31 downto 1) <= (others => '0'); - CtrlReg(0) <= '1'; -- set reset bit - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - CtrlReg(31 downto 1) <= (others => '0'); - CtrlReg(0) <= '1'; -- set reset bit - elsif (sel_ctrl = '1') then - CtrlReg <= dat_i; - end if; - end if; - end process gen_ctrl_reg; - -- assign bits - DMActrl_DMAen <= CtrlReg(15); - DMActrl_dir <= CtrlReg(13); - DMActrl_BeLeC1 <= CtrlReg(9); - DMActrl_BeLeC0 <= CtrlReg(8); - IDEctrl_IDEen <= CtrlReg(7); - IDEctrl_FATR1 <= CtrlReg(6); - IDEctrl_FATR0 <= CtrlReg(5); - IDEctrl_ppen <= CtrlReg(4); - PIO_dport1_IORDYen <= CtrlReg(3); - PIO_dport0_IORDYen <= CtrlReg(2); - PIO_cmdport_IORDYen <= CtrlReg(1); - IDEctrl_rst <= CtrlReg(0); - - -- generate status register clearable bits - gen_stat_reg: block - signal dirq, int : std_logic; - begin - gen_irq: process(clk_i, arst_i) - begin - if (arst_i = '0') then - int <= '0'; - dirq <= '0'; - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - int <= '0'; - dirq <= '0'; - else - int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0)); - dirq <= irq; - end if; - end if; - end process gen_irq; - - gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full) - begin - StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0') - - StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID - StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number - StatReg(15) <= DMAtip; - StatReg(10) <= DMARxEmpty; - StatReg(9) <= DMATxFull; - StatReg(8) <= DMA_dmarq; - StatReg(7) <= PIOtip; - StatReg(6) <= PIOpp_full; - StatReg(0) <= int; - end process; - end block gen_stat_reg; - - -- generate PIO compatible / command-port timing register - gen_PIO_cmdport_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_cmdport = '1') then - PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8)); - PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16)); - PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_cmdport_reg; - - -- generate PIO device0 timing register - gen_PIO_dport0_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_dport0 = '1') then - PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_dport0_T2 <= unsigned(dat_i(15 downto 8)); - PIO_dport0_T4 <= unsigned(dat_i(23 downto 16)); - PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_dport0_reg; - - -- generate PIO device1 timing register - gen_PIO_dport1_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); - PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); - PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); - PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); - elsif (sel_PIO_dport1 = '1') then - PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0)); - PIO_dport1_T2 <= unsigned(dat_i(15 downto 8)); - PIO_dport1_T4 <= unsigned(dat_i(23 downto 16)); - PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_PIO_dport1_reg; - - -- generate DMA device0 timing register - gen_DMA_dev0_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (sel_DMA_dev0 = '1') then - DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0)); - DMA_dev0_Td <= unsigned(dat_i(15 downto 8)); - DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_DMA_dev0_reg; - - -- generate DMA device1 timing register - gen_DMA_dev1_reg: process(clk_i, arst_i) - begin - if (arst_i = '0') then - DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (clk_i'event and clk_i = '1') then - if (rst_i = '1') then - DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); - DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); - DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); - elsif (sel_DMA_dev1 = '1') then - DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0)); - DMA_dev1_Td <= unsigned(dat_i(15 downto 8)); - DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24)); - end if; - end if; - end process gen_DMA_dev1_reg; - - end block register_block; - - -- - -- generate WISHBONE interconnect signals - -- - gen_WB_sigs: block - signal Q : std_logic_vector(31 downto 0); - begin - -- generate acknowledge signal - ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK - - -- generate error signal - err_o <= cyc_i and stb_i and berr; - - -- generate retry signal - rty_o <= cyc_i and stb_i and brty; - - -- assign interrupt signal - inta_o <= StatReg(0); - - -- generate output multiplexor - with ATA_ADR select - Q <= CtrlReg when ATA_CTRL_REG, -- control register - StatReg when ATA_STAT_REG, -- status register - std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register - std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0 - std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1 - std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0 - std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1 - DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register - (others => '0') when others; - - dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q; - end block gen_WB_sigs; - -end architecture structural; \ No newline at end of file Index: trunk/rtl/vhdl/ocidec3/atahost_controller.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_controller.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_controller.vhd (nonexistent) @@ -1,575 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- ATA/ATAPI-5 Host controller (OCIDEC-3) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 8th, 2001. Initial release --- --- CVS Log --- --- $Id: atahost_controller.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - - -- Multiword DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - irq : out std_logic; -- interrupt request signal - - -- control / registers - IDEctrl_IDEen, - IDEctrl_rst, - IDEctrl_ppen, - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; -- control register settings - - a : in unsigned(3 downto 0); -- address input - d : in std_logic_vector(31 downto 0); -- data input - we : in std_logic; -- write enable input '1'=write, '0'=read - - -- PIO registers - PIO_cmdport_T1, - PIO_cmdport_T2, - PIO_cmdport_T4, - PIO_cmdport_Teoc : in unsigned(7 downto 0); - PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings - - PIO_dport0_T1, - PIO_dport0_T2, - PIO_dport0_T4, - PIO_dport0_Teoc : in unsigned(7 downto 0); - PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings - - PIO_dport1_T1, - PIO_dport1_T2, - PIO_dport1_T4, - PIO_dport1_Teoc : in unsigned(7 downto 0); - PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings - - PIOsel : in std_logic; -- PIO controller select - PIOack : out std_logic; -- PIO controller acknowledge - PIOq : out std_logic_vector(15 downto 0); -- PIO data out - PIOtip : buffer std_logic; -- PIO transfer in progress - PIOpp_full : out std_logic; -- PIO Write PingPong full - - -- DMA registers - DMA_dev0_Td, - DMA_dev0_Tm, - DMA_dev0_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device0 - - DMA_dev1_Td, - DMA_dev1_Tm, - DMA_dev1_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device1 - - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : in std_logic; -- DMA settings - - DMAsel : in std_logic; -- DMA controller select - DMAack : out std_logic; -- DMA controller acknowledge - DMAq : out std_logic_vector(31 downto 0); -- DMA data out - DMAtip : buffer std_logic; -- DMA transfer in progress - DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line - - DMATxFull : buffer std_logic; -- DMA transmit buffer full - DMARxEmpty : buffer std_logic; -- DMA receive buffer empty - - DMA_req : out std_logic; -- DMA request to external DMA engine - DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine - - -- ATA signals - RESETn : out std_logic; - DDi : in std_logic_vector(15 downto 0); - DDo : out std_logic_vector(15 downto 0); - DDoe : out std_logic; - DA : out unsigned(2 downto 0); - CS0n : out std_logic; - CS1n : out std_logic; - - DMARQ : in std_logic; - DMACKn : out std_logic; - DIORn : out std_logic; - DIOWn : out std_logic; - IORDY : in std_logic; - INTRQ : in std_logic - ); -end entity atahost_controller; - -architecture structural of atahost_controller is - -- - -- component declarations - -- - component atahost_pio_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - -- control / registers - IDEctrl_IDEen, - IDEctrl_ppen, - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - -- PIO registers - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - sel : in std_logic; -- PIO controller selected - ack : out std_logic; -- PIO controller acknowledge - a : in unsigned(3 downto 0); -- lower address bits - we : in std_logic; -- write enable input - d : in std_logic_vector(15 downto 0); - q : out std_logic_vector(15 downto 0); - - PIOreq : out std_logic; -- PIO transfer request - PPFull : out std_logic; -- PIO Write PingPong Full - go : in std_logic; -- start PIO transfer - done : buffer std_logic; -- done with PIO transfer - - PIOa : out unsigned(3 downto 0); -- PIO address, address lines towards ATA devices - PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices - - SelDev : buffer std_logic; -- Selected Device, Dev-bit in ATA Device/Head register - - DDi : in std_logic_vector(15 downto 0); - DDoe : buffer std_logic; - - DIOR : buffer std_logic; - DIOW : buffer std_logic; - IORDY : in std_logic - ); - end component atahost_pio_controller; - - component atahost_dma_actrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst' - - sel : in std_logic; -- DMA buffers selected - we : in std_logic; -- write enable input - ack : out std_logic; -- acknowledge output - - dev0_Tm, - dev0_Td, - dev0_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 0 - dev1_Tm, - dev1_Td, - dev1_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 1 - - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : in std_logic; -- control register settings - - TxD : in std_logic_vector(31 downto 0); -- DMA transmit data - TxFull : buffer std_logic; -- DMA transmit buffer full - RxQ : out std_logic_vector(31 downto 0); -- DMA receive data - RxEmpty : buffer std_logic; -- DMA receive buffer empty - RxFull : out std_logic; -- DMA receive buffer full - DMA_req : out std_logic; -- DMA request to external DMA engine - DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine - - DMARQ : in std_logic; -- ATA devices request DMA transfer - - SelDev : in std_logic; -- Selected device - - Go : in std_logic; -- Start transfer sequence - Done : out std_logic; -- Transfer sequence done - - DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus - DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus - - DIOR, - DIOW : buffer std_logic - ); - end component atahost_dma_actrl; - - -- - -- signals - -- - signal SelDev : std_logic; -- selected device - signal DMARxFull : std_logic; -- DMA receive buffer full - - -- PIO / DMA signals - signal PIOgo, DMAgo : std_logic; -- start PIO / DMA timing controller - signal PIOdone, DMAdone : std_logic; -- PIO / DMA timing controller done - - -- PIO signals - signal PIOdior, PIOdiow : std_logic; - signal PIOoe : std_logic; - - -- PIO pingpong signals - signal PIOd : std_logic_vector(15 downto 0); - signal PIOa : unsigned(3 downto 0); - signal PIOreq : std_logic; - - -- DMA signals - signal DMAd : std_logic_vector(15 downto 0); - signal DMAdior, DMAdiow : std_logic; - - -- synchronized ATA inputs - signal sDMARQ, sIORDY : std_logic; - -begin - - -- - -- synchronize incoming signals - -- - synch_incoming: block - signal cDMARQ : std_logic; -- capture DMARQ - signal cIORDY : std_logic; -- capture IORDY - signal cINTRQ : std_logic; -- capture INTRQ - begin - process(clk) - begin - if (clk'event and clk = '1') then - cDMARQ <= DMARQ; - cIORDY <= IORDY; - cINTRQ <= INTRQ; - - sDMARQ <= cDMARQ; - sIORDY <= cIORDY; - irq <= cINTRQ; - end if; - end process; - - DMA_dmarq <= sDMARQ; - end block synch_incoming; - - -- - -- generate ATA signals - -- - gen_ata_sigs: block - signal iDDo : std_logic_vector(15 downto 0); - begin - -- generate registers for ATA signals - gen_regs: process(clk, nReset) - begin - if (nReset = '0') then - RESETn <= '0'; - DIORn <= '1'; - DIOWn <= '1'; - DA <= (others => '0'); - CS0n <= '1'; - CS1n <= '1'; - DDo <= (others => '0'); - DDoe <= '0'; - DMACKn <= '1'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - RESETn <= '0'; - DIORn <= '1'; - DIOWn <= '1'; - DA <= (others => '0'); - CS0n <= '1'; - CS1n <= '1'; - DDo <= (others => '0'); - DDoe <= '0'; - DMACKn <= '1'; - else - RESETn <= not IDEctrl_rst; - DA <= PIOa(2 downto 0); - CS0n <= not (not PIOa(3) and PIOtip); -- CS0 asserted when A(3) = '0', negate during DMA transfers - CS1n <= not ( PIOa(3) and PIOtip); -- CS1 asserted when A(3) = '1', negate during DMA transfers - - if (PIOtip = '1') then - DDo <= PIOd; - DDoe <= PIOoe; - DIORn <= not PIOdior; - DIOWn <= not PIOdiow; - else - DDo <= DMAd; - DDoe <= DMActrl_dir and DMAtip; - DIORn <= not DMAdior; - DIOWn <= not DMAdiow; - end if; - - DMACKn <= not DMAtip; - end if; - end if; - end process gen_regs; - end block gen_ata_sigs; - - -- - -- generate bus controller statemachine - -- - statemachine: block - type states is (idle, PIO_state, DMA_state); - signal nxt_state, c_state : states; -- next_state, current_state - - signal iPIOgo, iDMAgo : std_logic; - begin - -- generate next state decoder + output decoder - gen_nxt_state: process(c_state, DMActrl_DMAen, DMActrl_dir, PIOreq, sDMARQ, DMATxFull, DMARxFull, PIOdone, DMAdone) - begin - nxt_state <= c_state; -- initialy stay in current state - - iPIOgo <= '0'; - iDMAgo <= '0'; - - case c_state is - -- idle - when idle => - -- DMA transfer pending ? - if ( (sDMARQ = '1') and (DMActrl_DMAen = '1') ) then - if (( (DMActrl_dir = '1') and (DMATxFull = '1') ) or ( (DMActrl_dir = '0') and (DMARxFull = '0') )) then - nxt_state <= DMA_state; -- DMA transfer - iDMAgo <= '1'; -- start DMA timing controller - end if; - -- PIO transfer pending ? - elsif (PIOreq = '1') then - nxt_state <= PIO_state; -- PIO transfer - iPIOgo <= '1'; - end if; - - -- PIO transfer - when PIO_state => - if (PIOdone = '1') then - nxt_state <= idle; - end if; - - -- DMA transfer - when DMA_state => - if (DMAdone = '1') then - nxt_state <= idle; - end if; - - when others => - nxt_state <= idle; -- go to idle state - - end case; - end process gen_nxt_state; - - -- generate registers - gen_regs: process(clk, nReset) - begin - if (nReset = '0') then - c_state <= idle; - PIOgo <= '0'; - DMAgo <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - c_state <= idle; - PIOgo <= '0'; - DMAgo <= '0'; - else - c_state <= nxt_state; - PIOgo <= iPIOgo; - DMAgo <= iDMAgo; - end if; - end if; - end process gen_regs; - - -- generate PIOtip / DMAtip - gen_tip: process(clk, nReset) - begin - if (nReset = '0') then - PIOtip <= '0'; - DMAtip <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - PIOtip <= '0'; - DMAtip <= '0'; - else - PIOtip <= iPIOgo or (PIOtip and not PIOdone); - DMAtip <= iDMAgo or (DMAtip and not ((DMAdone and DMActrl_dir) or (DMAdone and not sDMARQ and not DMActrl_dir)) ); - end if; - end if; - end process gen_tip; - end block statemachine; - - -- - -- Hookup PIO controller - -- - PIO_control: atahost_pio_controller - generic map( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map( - clk => clk, - nReset => nReset, - rst => rst, - IDEctrl_IDEen => IDEctrl_IDEen, - IDEctrl_ppen => IDEctrl_ppen, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - cmdport_T1 => PIO_cmdport_T1, - cmdport_T2 => PIO_cmdport_T2, - cmdport_T4 => PIO_cmdport_T4, - cmdport_Teoc => PIO_cmdport_Teoc, - cmdport_IORDYen => PIO_cmdport_IORDYen, - dport0_T1 => PIO_dport0_T1, - dport0_T2 => PIO_dport0_T2, - dport0_T4 => PIO_dport0_T4, - dport0_Teoc => PIO_dport0_Teoc, - dport0_IORDYen => PIO_dport0_IORDYen, - dport1_T1 => PIO_dport1_T1, - dport1_T2 => PIO_dport1_T2, - dport1_T4 => PIO_dport1_T4, - dport1_Teoc => PIO_dport1_Teoc, - dport1_IORDYen => PIO_dport1_IORDYen, - sel => PIOsel, - ack => PIOack, - a => a, - we => we, - d => d(15 downto 0), - q => PIOq, - PIOreq => PIOreq, - PPFull => PIOpp_full, - go => PIOgo, - done => PIOdone, - PIOa => PIOa, - PIOd => PIOd, - SelDev => SelDev, - DDi => DDi, - DDoe => PIOoe, - DIOR => PIOdior, - DIOW => PIOdiow, - IORDY => sIORDY - ); - - -- - -- Hookup DMA access controller - -- - DMA_control: atahost_dma_actrl - generic map( - TWIDTH => TWIDTH, - DMA_mode0_Tm => DMA_mode0_Tm, - DMA_mode0_Td => DMA_mode0_Td, - DMA_mode0_Teoc => DMA_mode0_Teoc - ) - port map( - clk => clk, - nReset => nReset, - rst => rst, - IDEctrl_rst => IDEctrl_rst, - DMActrl_DMAen => DMActrl_DMAen, - DMActrl_dir => DMActrl_dir, - DMActrl_BeLeC0 => DMActrl_BeLeC0, - DMActrl_BeLeC1 => DMActrl_BeLeC1, - dev0_Td => DMA_dev0_Td, - dev0_Tm => DMA_dev0_Tm, - dev0_Teoc => DMA_dev0_Teoc, - dev1_Td => DMA_dev1_Td, - dev1_Tm => DMA_dev1_Tm, - dev1_Teoc => DMA_dev1_Teoc, - sel => DMAsel, - ack => DMAack, - we => we, - TxD => d, - TxFull => DMATxFull, - RxQ => DMAq, - RxFull => DMARxFull, - RxEmpty => DMARxEmpty, - DMA_req => DMA_req, - DMA_ack => DMA_ack, - SelDev => SelDev, - Go => DMAgo, - Done => DMAdone, - DDi => DDi, - DDo => DMAd, - DIOR => DMAdior, - DIOW => DMAdiow, - DMARQ => sDMARQ - ); -end architecture structural; Index: trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd (nonexistent) @@ -1,170 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- synchronous single clock fifo, uses LFSR pointers ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 12th, 2001. Initial release --- --- CVS Log --- --- $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_fifo is - generic( - DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range - -- 3, 7, 15, 31, 63 ... 65535 - SIZE : natural := 32 -- data width - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - rreq : in std_logic; -- read request - wreq : in std_logic; -- write request - - empty : out std_logic; -- fifo empty - full : out std_logic; -- fifo full - - D : in std_logic_vector(SIZE -1 downto 0); -- data input - Q : out std_logic_vector(SIZE -1 downto 0) -- data output - ); -end entity atahost_fifo; - -architecture structural of atahost_fifo is - -- - -- function declarations - -- - function bitsize(n : in natural) return natural is - variable tmp : unsigned(32 downto 1); - variable cnt : integer; - begin - tmp := conv_unsigned(n, 32); - cnt := 32; - - while ( (tmp(cnt) = '0') and (cnt > 0) ) loop - cnt := cnt -1; - end loop; - - return natural(cnt); - end function bitsize; - - -- - -- component declarations - -- - component atahost_lfsr is - generic( - TAPS : positive range 16 downto 3 :=8; - OFFSET : natural := 0 - ); - port( - clk : in std_logic; -- clock input - ena : in std_logic; -- count enable - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - Q : out unsigned(TAPS downto 1); -- count value - Qprev : out unsigned(TAPS downto 1) -- previous count value - ); - end component atahost_lfsr; - - constant ADEPTH : natural := bitsize(DEPTH); - - -- memory block - type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0); --- shared variable mem : memory; -- VHDL'93 PREFERED - signal mem : memory; -- VHDL'87 - - -- address pointers - signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0); - -begin - -- generate write address; hookup write_pointer counter - wr_ptr_lfsr: atahost_lfsr - generic map( - TAPS => ADEPTH, - OFFSET => 0 - ) - port map( - clk => clk, - ena => wreq, - nReset => nReset, - rst => rst, - Q => wr_ptr, - Qprev => dwr_ptr - ); - - -- generate read address; hookup read_pointer counter - rd_ptr_lfsr: atahost_lfsr - generic map( - TAPS => ADEPTH, - OFFSET => 0 - ) - port map( - clk => clk, - ena => rreq, - nReset => nReset, - rst => rst, - Q => rd_ptr, - Qprev => drd_ptr - ); - - -- generate full/empty signal - full <= '1' when (wr_ptr = drd_ptr) else '0'; - empty <= '1' when (rd_ptr = wr_ptr) else '0'; - - -- generate memory structure - gen_mem: process(clk) - begin - if (clk'event and clk = '1') then - if (wreq = '1') then - mem(conv_integer(wr_ptr)) <= D; - end if; - end if; - end process gen_mem; - Q <= mem(conv_integer(rd_ptr)); -end architecture structural; Index: trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd (nonexistent) @@ -1,144 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- Linear Feedback Shift Register ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 12th, 2001. Initial release --- --- CVS Log --- --- $Id: atahost_lfsr.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_lfsr is - generic( - TAPS : positive range 16 downto 3 :=8; - OFFSET : natural := 0 - ); - port( - clk : in std_logic; -- clock input - ena : in std_logic; -- count enable - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - Q : out unsigned(TAPS downto 1); -- count value - Qprev : out unsigned(TAPS downto 1) -- previous count value - ); -end entity atahost_lfsr; - -architecture dataflow of atahost_lfsr is - function lsb(tap : positive range 16 downto 3; Q : unsigned(TAPS downto 1) ) return std_logic is - begin - case tap is - when 3 => - return Q(3) xnor Q(2); - when 4 => - return Q(4) xnor Q(3); - when 5 => - return Q(5) xnor Q(3); - when 6 => - return Q(6) xnor Q(5); - when 7 => - return Q(7) xnor Q(6); - when 8 => - return (Q(8) xnor Q(6)) xnor (Q(5) xnor Q(4)); - when 9 => - return Q(9) xnor Q(5); - when 10 => - return Q(10) xnor Q(7); - when 11 => - return Q(11) xnor Q(9); - when 12 => - return (Q(12) xnor Q(6)) xnor (Q(4) xnor Q(1)); - when 13 => - return (Q(13) xnor Q(4)) xnor (Q(3) xnor Q(1)); - when 14 => - return (Q(14) xnor Q(5)) xnor (Q(3) xnor Q(1)); - when 15 => - return Q(15) xnor Q(14); - when 16 => - return (Q(16) xnor Q(15)) xnor (Q(13) xnor Q(4)); - end case; - end function lsb; - - signal msb : std_logic; - signal iQ : unsigned(TAPS downto 1); - -begin - -- - -- generate register - -- - gen_regs: process(clk, nReset) - variable tmpQ : unsigned(TAPS downto 1); - variable tmpmsb : std_logic; - begin - tmpQ := (others => '0'); - tmpmsb := '1'; - - for n in 1 to offset loop - tmpQ := (tmpQ(TAPS -1 downto 1) & lsb(TAPS, tmpQ) ); - tmpmsb := tmpQ(TAPS); - end loop; - - if (nReset = '0') then - iQ <= tmpQ; - msb <= tmpmsb; - elsif (clk'event and clk = '1') then - if (rst = '1') then - iQ <= tmpQ; - msb <= tmpmsb; - elsif (ena = '1') then - iQ <= (iQ(TAPS -1 downto 1) & lsb(TAPS, iq) ); - msb <= iQ(TAPS); - end if; - end if; - end process gen_regs; - - -- assign outputs - Q <= iQ; - Qprev <= (msb & iQ(TAPS downto 2)); -end architecture dataflow; - Index: trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd (nonexistent) @@ -1,465 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- DMA (single- and multiword) mode access controller ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 9th, 2001. Initial release --- --- CVS Log --- --- $Id: atahost_dma_actrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- --- - - --- Host accesses to DMA ports are 32bit wide. Accesses are made by 2 consecutive 16bit accesses to the ATA --- device's DataPort. The MSB HostData(31:16) is transfered first, then the LSB HostData(15:0) is transfered. - --- ---------------------------- --- DMA Access Controller -- ---------------------------- --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_dma_actrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst' - - sel : in std_logic; -- DMA buffers selected - we : in std_logic; -- write enable input - ack : out std_logic; -- acknowledge output - - dev0_Tm, - dev0_Td, - dev0_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 0 - dev1_Tm, - dev1_Td, - dev1_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 1 - - DMActrl_DMAen, - DMActrl_dir, - DMActrl_BeLeC0, - DMActrl_BeLeC1 : in std_logic; -- control register settings - - TxD : in std_logic_vector(31 downto 0); -- DMA transmit data - TxFull : buffer std_logic; -- DMA transmit buffer full - RxQ : out std_logic_vector(31 downto 0); -- DMA receive data - RxEmpty : buffer std_logic; -- DMA receive buffer empty - RxFull : out std_logic; -- DMA receive buffer full - DMA_req : out std_logic; -- DMA request to external DMA engine - DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine - - DMARQ : in std_logic; -- ATA devices request DMA transfer - - SelDev : in std_logic; -- Selected device - - Go : in std_logic; -- Start transfer sequence - Done : out std_logic; -- Transfer sequence done - - DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus - DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus - - DIOR, - DIOW : buffer std_logic - ); -end entity atahost_dma_actrl; - -architecture structural of atahost_dma_actrl is - -- - -- component declarations - -- - component atahost_dma_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 6; -- 70ns - DMA_mode0_Td : natural := 28; -- 290ns - DMA_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing register settings - Tm : in unsigned(TWIDTH -1 downto 0); -- Tm time (in clk-ticks) - Td : in unsigned(TWIDTH -1 downto 0); -- Td time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- DMA controller selected (strobe signal) - we : in std_logic; -- DMA direction '1' = write, '0' = read - - -- return signals - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic -- IOwrite signal, active high - ); - end component atahost_dma_tctrl; - - component atahost_reg_buf is - generic ( - WIDTH : natural := 8 - ); - port( - clk : in std_logic; - nReset : in std_logic; - rst : in std_logic; - - D : in std_logic_vector(WIDTH -1 downto 0); - Q : out std_logic_vector(WIDTH -1 downto 0); - rd : in std_logic; - wr : in std_logic; - valid : buffer std_logic - ); - end component atahost_reg_buf; - - component atahost_fifo is - generic( - DEPTH : natural := 32; -- fifo depth - SIZE : natural := 32 -- data width - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - rreq : in std_logic; -- read request - wreq : in std_logic; -- write request - - empty : out std_logic; -- fifo empty - full : out std_logic; -- fifo full - - D : in std_logic_vector(SIZE -1 downto 0); -- data input - Q : out std_logic_vector(SIZE -1 downto 0) -- data output - ); - end component atahost_fifo; - - signal Tdone, Tfw : std_logic; - signal RxWr, TxRd : std_logic; - signal dstrb, rd_dstrb, wr_dstrb : std_logic; - signal TxbufQ, RxbufD : std_logic_vector(31 downto 0); - -begin - - -- note: *fw = *first_word, *lw = *last_word - - - -- - -- generate DDi/DDo controls - -- - gen_DMA_sigs: block - signal writeDfw, writeDlw : std_logic_vector(15 downto 0); - signal readDfw, readDlw : std_logic_vector(15 downto 0); - signal BeLeC : std_logic; -- BigEndian <-> LittleEndian conversion - begin - -- generate byte_swap signal - BeLeC <= (not SelDev and DMActrl_BeLeC0) or (SelDev and DMActrl_BeLeC1); - - -- generate Tfw (Transfering first word) - gen_Tfw: process(clk, nReset) - begin - if (nReset = '0') then - Tfw <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - Tfw <= '0'; - else - Tfw <= go or (Tfw and not Tdone); - end if; - end if; - end process gen_Tfw; - - -- transmit data part - gen_writed_pipe:process(clk) - begin - if (clk'event and clk = '1') then - if (TxRd = '1') then -- reload registers - if (BeLeC = '1') then -- Do big<->little endian conversion - writeDfw(15 downto 8) <= TxbufQ( 7 downto 0); -- TxbufQ = data from transmit buffer - writeDfw( 7 downto 0) <= TxbufQ(15 downto 8); - writeDlw(15 downto 8) <= TxbufQ(23 downto 16); - writeDlw( 7 downto 0) <= TxbufQ(31 downto 24); - else -- don't do big<->little endian conversion - writeDfw <= TxbufQ(31 downto 16); - writeDlw <= TxbufQ(15 downto 0); - end if; - elsif (wr_dstrb = '1') then -- next word to transfer - writeDfw <= writeDlw; - end if; - end if; - end process gen_writed_pipe; - DDo <= writeDfw; -- assign DMA data out - - -- generate transmit register read request - gen_Tx_rreq: process(clk, nReset) - begin - if (nReset = '0') then - TxRd <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - TxRd <= '0'; - else - TxRd <= go and DMActrl_dir; - end if; - end if; - end process gen_Tx_rreq; - - -- receive - gen_readd_pipe:process(clk) - begin - if (clk'event and clk = '1') then - if (rd_dstrb = '1') then - - readDfw <= readDlw; -- shift previous read word to msb - if (BeLeC = '1') then -- swap bytes - readDlw(15 downto 8) <= DDi( 7 downto 0); - readDlw( 7 downto 0) <= DDi(15 downto 8); - else -- don't swap bytes - readDlw <= DDi; - end if; - end if; - end if; - end process gen_readd_pipe; - -- RxD = data to receive buffer - RxbufD <= (readDfw & readDlw) when (BeLeC = '0') else (readDlw & readDfw); - - -- generate receive register write request - gen_Rx_wreq: process(clk, nReset) - begin - if (nReset = '0') then - RxWr <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - RxWr <= '0'; - else - RxWr <= not Tfw and rd_dstrb; - end if; - end if; - end process gen_Rx_wreq; - end block gen_DMA_sigs; - - - -- - -- Hookup DMA read / write buffers - -- - gen_DMAbuf: block - signal DMArst : std_logic; - signal RxRd, TxWr : std_logic; - signal iRxEmpty : std_logic; - begin - -- generate DMA reset signal - DMArst <= rst or IDEctrl_rst; - - Txbuf: atahost_reg_buf - generic map (WIDTH => 32) - port map ( - clk => clk, - nReset => nReset, - rst => DMArst, - D => TxD, - Q => TxbufQ, - rd => TxRd, - wr => TxWr, - valid => TxFull - ); - - Rxbuf: atahost_fifo - generic map (DEPTH => 7, SIZE => 32) - port map ( - clk => clk, - nReset => nReset, - rst => DMArst, - D => RxbufD, - Q => RxQ, - rreq => RxRd, - wreq => RxWr, - empty => iRxEmpty, - full => RxFull - ); - - RxEmpty <= iRxEmpty; -- avoid 'cannot associate OUT port with BUFFER port' error - - -- - -- generate DMA buffer access signals - -- - RxRd <= sel and not we and not RxEmpty; - TxWr <= sel and we and not TxFull; - - ack <= RxRd or TxWr; -- DMA buffer access acknowledge - end block gen_DMAbuf; - - -- - -- generate request signal for external DMA engine - -- - gen_DMA_req: block - signal hgo : std_logic; - signal iDMA_req : std_logic; - signal request : std_logic; - begin - -- generate hold-go - gen_hgo : process(clk, nReset) - begin - if (nReset = '0') then - hgo <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - hgo <= '0'; - else - hgo <= go or (hgo and not (wr_dstrb and not Tfw) and DMActrl_dir); - end if; - end if; - end process gen_hgo; - - request <= (DMActrl_dir and DMARQ and not TxFull and not hgo) or not RxEmpty; - process(clk, nReset) - begin - if (nReset = '0') then - iDMA_req <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - iDMA_req <= '0'; - else - iDMA_req <= DMActrl_DMAen and not DMA_ack and (request or iDMA_req); --- DMA_req <= (DMActrl_DMAen and DMActrl_dir and DMARQ and not TxFull and not hgo) or not RxEmpty; - end if; - end if; - end process; - DMA_req <= iDMA_req; - end block gen_DMA_req; - - - -- - -- DMA timing controller - -- - DMA_timing_ctrl: block - signal Tm, Td, Teoc, Tdmack_ext : unsigned(TWIDTH -1 downto 0); - signal dTfw, igo : std_logic; - begin - -- - -- generate internal GO signal - -- - gen_igo : process(clk, nReset) - begin - if (nReset = '0') then - igo <= '0'; - dTfw <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - igo <= '0'; - dTfw <= '0'; - else - igo <= go or (not Tfw and dTfw); - dTfw <= Tfw; - end if; - end if; - end process gen_igo; - - -- - -- select timing settings for the addressed device - -- - sel_dev_t: process(clk) - begin - if (clk'event and clk = '1') then - if (SelDev = '1') then -- device1 selected - Tm <= dev1_Tm; - Td <= dev1_Td; - Teoc <= dev1_Teoc; - else -- device0 selected - Tm <= dev0_Tm; - Td <= dev0_Td; - Teoc <= dev0_Teoc; - end if; - end if; - end process sel_dev_t; - - -- - -- hookup timing controller - -- - DMA_timing_ctrl: atahost_dma_tctrl - generic map ( - TWIDTH => TWIDTH, - DMA_mode0_Tm => DMA_mode0_Tm, - DMA_mode0_Td => DMA_mode0_Td, - DMA_mode0_Teoc => DMA_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - Tm => Tm, - Td => Td, - Teoc => Teoc, - go => igo, - we => DMActrl_dir, - done => Tdone, - dstrb => dstrb, - DIOR => dior, - DIOW => diow - ); - - done <= Tdone and not Tfw; -- done transfering last word - rd_dstrb <= dstrb and not DMActrl_dir; -- read data strobe - wr_dstrb <= dstrb and DMActrl_dir; -- write data strobe - end block DMA_timing_ctrl; - -end architecture structural; - Index: trunk/rtl/vhdl/ocidec3/ud_cnt.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/ud_cnt.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/ud_cnt.vhd (nonexistent) @@ -1,102 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- Generic Up/Down counter (ripple carry architecture) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- --- CVS Log --- --- $Id: ud_cnt.vhd,v 1.1 2002-03-01 03:49:25 rherveille Exp $ --- --- $Date: 2002-03-01 03:49:25 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity ud_cnt is - generic( - SIZE : natural := 8; - RESD : natural := 0 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - ud : in std_logic := '0'; -- up / not down - nld : in std_logic := '1'; -- synchronous active low load - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0); -- current counter value - - rci : in std_logic := '1'; -- carry input - rco : out std_logic -- carry output - ); -end entity ud_cnt; - -architecture structural of ud_cnt is - signal Qi : unsigned(SIZE -1 downto 0); - signal val : unsigned(SIZE downto 0); -begin - val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); - - regs: process(clk, nReset) - begin - if (nReset = '0') then - Qi <= conv_unsigned(RESD, SIZE); - elsif (clk'event and clk = '1') then - if (rst = '1') then - Qi <= conv_unsigned(RESD, SIZE); - else - if (nld = '0') then - Qi <= D; - elsif (cnt_en = '1') then - Qi <= val(SIZE -1 downto 0); - end if; - end if; - end if; - end process regs; - - -- assign outputs - Q <= Qi; - rco <= val(SIZE); -end architecture structural; - Index: trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd (nonexistent) @@ -1,89 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- CVS Log --- --- $Id: atahost_reg_buf.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - - -library ieee; -use ieee.std_logic_1164.all; - -entity atahost_reg_buf is - generic ( - WIDTH : natural := 8 - ); - port( - clk : in std_logic; - nReset : in std_logic; - rst : in std_logic; - - D : in std_logic_vector(WIDTH -1 downto 0); - Q : out std_logic_vector(WIDTH -1 downto 0); - rd : in std_logic; - wr : in std_logic; - valid : buffer std_logic - ); -end entity atahost_reg_buf; - -architecture structural of atahost_reg_buf is -begin - process(clk, nReset) - begin - if (nReset = '0') then - Q <= (others => '0'); - valid <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - Q <= (others => '0'); - valid <= '0'; - else - if (wr = '1') then - Q <= D; - end if; - valid <= wr or (valid and not rd); - end if; - end if; - end process; -end architecture structural; Index: trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd (nonexistent) @@ -1,222 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- DMA (single- and multiword) mode timing statemachine ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 7th, 2001. Initial release --- --- CVS Log --- --- $Id: atahost_dma_tctrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - --- ---------------------------- --- DMA Timing Controller -- ---------------------------- --- - --- --- Timing DMA mode transfers ----------------------------------------------- --- T0: cycle time --- Td: DIOR-/DIOW- asserted pulse width --- Te: DIOR- data access --- Tf: DIOR- data hold --- Tg: DIOR-/DIOW- data setup --- Th: DIOW- data hold --- Ti: DMACK to DIOR-/DIOW- setup --- Tj: DIOR-/DIOW- to DMACK hold --- Tkr: DIOR- negated pulse width --- Tkw: DIOW- negated pulse width --- Tm: CS(1:0) valid to DIOR-/DIOW- --- Tn: CS(1:0) hold --- --- --- Transfer sequence ----------------------------------- --- 1) wait for Tm --- 2) assert DIOR-/DIOW- --- when write action present data (Timing spec. Tg always honored) --- output enable is controlled by DMA-direction and DMACK- --- 3) wait for Td --- 4) negate DIOR-/DIOW- --- when read action, latch data --- 5) wait for Teoc (T0 - Td - Tm) or Tkw, whichever is greater --- Th, Tj, Tk, Tn always honored --- 6) start new cycle --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_dma_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- DMA mode 0 settings (@100MHz clock) - DMA_mode0_Tm : natural := 4; -- 50ns - DMA_mode0_Td : natural := 21; -- 215ns - DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing register settings - Tm : in unsigned(TWIDTH -1 downto 0); -- Tm time (in clk-ticks) - Td : in unsigned(TWIDTH -1 downto 0); -- Td time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- DMA controller selected (strobe signal) - we : in std_logic; -- DMA direction '1' = write, '0' = read - - -- return signals - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic -- IOwrite signal, active high - ); -end entity atahost_dma_tctrl; - -architecture structural of atahost_dma_tctrl is - component ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); - end component ro_cnt; - - signal Tmdone, Tddone : std_logic; -begin - - -- 1) hookup Tm counter - tm_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => DMA_mode0_Tm - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => go, - D => Tm, - done => Tmdone - ); - - -- 2) set (and reset) DIOR-/DIOW- - T2proc: process(clk, nReset) - begin - if (nReset = '0') then - DIOR <= '0'; - DIOW <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - DIOR <= '0'; - DIOW <= '0'; - else - DIOR <= (not we and Tmdone) or (DIOR and not Tddone); - DIOW <= ( we and Tmdone) or (DIOW and not Tddone); - end if; - end if; - end process T2proc; - - -- 3) hookup Td counter - td_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => DMA_mode0_Td - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => Tmdone, - D => Td, - done => Tddone - ); - - -- generate data_strobe - gen_dstrb: process(clk) - begin - if (clk'event and clk = '1') then - dstrb <= Tddone; -- capture data at rising edge of DIOR- - end if; - end process gen_dstrb; - - -- 4) negate DIOR-/DIOW- when Tddone - -- 5) hookup end_of_cycle counter - eoc_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => DMA_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => Tddone, - D => Teoc, - done => done - ); -end architecture structural; Index: trunk/rtl/vhdl/ocidec3/revision_history.txt =================================================================== --- trunk/rtl/vhdl/ocidec3/revision_history.txt (revision 32) +++ trunk/rtl/vhdl/ocidec3/revision_history.txt (nonexistent) @@ -1,53 +0,0 @@ ------------------------------ -Revision: 1.0 -Date: march 22nd, 2001 -Author: Richard Herveille -- initial release ------------------------------ - ------------------------------ -Revision: 1.0a -Date: april 12th, 2001 -Author: Richard Herveille -- removed records.vhd -- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools -- fixed a minor bug where core didn't respond to IDEen bit. ------------------------------ - ------------------------------ -Revision: 1.1 -Date: june 18th, 2001 -Author: Richard Herveille -- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) ------------------------------ - ------------------------------ -Revision: 1.1a -Date: june 19th, 2001 -Author: Richard Herveille -- Simplified DAT_O output multiplexor ------------------------------ - ------------------------------ -Revision: 1.3 -Date: July 11th, 2001 -Author: Richard Herveille -- renamed 'ata.vhd' to 'atahost.vhd' -- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). ------------------------------ - ------------------------------ -Revision: 1.4 -Date: Februar 17th, 2002 -Author: Richard Herveille -- renamed all files to 'atahost_***.vhd' -- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' -- changed resD input to generic RESD in ud_cnt.vhd -- changed ID input to generic ID in ro_cnt.vhd -- changed core to reflect changes in ro_cnt.vhd -- removed references to 'count' library -- changed IO names -- added disclaimer -- added CVS log -- moved registers and wishbone signals into 'atahost_wb_slave.vhd' ------------------------------ Index: trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd (nonexistent) @@ -1,380 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- ATA/ATAPI-5 PIO controller with write PingPong ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 8th, 2001. Initial release --- --- CVS Log --- --- $Id: atahost_pio_controller.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_pio_controller is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock in - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - -- control / registers - IDEctrl_IDEen, - IDEctrl_ppen, - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - -- PIO registers - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - sel : in std_logic; -- PIO controller selected - ack : out std_logic; -- PIO controller acknowledge - a : in unsigned(3 downto 0); -- lower address bits - we : in std_logic; -- write enable input - d : in std_logic_vector(15 downto 0); - q : out std_logic_vector(15 downto 0); - - PIOreq : out std_logic; -- PIO transfer request - PPFull : out std_logic; -- PIO Write PingPong Full - go : in std_logic; -- start PIO transfer - done : buffer std_logic; -- done with PIO transfer - - PIOa : out unsigned(3 downto 0); -- PIO address, address lines towards ATA devices - PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices - - SelDev : buffer std_logic; -- Selected Device, Dev-bit in ATA Device/Head register - - DDi : in std_logic_vector(15 downto 0); - DDoe : buffer std_logic; - - DIOR : buffer std_logic; - DIOW : buffer std_logic; - IORDY : in std_logic - ); -end entity atahost_pio_controller; - -architecture structural of atahost_pio_controller is - -- - -- component declarations - -- - component atahost_pio_actrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - SelDev : in std_logic; -- Selected device - - go : in std_logic; -- Start transfer sequence - done : out std_logic; -- Transfer sequence done - dir : in std_logic; -- Transfer direction '1'=write, '0'=read - a : in unsigned(3 downto 0); -- PIO transfer address - q : out std_logic_vector(15 downto 0); -- Data read from ATA devices - - DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus - oe : buffer std_logic; -- DDbus output-enable signal - - DIOR, - DIOW : buffer std_logic; - IORDY : in std_logic - ); - end component atahost_pio_actrl; - - -- - -- signals - -- - - -- PIO pingpong signals - signal pp_d : std_logic_vector(15 downto 0); - signal pp_a : unsigned(3 downto 0); - signal pp_we : std_logic; - signal idone : std_logic; - -begin - -- - -- generate selected device - -- - gen_seldev: process(clk, pp_a) - variable Asel : std_logic; -- address selected - begin - Asel := not pp_a(3) and pp_a(2) and pp_a(1) and not pp_a(0); -- header/device register - - if (clk'event and clk = '1') then - if ( (idone = '1') and (Asel = '1') and (pp_we = '1') ) then - SelDev <= pp_d(4); - end if; - end if; - end process gen_seldev; - - -- - -- generate PIO write pingpong system - -- - gen_pingpong: block - signal ping_d, pong_d : std_logic_vector(15 downto 0); - signal ping_a, pong_a : unsigned(3 downto 0); - signal ping_we, pong_we : std_logic; - signal ping_valid, pong_valid : std_logic; - signal dping_valid, dpong_valid : std_logic; - signal wpp, rpp : std_logic; - - signal dsel, sel_strb : std_logic; - - signal iack : std_logic; - begin - -- generate PIO acknowledge - gen_ack: process(clk, ping_valid, dping_valid, pong_valid, dpong_valid, we) - variable ping_re, ping_fe, pong_re, pong_fe : std_logic; - begin - -- detect rising edge of ping_valid and pong_valid - ping_re := ping_valid and not dping_valid and we; - pong_re := pong_valid and not dpong_valid and we; - - -- detect falling edge of ping_valid and pong_valid - ping_fe := not ping_valid and dping_valid; - pong_fe := not pong_valid and dpong_valid; - - if (clk'event and clk = '1') then - if ((pp_we = '1') and (IDEctrl_ppen = '1')) then -- write sequence - if (wpp = '1') then - iack <= ping_re; - else - iack <= pong_re; - end if; - else -- read sequence - if (rpp = '1') then - iack <= ping_fe; - else - iack <= pong_fe; - end if; - end if; - end if; - end process gen_ack; - ack <= (iack or not IDEctrl_IDEen) and sel; -- acknowledge access when not enabled (discard access) - - -- generate select-strobe, hold sel_strb until pingpong system ready for new data - gen_sel_strb: process(clk, nReset) - begin - if (nReset = '0') then - dsel <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - dsel <= '0'; - else - dsel <= sel_strb or (dsel and sel); - end if; - end if; - end process gen_sel_strb; - sel_strb <= sel and not dsel and IDEctrl_IDEen and ((wpp and not ping_valid) or (not wpp and not pong_valid)); - - -- generate pingpong control - gen_pp : process(clk, nReset) - begin - if (nReset = '0') then - wpp <= '0'; - rpp <= '0'; - ping_valid <= '0'; - pong_valid <= '0'; - dping_valid <= '0'; - dpong_valid <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - wpp <= '0'; - rpp <= '0'; - ping_valid <= '0'; - pong_valid <= '0'; - dping_valid <= '0'; - dpong_valid <= '0'; - else - wpp <= (wpp xor (iack and we)) and IDEctrl_ppen; - rpp <= (rpp xor (idone and pp_we)) and IDEctrl_ppen; - ping_valid <= (( wpp and sel_strb) or ping_valid) and not ( rpp and idone); - pong_valid <= ((not wpp and sel_strb) or pong_valid) and not (not rpp and idone); - dping_valid <= ping_valid; - dpong_valid <= pong_valid; - end if; - end if; - end process gen_pp; - - -- generate pingpong full signal - PPFull <= (ping_valid and pong_valid) when (IDEctrl_ppen = '1') else pong_valid; - - -- fill ping/pong registers - fill_pp: process(clk) - begin - if (clk'event and clk = '1') then - if (sel = '1') then - if (wpp = '1') then - if (ping_valid = '0') then - ping_d <= d; - ping_a <= a; - ping_we <= we; - end if; - else - if (pong_valid = '0') then - pong_d <= d; - pong_a <= a; - pong_we <= we; - end if; - end if; - end if; - end if; - end process fill_pp; - - -- multiplex pingpong data to pp_d, pp_a, pp_we - pp_d <= ping_d when (rpp = '1') else pong_d; - pp_a <= ping_a when (rpp = '1') else pong_a; - pp_we <= ping_we when (rpp = '1') else pong_we; - - -- generate PIOreq - PIOreq <= (ping_valid and not idone) when (rpp = '1') else (pong_valid and not idone); - end block gen_pingpong; - - -- - -- Hookup PIO access controller - -- - PIO_access_control: atahost_pio_actrl - generic map( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map( - clk => clk, - nReset => nReset, - rst => rst, - IDEctrl_FATR0 => IDEctrl_FATR0, - IDEctrl_FATR1 => IDEctrl_FATR1, - cmdport_T1 => cmdport_T1, - cmdport_T2 => cmdport_T2, - cmdport_T4 => cmdport_T4, - cmdport_Teoc => cmdport_Teoc, - cmdport_IORDYen => cmdport_IORDYen, - dport0_T1 => dport0_T1, - dport0_T2 => dport0_T2, - dport0_T4 => dport0_T4, - dport0_Teoc => dport0_Teoc, - dport0_IORDYen => dport0_IORDYen, - dport1_T1 => dport1_T1, - dport1_T2 => dport1_T2, - dport1_T4 => dport1_T4, - dport1_Teoc => dport1_Teoc, - dport1_IORDYen => dport1_IORDYen, - SelDev => SelDev, - go => go, - done => idone, - dir => pp_we, - a => pp_a, - q => Q, - DDi => DDi, - oe => DDoe, - DIOR => dior, - DIOW => diow, - IORDY => IORDY - ); - - -- - -- assign outputs - -- - PIOa <= pp_a; - PIOd <= pp_d; - Done <= idone; -end architecture structural; - Index: trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd (nonexistent) @@ -1,255 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores IDE Controller ---- ----- PIO Access Controller (common for OCIDEC 2 and above) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws --- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 9th, 2001 --- rev.: 1.0a april 12th, 2001 Removed references to records.vhd --- --- --- CVS Log --- --- $Id: atahost_pio_actrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ - --- ---------------------------- --- PIO Access controller -- ---------------------------- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_pio_actrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - IDEctrl_FATR0, - IDEctrl_FATR1 : in std_logic; - - cmdport_T1, - cmdport_T2, - cmdport_T4, - cmdport_Teoc : in unsigned(7 downto 0); - cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing - - dport0_T1, - dport0_T2, - dport0_T4, - dport0_Teoc : in unsigned(7 downto 0); - dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 - - dport1_T1, - dport1_T2, - dport1_T4, - dport1_Teoc : in unsigned(7 downto 0); - dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 - - SelDev : in std_logic; -- Selected device - - go : in std_logic; -- Start transfer sequence - done : out std_logic; -- Transfer sequence done - dir : in std_logic; -- Transfer direction '1'=write, '0'=read - a : in unsigned(3 downto 0); -- PIO transfer address - q : out std_logic_vector(15 downto 0); -- Data read from ATA devices - - DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus - oe : buffer std_logic; -- DDbus output-enable signal - - DIOR, - DIOW : buffer std_logic; - IORDY : in std_logic - ); -end entity atahost_pio_actrl; - -architecture structural of atahost_pio_actrl is - -- - -- Component declarations - -- - component atahost_pio_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing/control register settings - IORDY_en : in std_logic; -- use IORDY (or not) - T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) - T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) - T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- PIO controller selected (strobe signal) - we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device - - -- return signals - oe : buffer std_logic; -- output enable signal - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe, latch data (during read) - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic; -- IOwrite signal, active high - IORDY : in std_logic -- IORDY signal - ); - end component atahost_pio_tctrl; - - signal dstrb : std_logic; - signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0); - signal IORDYen : std_logic; - -begin - -- - -------------------------- - -- PIO transfer control -- - -------------------------- - -- - -- capture ATA data for PIO access - gen_PIOq: process(clk) - begin - if (clk'event and clk = '1') then - if (dstrb = '1') then - q <= DDi; - end if; - end if; - end process gen_PIOq; - - -- - -- PIO timing controllers - -- - - -- select timing settings for the addressed port - sel_port_t: process(clk, a, SelDev, IDEctrl_FATR1, IDEctrl_FATR0, - cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen, - dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen, - dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen) - variable Asel : std_logic; -- address selected - variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0); - variable iIORDYen : std_logic; - begin - -- initially set timing registers to compatible timing - iT1 := cmdport_T1; - iT2 := cmdport_T2; - iT4 := cmdport_T4; - iTeoc := cmdport_Teoc; - iIORDYen := cmdport_IORDYen; - - -- detect data-port access - Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port - if (Asel = '1') then -- data port selected, 16bit transfers - if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ? - iT1 := dport1_T1; - iT2 := dport1_T2; - iT4 := dport1_T4; - iTeoc := dport1_Teoc; - iIORDYen := dport1_IORDYen; - elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ? - iT1 := dport0_T1; - iT2 := dport0_T2; - iT4 := dport0_T4; - iTeoc := dport0_Teoc; - iIORDYen := dport0_IORDYen; - end if; - end if; - - if (clk'event and clk = '1') then - T1 <= iT1; - T2 <= iT2; - T4 <= iT4; - Teoc <= iTeoc; - IORDYen <= iIORDYen; - end if; - end process sel_port_t; - - -- - -- hookup timing controller - -- - PIO_timing_controller: atahost_pio_tctrl - generic map ( - TWIDTH => TWIDTH, - PIO_mode0_T1 => PIO_mode0_T1, - PIO_mode0_T2 => PIO_mode0_T2, - PIO_mode0_T4 => PIO_mode0_T4, - PIO_mode0_Teoc => PIO_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - IORDY_en => IORDYen, - T1 => T1, - T2 => T2, - T4 => T4, - Teoc => Teoc, - go => go, - we => dir, - oe => oe, - done => done, - dstrb => dstrb, - DIOR => dior, - DIOW => diow, - IORDY => IORDY - ); -end architecture structural; - Index: trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd =================================================================== --- trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd (revision 32) +++ trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd (nonexistent) @@ -1,285 +0,0 @@ ---------------------------------------------------------------------- ----- ---- ----- OpenCores ATA/ATAPI-5 Host Controller ---- ----- PIO Timing Controller (common for all OCIDEC cores) ---- ----- ---- ----- Author: Richard Herveille ---- ----- richard@asics.ws ---- ----- www.asics.ws ---- ----- ---- ---------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2001, 2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------- - --- rev.: 1.0 march 7th, 2001. Initial release --- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation. --- --- --- CVS Log --- --- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ --- --- $Date: 2002-02-18 14:32:12 $ --- $Revision: 1.1 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: not supported by cvs2svn $ --- --- - --- ---------------------------- --- PIO Timing controller -- ---------------------------- --- - --- --- Timing PIO mode transfers ----------------------------------------------- --- T0: cycle time --- T1: address valid to DIOR-/DIOW- --- T2: DIOR-/DIOW- pulse width --- T2i: DIOR-/DIOW- recovery time --- T3: DIOW- data setup --- T4: DIOW- data hold --- T5: DIOR- data setup --- T6: DIOR- data hold --- T9: address hold from DIOR-/DIOW- negated --- Trd: Read data valid to IORDY asserted --- Ta: IORDY setup time --- Tb: IORDY pulse width --- --- Transfer sequence ----------------------------------- --- 1) set address (DA, CS0-, CS1-) --- 2) wait for T1 --- 3) assert DIOR-/DIOW- --- when write action present Data (timing spec. T3 always honored), enable output enable-signal --- 4) wait for T2 --- 5) check IORDY --- when not IORDY goto 5 --- when IORDY negate DIOW-/DIOR-, latch data (if read action) --- when write, hold data for T4, disable output-enable signal --- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest --- 7) start new cycle - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -entity atahost_pio_tctrl is - generic( - TWIDTH : natural := 8; -- counter width - - -- PIO mode 0 settings (@100MHz clock) - PIO_mode0_T1 : natural := 6; -- 70ns - PIO_mode0_T2 : natural := 28; -- 290ns - PIO_mode0_T4 : natural := 2; -- 30ns - PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic; -- asynchronous active low reset - rst : in std_logic; -- synchronous active high reset - - -- timing/control register settings - IORDY_en : in std_logic; -- use IORDY (or not) - T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) - T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) - T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) - Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time - - -- control signals - go : in std_logic; -- PIO controller selected (strobe signal) - we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device - - -- return signals - oe : buffer std_logic; -- output enable signal - done : out std_logic; -- finished cycle - dstrb : out std_logic; -- data strobe, latch data (during read) - - -- ATA signals - DIOR, -- IOread signal, active high - DIOW : buffer std_logic; -- IOwrite signal, active high - IORDY : in std_logic -- IORDY signal - ); -end entity atahost_pio_tctrl; - -architecture structural of atahost_pio_tctrl is - component ro_cnt is - generic( - SIZE : natural := 8; - UD : std_logic := '0'; -- default count down - ID : natural := 0 -- initial data after reset - ); - port( - clk : in std_logic; -- master clock - nReset : in std_logic := '1'; -- asynchronous active low reset - rst : in std_logic := '0'; -- synchronous active high reset - - cnt_en : in std_logic := '1'; -- count enable - go : in std_logic; -- load counter and start sequence - done : out std_logic; -- done counting - d : in unsigned(SIZE -1 downto 0); -- load counter value - q : out unsigned(SIZE -1 downto 0) -- current counter value - ); - end component ro_cnt; - - signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic; - signal busy, hold_go, igo, hT2done : std_logic; -begin - -- generate internal go strobe - -- strecht go until ready for new cycle - process(clk, nReset) - begin - if (nReset = '0') then - busy <= '0'; - hold_go <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - busy <= '0'; - hold_go <= '0'; - else - busy <= (igo or busy) and not Teoc_done; - hold_go <= (go or (hold_go and busy)) and not igo; - end if; - end if; - end process; - igo <= (go or hold_go) and not busy; - - -- 1) hookup T1 counter - t1_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T1 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => igo, - D => T1, - done => T1done - ); - - -- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device - T2proc: process(clk, nReset) - begin - if (nReset = '0') then - DIOR <= '0'; - DIOW <= '0'; - oe <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - DIOR <= '0'; - DIOW <= '0'; - oe <= '0'; - else - DIOR <= (not we and T1done) or (DIOR and not IORDY_done); - DIOW <= ( we and T1done) or (DIOW and not IORDY_done); - oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done - end if; - end if; - end process T2proc; - - -- 3) hookup T2 counter - t2_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T2 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => T1done, - D => T2, - done => T2done - ); - - -- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) - -- hold T2done - gen_hT2done: process(clk, nReset) - begin - if (nReset = '0') then - hT2done <= '0'; - elsif (clk'event and clk = '1') then - if (rst = '1') then - hT2done <= '0'; - else - hT2done <= (T2done or hT2done) and not IORDY_done; - end if; - end if; - end process gen_hT2done; - IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en); - - -- generate datastrobe, capture data at rising DIOR- edge - gen_dstrb: process(clk) - begin - if (clk'event and clk = '1') then - dstrb <= IORDY_done; - end if; - end process gen_dstrb; - - -- hookup data hold counter - dhold_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_T4 - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => IORDY_done, - D => T4, - done => T4done - ); - done <= T4done; -- placing done here provides the fastest return possible, - -- while still guaranteeing data and address hold-times - - -- 5) hookup end_of_cycle counter - eoc_cnt : ro_cnt - generic map ( - SIZE => TWIDTH, - UD => '0', - ID => PIO_mode0_Teoc - ) - port map ( - clk => clk, - nReset => nReset, - rst => rst, - go => IORDY_done, - D => Teoc, - done => Teoc_done - ); - -end architecture structural; Index: trunk/doc/src/ata_core.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/ata_core.doc =================================================================== --- trunk/doc/src/ata_core.doc (revision 32) +++ trunk/doc/src/ata_core.doc (nonexistent)

trunk/doc/src/ata_core.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/preliminary_ata_core.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/preliminary_ata_core.pdf =================================================================== --- trunk/doc/preliminary_ata_core.pdf (revision 32) +++ trunk/doc/preliminary_ata_core.pdf (nonexistent)

trunk/doc/preliminary_ata_core.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: ata/trunk/rtl/verilog/ocidec-1/atahost_controller.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/atahost_controller.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/atahost_controller.v (revision 33) @@ -0,0 +1,266 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OCIDEC-1 ATA/ATAPI-5 Host Controller //// +//// PIO Controller //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: atahost_controller.v,v 1.4 2002-05-19 06:04:22 rherveille Exp $ +// +// $Date: 2002-05-19 06:04:22 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// rev.: 1.0 june 28th, 2001. Initial Verilog release +// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section. +// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite. +// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). +// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments. +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/02/16 10:42:17 rherveille +// Added disclaimer +// Added CVS information +// Changed core for new internal counter libraries (synthesis fixes). +// +// +// + +`include "timescale.v" + +module atahost_controller (clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, + PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, + PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe, + RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ); + // + // parameter declarations + // + parameter TWIDTH = 8; // counter width + // PIO mode 0 timing settings @100MHz master clock + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + // + // inputs & outputs + // + input clk; //master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + + output irq; // interrupt request signal + reg irq; + + // control bits + input IDEctrl_rst; + input IDEctrl_IDEen; + + // PIO timing registers + input [7:0] PIO_cmdport_T1; + input [7:0] PIO_cmdport_T2; + input [7:0] PIO_cmdport_T4; + input [7:0] PIO_cmdport_Teoc; + input PIO_cmdport_IORDYen; + + // PIO control signals + input PIOreq; // PIO transfer request + output PIOack; // PIO transfer ended + input [ 3:0] PIOa; // PIO address + input [15:0] PIOd; // PIO data in + output [15:0] PIOq; // PIO data out + input PIOwe; // PIO direction bit. 1'b1==write, 1'b0==read + + reg [15:0] PIOq; + reg PIOack; + + // ATA signals + output RESETn; + input [15:0] DDi; + output [15:0] DDo; + output DDoe; + output [ 2:0] DA; + output CS0n; + output CS1n; + output DIORn; + output DIOWn; + input IORDY; + input INTRQ; + + reg RESETn; + reg [15:0] DDo; + reg DDoe; + reg [ 2:0] DA; + reg CS0n; + reg CS1n; + reg DIORn; + reg DIOWn; + + // + // Variable declarations + // + + reg dPIOreq; + reg PIOgo; // start PIO timing controller + wire PIOdone; // PIO timing controller done + + // PIO signals + wire PIOdior, PIOdiow; + wire PIOoe; + + // Timing settings + wire dstrb; + wire [TWIDTH-1:0] T1, T2, T4, Teoc; + wire IORDYen; + + // synchronized ATA inputs + reg sIORDY; + + // + // Module body + // + + + // synchronize incoming signals + reg cIORDY; // capture IORDY + reg cINTRQ; // capture INTRQ + + always@(posedge clk) + begin : synch_incoming + cIORDY <= #1 IORDY; + cINTRQ <= #1 INTRQ; + + sIORDY <= #1 cIORDY; + irq <= #1 cINTRQ; + end + + // generate ATA signals + always@(posedge clk or negedge nReset) + if (~nReset) + begin + RESETn <= #1 1'b0; + DIORn <= #1 1'b1; + DIOWn <= #1 1'b1; + DA <= #1 0; + CS0n <= #1 1'b1; + CS1n <= #1 1'b1; + DDo <= #1 0; + DDoe <= #1 1'b0; + end + else if (rst) + begin + RESETn <= #1 1'b0; + DIORn <= #1 1'b1; + DIOWn <= #1 1'b1; + DA <= #1 0; + CS0n <= #1 1'b1; + CS1n <= #1 1'b1; + DDo <= #1 0; + DDoe <= #1 1'b0; + end + else + begin + RESETn <= #1 !IDEctrl_rst; + DA <= #1 PIOa[2:0]; + CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0' + CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1' + + DDo <= #1 PIOd; + DDoe <= #1 PIOoe; + DIORn <= #1 !PIOdior; + DIOWn <= #1 !PIOdiow; + end + + + // + ////////////////////////// + // PIO transfer control // + ////////////////////////// + // + // capture ATA data for PIO access + always@(posedge clk) + if (dstrb) + PIOq <= #1 DDi; + + // generate PIOgo signal + always @(posedge clk or negedge nReset) + if (~nReset) + begin + dPIOreq <= #1 1'b0; + PIOgo <= #1 1'b0; + end + else if (rst) + begin + dPIOreq <= #1 1'b0; + PIOgo <= #1 1'b0; + end + else + begin + dPIOreq <= #1 PIOreq & !PIOack; + PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen; + end + + // set Timing signals + assign T1 = PIO_cmdport_T1; + assign T2 = PIO_cmdport_T2; + assign T4 = PIO_cmdport_T4; + assign Teoc = PIO_cmdport_Teoc; + assign IORDYen = PIO_cmdport_IORDYen; + + // hookup timing controller + atahost_pio_tctrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) + PIO_timing_controller ( + .clk(clk), + .nReset(nReset), + .rst(rst), + .IORDY_en(IORDYen), + .T1(T1), + .T2(T2), + .T4(T4), + .Teoc(Teoc), + .go(PIOgo), + .we(PIOwe), + .oe(PIOoe), + .done(PIOdone), + .dstrb(dstrb), + .DIOR(PIOdior), + .DIOW(PIOdiow), + .IORDY(sIORDY) + ); + + always@(posedge clk) + PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) + +endmodule Index: ata/trunk/rtl/verilog/ocidec-1/revision_history.txt =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/revision_history.txt (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/revision_history.txt (revision 33) @@ -0,0 +1,93 @@ +----------------------------- +Revision: 1.0 +Date: June 28th, 2001 +Author: Richard Herveille +- Initial Verilog release (beta) +----------------------------- + +----------------------------- +Revision: 1.1 +Date: June 18th, 2001 +Author: Richard Herveille +- Fixed some incomplete port lists and some Verilog related issues. + Design now completely compiles +----------------------------- + +----------------------------- +Revision: 1.1a +Date: July 3rd, 2001 +Author: Richard Herveille +- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues. +----------------------------- + +----------------------------- +Revision: 1.2 +Date: July 9th, 2001 +Author: Richard Herveille +- added 'timescale to all files +- fixed error where control registers latched data on all rising clock edges, instead of + when addressed. +----------------------------- + +----------------------------- +Revision: 1.3 +Date: July 11th, 2001 +Author: Richard Herveille +- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration. +- changed 'ata.v' into 'atahost.v' +- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous +- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). +----------------------------- + +----------------------------- +Revision: 1.4 +Date: July 26th, 2001 +Author: Richard Herveille +- Fixed some blocking versus non-blocking statement issues. +----------------------------- + +----------------------------- +Revision: 1.5 +Date: August 15th, 2001. +Author: Richard Herveille +- Changed filenames and top-level port names to be conform new OpenCores conventions +----------------------------- + +----------------------------- +Revision: 1.6 +Date: September 12th, 2001. +Author: Richard Herveille +- Made asynchronous input programmable (using atahost_define.v) +----------------------------- + +----------------------------- +Revision: 1.7 +Date: October 16th, 2001. +Author: Richard Herveille +- Changed programmable asynchronous level from define to parameter +----------------------------- + +----------------------------- +Revision: 1.8 +Date: Februar 16th, 2002. +Author: Richard Herveille +- Added disclaimer +- Added CVS information +- Changed core for new counter libraries +- Updated testbench +----------------------------- + +----------------------------- +Revision: 1.9 +Date: Februar 17th, 2002. +Author: Richard Herveille +- moved wishbone interface into 'atahost_wb_slave.v' +----------------------------- + +----------------------------- +Revision: 1.10 +Date: May 19th, 2002. +Author: Richard Herveille +- Fixed a potential bug that forced the core into an unknown state + when an asynchronous reset was given without a running clock +----------------------------- Index: ata/trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v (revision 33) @@ -0,0 +1,265 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores ATA/ATAPI-5 Host Controller //// +//// PIO Timing Controller (common for all OCIDEC cores) //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: atahost_pio_tctrl.v,v 1.3 2002-02-18 14:25:43 rherveille Exp $ +// +// $Date: 2002-02-18 14:25:43 $ +// $Revision: 1.3 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// Rev. 1.0 June 27th, 2001. Initial Verilog release +// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues. +// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation. +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/02/16 10:42:17 rherveille +// Added disclaimer +// Added CVS information +// Changed core for new internal counter libraries (synthesis fixes). +// +// + + +// +// Timing PIO mode transfers +//-------------------------------------------- +// T0: cycle time +// T1: address valid to DIOR-/DIOW- +// T2: DIOR-/DIOW- pulse width +// T2i: DIOR-/DIOW- recovery time +// T3: DIOW- data setup +// T4: DIOW- data hold +// T5: DIOR- data setup +// T6: DIOR- data hold +// T9: address hold from DIOR-/DIOW- negated +// Trd: Read data valid to IORDY asserted +// Ta: IORDY setup time +// Tb: IORDY pulse width +// +// Transfer sequence +//-------------------------------- +// 1) set address (DA, CS0-, CS1-) +// 2) wait for T1 +// 3) assert DIOR-/DIOW- +// when write action present Data (timing spec. T3 always honored), enable output enable-signal +// 4) wait for T2 +// 5) check IORDY +// when not IORDY goto 5 +// when IORDY negate DIOW-/DIOR-, latch data (if read action) +// when write, hold data for T4, disable output-enable signal +// 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest +// 7) start new cycle + +`include "timescale.v" + +module atahost_pio_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY); + // parameter declarations + parameter TWIDTH = 8; + parameter PIO_MODE0_T1 = 6; // 70ns + parameter PIO_MODE0_T2 = 28; // 290ns + parameter PIO_MODE0_T4 = 2; // 30ns + parameter PIO_MODE0_Teoc = 23; // 240ns + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + + // timing & control register settings + input IORDY_en; // use IORDY (or not) + input [TWIDTH-1:0] T1; // T1 time (in clk-ticks) + input [TWIDTH-1:0] T2; // T1 time (in clk-ticks) + input [TWIDTH-1:0] T4; // T1 time (in clk-ticks) + input [TWIDTH-1:0] Teoc; // T1 time (in clk-ticks) + + // control signals + input go; // PIO controller selected (strobe signal) + input we; // write enable signal. 1'b0 == read, 1'b1 == write + + // return signals + output oe; // output enable signal + reg oe; + output done; // finished cycle + output dstrb; // data strobe, latch data (during read) + reg dstrb; + + // ata signals + output DIOR; // IOread signal, active high + reg DIOR; + output DIOW; // IOwrite signal, active high + reg DIOW; + input IORDY; // IOrDY signal + + + // + // constant declarations + // + // PIO mode 0 settings (@100MHz clock) + wire [TWIDTH-1:0] T1_m0 = PIO_MODE0_T1; + wire [TWIDTH-1:0] T2_m0 = PIO_MODE0_T2; + wire [TWIDTH-1:0] T4_m0 = PIO_MODE0_T4; + wire [TWIDTH-1:0] Teoc_m0 = PIO_MODE0_Teoc; + + // + // variable declaration + // + reg busy, hold_go; + wire igo; + wire T1done, T2done, T4done, Teoc_done, IORDY_done; + reg hT2done; + + // + // module body + // + + // generate internal go strobe + // strecht go until ready for new cycle + always@(posedge clk or negedge nReset) + if (~nReset) + begin + busy <= #1 1'b0; + hold_go <= #1 1'b0; + end + else if (rst) + begin + busy <= #1 1'b0; + hold_go <= #1 1'b0; + end + else + begin + busy <= #1 (igo | busy) & !Teoc_done; + hold_go <= #1 (go | (hold_go & busy)) & !igo; + end + + assign igo = (go | hold_go) & !busy; + + // 1) hookup T1 counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1) + t1_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(igo), + .d(T1), + .q(), + .done(T1done) + ); + + // 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device + always@(posedge clk or negedge nReset) + if (~nReset) + begin + DIOR <= #1 1'b0; + DIOW <= #1 1'b0; + oe <= #1 1'b0; + end + else if (rst) + begin + DIOR <= #1 1'b0; + DIOW <= #1 1'b0; + oe <= #1 1'b0; + end + else + begin + DIOR <= #1 (!we & T1done) | (DIOR & !IORDY_done); + DIOW <= #1 ( we & T1done) | (DIOW & !IORDY_done); + oe <= #1 ( (we & igo) | oe) & !T4done; // negate oe when t4-done + end + + // 3) hookup T2 counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2) + t2_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(T1done), + .d(T2), + .q(), + .done(T2done) + ); + + // 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) + // hold T2done + always@(posedge clk or negedge nReset) + if (~nReset) + hT2done <= #1 1'b0; + else if (rst) + hT2done <= #1 1'b0; + else + hT2done <= #1 (T2done | hT2done) & !IORDY_done; + + assign IORDY_done = (T2done | hT2done) & (IORDY | !IORDY_en); + + // generate datastrobe, capture data at rising DIOR- edge + always@(posedge clk) + dstrb <= #1 IORDY_done; + + // hookup data hold counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4) + dhold_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(IORDY_done), + .d(T4), + .q(), + .done(T4done) + ); + + assign done = T4done; // placing done here provides the fastest return possible, + // while still guaranteeing data and address hold-times + + // 5) hookup end_of_cycle counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc) + eoc_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(IORDY_done), + .d(Teoc), + .q(), + .done(Teoc_done) + ); + +endmodule Index: ata/trunk/rtl/verilog/ocidec-1/atahost_top.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/atahost_top.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/atahost_top.v (revision 33) @@ -0,0 +1,292 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OCIDEC-1 ATA/ATAPI-5 Controller //// +//// Top Level //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: atahost_top.v,v 1.7 2002-02-18 14:25:43 rherveille Exp $ +// +// $Date: 2002-02-18 14:25:43 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// rev.: 1.0 June 29th, 2001. Initial Verilog release +// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list. +// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected. +// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration. +// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments. +// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention. +// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2002/02/16 10:42:17 rherveille +// Added disclaimer +// Added CVS information +// Changed core for new internal counter libraries (synthesis fixes). +// +// +// +// + +///////////////////////////////////////////////////////////// +// +// DeviceType: OCIDEC-1: OpenCores IDE Controller type1 +// Features: PIO Compatible Timing +// DeviceID: 0x01 +// RevNo : 0x00 +// + +// +// Host signals: +// Reset +// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. +// DIOW- write strobe. The rising edge latches data from DD into the device. +// DA(2:0) 3bit binary coded adress +// CS0- select command block registers +// CS1- select control block registers + +`include "timescale.v" + +module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o, + resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o, + cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i); + // + // Parameter declarations + // + parameter ARST_LVL = 1'b0; // asynchronous reset level + + parameter TWIDTH = 8; // counter width + // PIO mode 0 settings (@100MHz clock) + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + // + // inputs & outputs + // + + // WISHBONE SYSCON signals + input wb_clk_i; // master clock in + input arst_i; // asynchronous reset + input wb_rst_i; // synchronous reset + + // WISHBONE SLAVE signals + input wb_cyc_i; // valid bus cycle input + input wb_stb_i; // strobe/core select input + output wb_ack_o; // strobe acknowledge output + output wb_err_o; // error output + input [6:2] wb_adr_i; // A6 = '1' ATA devices selected + // A5 = '1' CS1- asserted, '0' CS0- asserted + // A4..A2 ATA address lines + // A6 = '0' ATA controller selected + input [31:0] wb_dat_i; // Databus in + output [31:0] wb_dat_o; // Databus out + input [ 3:0] wb_sel_i; // Byte select signals + input wb_we_i; // Write enable input + output wb_inta_o; // interrupt request signal + + // ATA signals + output resetn_pad_o; + input [15:0] dd_pad_i; + output [15:0] dd_pad_o; + output dd_padoe_o; + output [ 2:0] da_pad_o; + output cs0n_pad_o; + output cs1n_pad_o; + + output diorn_pad_o; + output diown_pad_o; + input iordy_pad_i; + input intrq_pad_i; + + // + // constant declarations + // + parameter [3:0] DeviceId = 4'h1; + parameter [3:0] RevisionNo = 4'h0; + + // + // Variable declarations + // + + // registers + wire IDEctrl_IDEen, IDEctrl_rst; + wire [ 7:0] PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc; + wire PIO_cmdport_IORDYen; + + wire PIOack; + wire [15:0] PIOq; + + wire irq; // ATA bus IRQ signal + + + ///////////////// + // Module body // + ///////////////// + + // generate asynchronous reset level + // arst_signal is either a wire or a NOT-gate + wire arst_signal = arst_i ^ ARST_LVL; + + // + // hookup wishbone slave + // + atahost_wb_slave #(DeviceId, RevisionNo, PIO_mode0_T1, + PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc, 0, 0, 0) + u0 ( + // WISHBONE SYSCON signals + .clk_i(wb_clk_i), + .arst_i(arst_signal), + .rst_i(wb_rst_i), + + // WISHBONE SLAVE signals + .cyc_i(wb_cyc_i), + .stb_i(wb_stb_i), + .ack_o(wb_ack_o), + .rty_o(), + .err_o(wb_err_o), + .adr_i(wb_adr_i), + .dat_i(wb_dat_i), + .dat_o(wb_dat_o), + .sel_i(wb_sel_i), + .we_i(wb_we_i), + .inta_o(wb_inta_o), + + // PIO control inputs + .PIOsel(PIOsel), + // PIOtip is only asserted during a PIO transfer (No shit! ;) + // Since it is impossible to read the status register and access the PIO registers at the same time + // this bit is useless (besides using-up resources) + .PIOtip(1'b0), + .PIOack(PIOack), + .PIOq(PIOq), + .PIOpp_full(1'b0), // OCIDEC-1 does not support PIO-write pingpong, negate signal + .irq(irq), + + // DMA control inputs (negate all of them, OCIDEC-1 does not support DMA) + .DMAsel(), + .DMAtip(1'b0), + .DMAack(1'b0), + .DMARxEmpty(1'b0), + .DMATxFull(1'b0), + .DMA_dmarq(1'b0), + .DMAq(32'h0), + + // outputs + // control register outputs + .IDEctrl_rst(IDEctrl_rst), + .IDEctrl_IDEen(IDEctrl_IDEen), + .IDEctrl_FATR0(), + .IDEctrl_FATR1(), + .IDEctrl_ppen(), + + .DMActrl_DMAen(), + .DMActrl_dir(), + .DMActrl_BeLeC0(), + .DMActrl_BeLeC1(), + + // CMD port timing registers + .PIO_cmdport_T1(PIO_cmdport_T1), + .PIO_cmdport_T2(PIO_cmdport_T2), + .PIO_cmdport_T4(PIO_cmdport_T4), + .PIO_cmdport_Teoc(PIO_cmdport_Teoc), + .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen), + + // data-port0 timing registers + .PIO_dport0_T1(), + .PIO_dport0_T2(), + .PIO_dport0_T4(), + .PIO_dport0_Teoc(), + .PIO_dport0_IORDYen(), + + // data-port1 timing registers + .PIO_dport1_T1(), + .PIO_dport1_T2(), + .PIO_dport1_T4(), + .PIO_dport1_Teoc(), + .PIO_dport1_IORDYen(), + + // DMA device0 timing registers + .DMA_dev0_Tm(), + .DMA_dev0_Td(), + .DMA_dev0_Teoc(), + + // DMA device1 timing registers + .DMA_dev1_Tm(), + .DMA_dev1_Td(), + .DMA_dev1_Teoc() + ); + + + // + // hookup controller section + // + atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) + u1 ( + .clk(wb_clk_i), + .nReset(arst_signal), + .rst(wb_rst_i), + .irq(irq), + .IDEctrl_rst(IDEctrl_rst), + .IDEctrl_IDEen(IDEctrl_IDEen), + .PIO_cmdport_T1(PIO_cmdport_T1), + .PIO_cmdport_T2(PIO_cmdport_T2), + .PIO_cmdport_T4(PIO_cmdport_T4), + .PIO_cmdport_Teoc(PIO_cmdport_Teoc), + .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen), + .PIOreq(PIOsel), + .PIOack(PIOack), + .PIOa(wb_adr_i[5:2]), + .PIOd(wb_dat_i[15:0]), + .PIOq(PIOq), + .PIOwe(wb_we_i), + .RESETn(resetn_pad_o), + .DDi(dd_pad_i), + .DDo(dd_pad_o), + .DDoe(dd_padoe_o), + .DA(da_pad_o), + .CS0n(cs0n_pad_o), + .CS1n(cs1n_pad_o), + .DIORn(diorn_pad_o), + .DIOWn(diown_pad_o), + .IORDY(iordy_pad_i), + .INTRQ(intrq_pad_i) + ); + +endmodule Index: ata/trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v (revision 33) @@ -0,0 +1,482 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OCIDEC-1 ATA/ATAPI-5 Controller //// +//// Wishbone Slave interface (common for all OCIDEC cores) //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// +// CVS Log +// +// $Id: atahost_wb_slave.v,v 1.1 2002-02-18 14:25:43 rherveille Exp $ +// +// $Date: 2002-02-18 14:25:43 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module atahost_wb_slave ( + clk_i, arst_i, rst_i, cyc_i, stb_i, ack_o, rty_o, err_o, adr_i, dat_i, dat_o, sel_i, we_i, inta_o, + PIOsel, PIOtip, PIOack, PIOq, PIOpp_full, irq, + DMAsel, DMAtip, DMAack, DMARxEmpty, DMATxFull, DMA_dmarq, DMAq, + IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR1, IDEctrl_FATR0, IDEctrl_ppen, + DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1, + PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, + PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc, PIO_dport0_IORDYen, + PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc, PIO_dport1_IORDYen, + DMA_dev0_Tm, DMA_dev0_Td, DMA_dev0_Teoc, DMA_dev1_Tm, DMA_dev1_Td, DMA_dev1_Teoc + ); + + // + // Parameters + // + parameter DeviceId = 4'h0; + parameter RevisionNo = 4'h0; + + // PIO mode 0 settings (@100MHz clock) + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + // Multiword DMA mode 0 settings (@100MHz clock) + parameter DMA_mode0_Tm = 6; // 50ns + parameter DMA_mode0_Td = 21; // 215ns + parameter DMA_mode0_Teoc = 21; // 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + + // + // inputs & outputs + // + + // WISHBONE SYSCON signals + input clk_i; // master clock in + input arst_i; // asynchronous active low reset + input rst_i; // synchronous active high reset + + // WISHBONE SLAVE signals + input cyc_i; // valid bus cycle input + input stb_i; // strobe/core select input + output ack_o; // strobe acknowledge output + output rty_o; // retry output + output err_o; // error output + input [6:2] adr_i; // A6 = '1' ATA devices selected + // A5 = '1' CS1- asserted, '0' CS0- asserted + // A4..A2 ATA address lines + // A6 = '0' ATA controller selected + input [31:0] dat_i; // Databus in + output [31:0] dat_o; // Databus out + input [ 3:0] sel_i; // Byte select signals + input we_i; // Write enable input + output inta_o; // interrupt request signal IDE0 + + // PIO control input + output PIOsel; + input PIOtip; // PIO transfer in progress + input PIOack; // PIO acknowledge signal + input [15:0] PIOq; // PIO data input + input PIOpp_full; // PIO write-ping-pong buffers full + input irq; // interrupt signal input + + // DMA control inputs + output DMAsel; + input DMAtip; // DMA transfer in progress + input DMAack; // DMA transfer acknowledge + input DMARxEmpty; // DMA receive buffer empty + input DMATxFull; // DMA transmit buffer full + input DMA_dmarq; // wishbone DMA request + input [31:0] DMAq; + + // outputs + // control register outputs + output IDEctrl_rst; + output IDEctrl_IDEen; + output IDEctrl_FATR1; + output IDEctrl_FATR0; + output IDEctrl_ppen; + output DMActrl_DMAen; + output DMActrl_dir; + output DMActrl_BeLeC0; + output DMActrl_BeLeC1; + + // CMD port timing registers + output [7:0] PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc; + output PIO_cmdport_IORDYen; + + reg [7:0] PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc; + + // data-port0 timing registers + output [7:0] PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc; + output PIO_dport0_IORDYen; + + reg [7:0] PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc; + + // data-port1 timing registers + output [7:0] PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc; + output PIO_dport1_IORDYen; + + reg [7:0] PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc; + + // DMA device0 timing registers + output [7:0] DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc; + + reg [7:0] DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc; + + // DMA device1 timing registers + output [7:0] DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc; + + reg [7:0] DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc; + + + // + // constants + // + + // addresses + `define ATA_DEV_ADR adr_i[6] + `define ATA_ADR adr_i[5:2] + + `define ATA_CTRL_REG 4'b0000 + `define ATA_STAT_REG 4'b0001 + `define ATA_PIO_CMD 4'b0010 + `define ATA_PIO_DP0 4'b0011 + `define ATA_PIO_DP1 4'b0100 + `define ATA_DMA_DEV0 4'b0101 + `define ATA_DMA_DEV1 4'b0110 + // reserved // + `define ATA_DMA_PORT 4'b1111 + + + // + // signals + // + + // registers + reg [31:0] CtrlReg; // control register + wire [31:0] StatReg; // status register + + // store ping-pong-full signal + reg store_pp_full; + + + // + // generate bus cycle / address decoder + // + wire w_acc = &sel_i[1:0]; // word access + wire dw_acc = &sel_i; // double word access + + // bus error + wire berr = `ATA_DEV_ADR ? !w_acc : !dw_acc; + + // PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong-full + wire PIOsel = cyc_i & stb_i & `ATA_DEV_ADR & w_acc & !(DMAtip | store_pp_full); + + // CON accesses only 32bit wide + wire CONsel = cyc_i & stb_i & !(`ATA_DEV_ADR) & dw_acc; + wire DMAsel = CONsel & (`ATA_ADR == `ATA_DMA_PORT); + + // bus retry (OCIDEC-3 and above) + // store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle + always@(posedge clk_i) + if (!PIOsel) + store_pp_full <= #1 PIOpp_full; + + wire brty = (`ATA_DEV_ADR & w_acc) & (DMAtip | store_pp_full); + + // + // generate registers + // + + // generate register select signals + wire sel_ctrl = CONsel & we_i & (`ATA_ADR == `ATA_CTRL_REG); + wire sel_stat = CONsel & we_i & (`ATA_ADR == `ATA_STAT_REG); + wire sel_PIO_cmdport = CONsel & we_i & (`ATA_ADR == `ATA_PIO_CMD); + wire sel_PIO_dport0 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP0); + wire sel_PIO_dport1 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP1); + wire sel_DMA_dev0 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV0); + wire sel_DMA_dev1 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV1); + // reserved 0x1c-0x38 + // reserved 0x3c : DMA-port + + + // generate control register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + CtrlReg[31:1] <= #1 0; + CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) + end + else if (rst_i) + begin + CtrlReg[31:1] <= #1 0; + CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) + end + else if (sel_ctrl) + CtrlReg <= #1 dat_i; + + // assign bits + assign DMActrl_DMAen = CtrlReg[15]; + assign DMActrl_dir = CtrlReg[13]; + assign DMActrl_BeLeC1 = CtrlReg[9]; + assign DMActrl_BeLeC0 = CtrlReg[8]; + assign IDEctrl_IDEen = CtrlReg[7]; + assign IDEctrl_FATR1 = CtrlReg[6]; + assign IDEctrl_FATR0 = CtrlReg[5]; + assign IDEctrl_ppen = CtrlReg[4]; + assign PIO_dport1_IORDYen = CtrlReg[3]; + assign PIO_dport0_IORDYen = CtrlReg[2]; + assign PIO_cmdport_IORDYen = CtrlReg[1]; + assign IDEctrl_rst = CtrlReg[0]; + + + // generate status register clearable bits + reg dirq, int; + + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + int <= #1 1'b0; + dirq <= #1 1'b0; + end + else if (rst_i) + begin + int <= #1 1'b0; + dirq <= #1 1'b0; + end + else + begin + int <= #1 (int | (irq & !dirq)) & !(sel_stat & !dat_i[0]); + dirq <= #1 irq; + end + + // assign status bits + assign StatReg[31:28] = DeviceId; // set Device ID + assign StatReg[27:24] = RevisionNo; // set revision number + assign StatReg[23:16] = 0; // reserved + assign StatReg[15] = DMAtip; + assign StatReg[14:11] = 0; + assign StatReg[10] = DMARxEmpty; + assign StatReg[9] = DMATxFull; + assign StatReg[8] = DMA_dmarq; + assign StatReg[7] = PIOtip; + assign StatReg[6] = PIOpp_full; + assign StatReg[5:1] = 0; // reserved + assign StatReg[0] = int; + + + // generate PIO compatible / command-port timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + PIO_cmdport_T1 <= #1 PIO_mode0_T1; + PIO_cmdport_T2 <= #1 PIO_mode0_T2; + PIO_cmdport_T4 <= #1 PIO_mode0_T4; + PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; + end + else if (rst_i) + begin + PIO_cmdport_T1 <= #1 PIO_mode0_T1; + PIO_cmdport_T2 <= #1 PIO_mode0_T2; + PIO_cmdport_T4 <= #1 PIO_mode0_T4; + PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; + end + else if(sel_PIO_cmdport) + begin + PIO_cmdport_T1 <= #1 dat_i[ 7: 0]; + PIO_cmdport_T2 <= #1 dat_i[15: 8]; + PIO_cmdport_T4 <= #1 dat_i[23:16]; + PIO_cmdport_Teoc <= #1 dat_i[31:24]; + end + + // generate PIO device0 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + PIO_dport0_T1 <= #1 PIO_mode0_T1; + PIO_dport0_T2 <= #1 PIO_mode0_T2; + PIO_dport0_T4 <= #1 PIO_mode0_T4; + PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; + end + else if (rst_i) + begin + PIO_dport0_T1 <= #1 PIO_mode0_T1; + PIO_dport0_T2 <= #1 PIO_mode0_T2; + PIO_dport0_T4 <= #1 PIO_mode0_T4; + PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; + end + else if(sel_PIO_dport0) + begin + PIO_dport0_T1 <= #1 dat_i[ 7: 0]; + PIO_dport0_T2 <= #1 dat_i[15: 8]; + PIO_dport0_T4 <= #1 dat_i[23:16]; + PIO_dport0_Teoc <= #1 dat_i[31:24]; + end + + // generate PIO device1 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + PIO_dport1_T1 <= #1 PIO_mode0_T1; + PIO_dport1_T2 <= #1 PIO_mode0_T2; + PIO_dport1_T4 <= #1 PIO_mode0_T4; + PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; + end + else if (rst_i) + begin + PIO_dport1_T1 <= #1 PIO_mode0_T1; + PIO_dport1_T2 <= #1 PIO_mode0_T2; + PIO_dport1_T4 <= #1 PIO_mode0_T4; + PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; + end + else if(sel_PIO_dport1) + begin + PIO_dport1_T1 <= #1 dat_i[ 7: 0]; + PIO_dport1_T2 <= #1 dat_i[15: 8]; + PIO_dport1_T4 <= #1 dat_i[23:16]; + PIO_dport1_Teoc <= #1 dat_i[31:24]; + end + + // generate DMA device0 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + DMA_dev0_Tm <= #1 DMA_mode0_Tm; + DMA_dev0_Td <= #1 DMA_mode0_Td; + DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; + end + else if (rst_i) + begin + DMA_dev0_Tm <= #1 DMA_mode0_Tm; + DMA_dev0_Td <= #1 DMA_mode0_Td; + DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; + end + else if(sel_DMA_dev0) + begin + DMA_dev0_Tm <= #1 dat_i[ 7: 0]; + DMA_dev0_Td <= #1 dat_i[15: 8]; + DMA_dev0_Teoc <= #1 dat_i[31:24]; + end + + // generate DMA device1 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + DMA_dev1_Tm <= #1 DMA_mode0_Tm; + DMA_dev1_Td <= #1 DMA_mode0_Td; + DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; + end + else if (rst_i) + begin + DMA_dev1_Tm <= #1 DMA_mode0_Tm; + DMA_dev1_Td <= #1 DMA_mode0_Td; + DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; + end + else if(sel_DMA_dev1) + begin + DMA_dev1_Tm <= #1 dat_i[ 7: 0]; + DMA_dev1_Td <= #1 dat_i[15: 8]; + DMA_dev1_Teoc <= #1 dat_i[31:24]; + end + + // + // generate WISHBONE interconnect signals + // + reg [31:0] Q; + + // generate acknowledge signal + assign ack_o = PIOack | CONsel; // | DMAack; // since DMAack is derived from CONsel this is OK + + // generate error signal + assign err_o = cyc_i & stb_i & berr; + + // generate retry signal (for OCIDEC-3 and above only) + assign rty_o = cyc_i & stb_i & brty; + + // generate interrupt signal + assign inta_o = StatReg[0]; + + // generate output multiplexor + always@(`ATA_ADR or CtrlReg or StatReg or + PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc or + PIO_dport0_T1 or PIO_dport0_T2 or PIO_dport0_T4 or PIO_dport0_Teoc or + PIO_dport1_T1 or PIO_dport1_T2 or PIO_dport1_T4 or PIO_dport1_Teoc or + DMA_dev0_Tm or DMA_dev0_Td or DMA_dev0_Teoc or + DMA_dev1_Tm or DMA_dev1_Td or DMA_dev1_Teoc or + DMAq + ) + case (`ATA_ADR) // synopsis full_case parallel_case + `ATA_CTRL_REG: Q = CtrlReg; + `ATA_STAT_REG: Q = StatReg; + `ATA_PIO_CMD : Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1}; + `ATA_PIO_DP0 : Q = {PIO_dport0_Teoc, PIO_dport0_T4, PIO_dport0_T2, PIO_dport0_T1}; + `ATA_PIO_DP1 : Q = {PIO_dport1_Teoc, PIO_dport1_T4, PIO_dport1_T2, PIO_dport1_T1}; + `ATA_DMA_DEV0: Q = {DMA_dev0_Teoc, 8'h0, DMA_dev0_Td, DMA_dev0_Tm}; + `ATA_DMA_DEV1: Q = {DMA_dev1_Teoc, 8'h0, DMA_dev1_Td, DMA_dev1_Tm}; + `ATA_DMA_PORT: Q = DMAq; + default: Q = 0; + endcase + + // assign DAT_O output + assign dat_o = `ATA_DEV_ADR ? {16'h0, PIOq} : Q; + +endmodule Index: ata/trunk/rtl/verilog/ocidec-1/ud_cnt.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/ud_cnt.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/ud_cnt.v (revision 33) @@ -0,0 +1,100 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Generic Up/Down counter //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ud_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $ +// +// $Date: 2002-02-16 10:42:17 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + + +///////////////////////////// +// general purpose counter // +///////////////////////////// + +`include "timescale.v" + +module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco); + // parameter declaration + parameter SIZE = 8; + parameter RESD = {SIZE{1'b0}}; // data after reset + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + input cnt_en; // count enable + input ud; // up/not down + input nld; // synchronous active low load + input [SIZE-1:0] d; // load counter value + output [SIZE-1:0] q; // current counter value + input rci; // carry input + output rco; // carry output + + // variable declarations + reg [SIZE-1:0] Qi; // intermediate value + wire [SIZE:0] val; // carry+result + + // + // Module body + // + + assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci); + + always@(posedge clk or negedge nReset) + begin + if (~nReset) + Qi <= #1 RESD; + else if (rst) + Qi <= #1 RESD; + else if (~nld) + Qi <= #1 d; + else if (cnt_en) + Qi <= #1 val[SIZE-1:0]; + end + + // assign outputs + assign q = Qi; + assign rco = val[SIZE]; +endmodule + + Index: ata/trunk/rtl/verilog/ocidec-1/ro_cnt.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/ro_cnt.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/ro_cnt.v (revision 33) @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Run-Once counter //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ro_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $ +// +// $Date: 2002-02-16 10:42:17 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + + +/////////////////////////// +// run-once down-counter // +/////////////////////////// + +// counts D+1 cycles before generating 'DONE' + +`include "timescale.v" + +module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q); + + // parameter declaration + parameter SIZE = 8; + + parameter UD = 1'b0; // default count down + parameter ID = {SIZE{1'b0}}; // initial data after reset + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + input cnt_en; // count enable + input go; // load counter and start sequence + output done; // done counting + input [SIZE-1:0] d; // load counter value + output [SIZE-1:0] q; // current counter value + + // variable declarations + reg rci; + wire nld, rco; + + // + // module body + // + + always@(posedge clk or negedge nReset) + if (~nReset) + rci <= #1 1'b0; + else if (rst) + rci <= #1 1'b0; + else //if (cnt_en) + rci <= #1 go | (rci & !rco); + + assign nld = !go; + + // hookup counter + ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en), + .ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco)); + + + // assign outputs + + assign done = rco; + +endmodule + + + Index: ata/trunk/rtl/verilog/ocidec-1/timescale.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-1/timescale.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-1/timescale.v (revision 33) @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + Index: ata/trunk/rtl/verilog/ocidec-2/atahost_controller.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/atahost_controller.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/atahost_controller.v (revision 33) @@ -0,0 +1,275 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores ATA/ATAPI-5 Host Controller //// +//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// +// CVS Log +// +// $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $ +// +// $Date: 2002-05-19 06:05:28 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + +// +// OCIDEC2 supports: +// -Common Compatible timing access to all connected devices +// -Separate timing accesses to data port +// -No DMA support +// + +`include "timescale.v" + +module atahost_controller ( + clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1, + cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen, + dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen, + dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen, + PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe, + RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ + ); + + // + // parameters + // + parameter TWIDTH = 8; + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns + + // + // inputs & outputs + // + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + + output irq; // interrupt request signal + reg irq; + + // control / registers + input IDEctrl_rst; + input IDEctrl_IDEen; + input IDEctrl_FATR0; + input IDEctrl_FATR1; + + input [7:0] cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc; + input cmdport_IORDYen; // PIO command port / non-fast timing + + input [7:0] dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc; + input dport0_IORDYen; // PIO mode data-port / fast timing device 0 + + input [7:0] dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc; + input dport1_IORDYen; // PIO mode data-port / fast timing device 1 + + input PIOreq; // PIO transfer request + output PIOack; // PIO transfer ended + input [ 3:0] PIOa; // PIO address + input [15:0] PIOd; // PIO data in + output [15:0] PIOq; // PIO data out + input PIOwe; // PIO direction bit '1'=write, '0'=read + + reg PIOack; + + // ATA signals + output RESETn; + input [15:0] DDi; + output [15:0] DDo; + output DDoe; + output [ 2:0] DA; + output CS0n; + output CS1n; + output DIORn; + output DIOWn; + input IORDY; + input INTRQ; + + reg RESETn; + reg [15:0] DDo; + reg DDoe; + reg [ 2:0] DA; + reg CS0n; + reg CS1n; + reg DIORn; + reg DIOWn; + + + // + // signals & variables + // + wire PIOdone; // PIO timing controller done + + // PIO signals + wire PIOdior, PIOdiow, PIOoe; + + // synchronized ATA inputs + reg sIORDY; + + // + // module body + // + + + // synchronize incoming signals + reg cIORDY; // capture IORDY + reg cINTRQ; // capture INTRQ + + always @(posedge clk) + begin : synch_incoming + + cIORDY <= #1 IORDY; + cINTRQ <= #1 INTRQ; + + sIORDY <= #1 cIORDY; + irq <= #1 cINTRQ; + end + + // generate ATA signals + always @(posedge clk or negedge nReset) + if (~nReset) + begin + RESETn <= #1 1'b0; + DIORn <= #1 1'b1; + DIOWn <= #1 1'b1; + DA <= #1 0; + CS0n <= #1 1'b1; + CS1n <= #1 1'b1; + DDo <= #1 0; + DDoe <= #1 1'b0; + end + else if (rst) + begin + RESETn <= #1 1'b0; + DIORn <= #1 1'b1; + DIOWn <= #1 1'b1; + DA <= #1 0; + CS0n <= #1 1'b1; + CS1n <= #1 1'b1; + DDo <= #1 0; + DDoe <= #1 1'b0; + end + else + begin + RESETn <= #1 !IDEctrl_rst; + DA <= #1 PIOa[2:0]; + CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0' + CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1' + + DDo <= #1 PIOd; + DDoe <= #1 PIOoe; + DIORn <= #1 !PIOdior; + DIOWn <= #1 !PIOdiow; + end + + // generate selected device + reg SelDev; + always @(posedge clk) + if (PIOdone & (PIOa == 4'b0110) & PIOwe) + SelDev <= #1 PIOd[4]; + + // generate PIOgo signal + always @(posedge clk or negedge nReset) + if (~nReset) + begin + dPIOreq <= #1 1'b0; + PIOgo <= #1 1'b0; + end + else if (rst) + begin + dPIOreq <= #1 1'b0; + PIOgo <= #1 1'b0; + end + else + begin + dPIOreq <= #1 PIOreq & !PIOack; + PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen; + end + + // + // Hookup PIO access controller + // + atahost_pio_actrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) + PIO_access_control ( + .clk(clk), + .nReset(nReset), + .rst(rst), + .IDEctrl_FATR0(IDEctrl_FATR0), + .IDEctrl_FATR1(IDEctrl_FATR1), + .cmdport_T1(cmdport_T1), + .cmdport_T2(cmdport_T2), + .cmdport_T4(cmdport_T4), + .cmdport_Teoc(cmdport_Teoc), + .cmdport_IORDYen(cmdport_IORDYen), + .dport0_T1(dport0_T1), + .dport0_T2(dport0_T2), + .dport0_T4(dport0_T4), + .dport0_Teoc(dport0_Teoc), + .dport0_IORDYen(dport0_IORDYen), + .dport1_T1(dport1_T1), + .dport1_T2(dport1_T2), + .dport1_T4(dport1_T4), + .dport1_Teoc(dport1_Teoc), + .dport1_IORDYen(dport1_IORDYen), + .SelDev(SelDev), + .go(PIOgo), + .done(PIOdone), + .dir(PIOwe), + .a(PIOa), + .q(PIOq), + .DDi(DDi), + .oe(PIOoe), + .DIOR(PIOdior), + .DIOW(PIOdiow), + .IORDY(sIORDY) + ); + + always @(posedge clk) + PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) + +endmodule Index: ata/trunk/rtl/verilog/ocidec-2/revision_history.txt =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/revision_history.txt (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/revision_history.txt (revision 33) @@ -0,0 +1,14 @@ +----------------------------- +Revision: 1.0 +Date: februar 18th, 2002 +Author: Richard Herveille +- initial Verilog release +----------------------------- + +----------------------------- +Revision: 1.1 +Date: May 19th, 2002. +Author: Richard Herveille +- Fixed a potential bug that forced the core into an unknown state + when an asynchronous reset was given without a running clock +----------------------------- Index: ata/trunk/rtl/verilog/ocidec-2/ud_cnt.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/ud_cnt.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/ud_cnt.v (revision 33) @@ -0,0 +1,105 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Generic Up/Down counter //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ud_cnt.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ +// +// $Date: 2002-02-18 14:26:46 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/02/16 10:42:17 rherveille +// Added disclaimer +// Added CVS information +// Changed core for new internal counter libraries (synthesis fixes). +// +// + + +///////////////////////////// +// general purpose counter // +///////////////////////////// + +`include "timescale.v" + +module ud_cnt (clk, nReset, rst, cnt_en, ud, nld, d, q, rci, rco); + // parameter declaration + parameter SIZE = 8; + parameter RESD = {SIZE{1'b0}}; // data after reset + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + input cnt_en; // count enable + input ud; // up/not down + input nld; // synchronous active low load + input [SIZE-1:0] d; // load counter value + output [SIZE-1:0] q; // current counter value + input rci; // carry input + output rco; // carry output + + // variable declarations + reg [SIZE-1:0] Qi; // intermediate value + wire [SIZE:0] val; // carry+result + + // + // Module body + // + + assign val = ud ? ( {1'b0, Qi} + rci) : ( {1'b0, Qi} - rci); + + always@(posedge clk or negedge nReset) + begin + if (~nReset) + Qi <= #1 RESD; + else if (rst) + Qi <= #1 RESD; + else if (~nld) + Qi <= #1 d; + else if (cnt_en) + Qi <= #1 val[SIZE-1:0]; + end + + // assign outputs + assign q = Qi; + assign rco = val[SIZE]; +endmodule + + Index: ata/trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v (revision 33) @@ -0,0 +1,197 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores ATA/ATAPI-5 Host Controller //// +//// PIO Access Controller (common for OCIDEC 2 and above) //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// +// CVS Log +// +// $Id: atahost_pio_actrl.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ +// +// $Date: 2002-02-18 14:26:46 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ + +`include "timescale.v" + +module atahost_pio_actrl ( + clk, nReset, rst, IDEctrl_FATR0, IDEctrl_FATR1, + cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen, + dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen, + dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen, + SelDev, go, done, dir, a, q, DDi, oe, DIOR, DIOW, IORDY + ); + + // + // parameters + // + parameter TWIDTH = 8; + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns + + // + // inputs & outputs + // + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + + input IDEctrl_FATR0; + input IDEctrl_FATR1; + + input [7:0] cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc; + input cmdport_IORDYen; // PIO command port / non-fast timing + + input [7:0] dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc; + input dport0_IORDYen; // PIO mode data-port / fast timing device 0 + + input [7:0] dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc; + input dport1_IORDYen; // PIO mode data-port / fast timing device 1 + + input SelDev; // Selected device + + input go; // Start transfer sequence + output done; // Transfer sequence done + input dir; // Transfer direction '1'=write, '0'=read + input [ 3:0] a; // PIO transfer address + output [15:0] q; // Data read from ATA devices + reg [15:0] q; + + input [15:0] DDi; // Data from ATA DD bus + output oe; // DDbus output-enable signal + + output DIOR; + output DIOW; + input IORDY; + + // + // signals & variables + // + wire dstrb; + reg [7:0] T1, T2, T4, Teoc; + reg IORDYen; + + + // + // Module body + // + + // PIO transfer control + // + // capture ATA data for PIO access + always@(posedge clk) + if (dstrb) + q <= DDi; + + + // PIO timing controllers + // + // select timing settings for the addressed port + always@(posedge clk) + if (|a) // command ports accessed ? + begin + T1 <= #1 cmdport_T1; + T2 <= #1 cmdport_T2; + T4 <= #1 cmdport_T4; + Teoc <= #1 cmdport_Teoc; + IORDYen <= #1 cmdport_IORDYen; + end + else // data ports accessed + begin + if (SelDev & IDEctrl_FATR1) + begin + T1 <= #1 dport1_T1; + T2 <= #1 dport1_T2; + T4 <= #1 dport1_T4; + Teoc <= #1 dport1_Teoc; + IORDYen <= #1 dport1_IORDYen; + end + else if (!SelDev & IDEctrl_FATR0) + begin + T1 <= #1 dport0_T1; + T2 <= #1 dport0_T2; + T4 <= #1 dport0_T4; + Teoc <= #1 dport0_Teoc; + IORDYen <= #1 dport0_IORDYen; + end + else + begin + T1 <= #1 cmdport_T1; + T2 <= #1 cmdport_T2; + T4 <= #1 cmdport_T4; + Teoc <= #1 cmdport_Teoc; + IORDYen <= #1 cmdport_IORDYen; + end + end + + // + // hookup timing controller + // + atahost_pio_tctrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) + PIO_timing_controller ( + .clk(clk), + .nReset(nReset), + .rst(rst), + .IORDY_en(IORDYen), + .T1(T1), + .T2(T2), + .T4(T4), + .Teoc(Teoc), + .go(go), + .we(dir), + .oe(oe), + .done(done), + .dstrb(dstrb), + .DIOR(DIOR), + .DIOW(DIOW), + .IORDY(IORDY) + ); + +endmodule + Index: ata/trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v (revision 33) @@ -0,0 +1,265 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores ATA/ATAPI-5 Host Controller //// +//// PIO Timing Controller (common for all OCIDEC cores) //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: atahost_pio_tctrl.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ +// +// $Date: 2002-02-18 14:26:46 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// Rev. 1.0 June 27th, 2001. Initial Verilog release +// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues. +// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation. +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/02/16 10:42:17 rherveille +// Added disclaimer +// Added CVS information +// Changed core for new internal counter libraries (synthesis fixes). +// +// + + +// +// Timing PIO mode transfers +//-------------------------------------------- +// T0: cycle time +// T1: address valid to DIOR-/DIOW- +// T2: DIOR-/DIOW- pulse width +// T2i: DIOR-/DIOW- recovery time +// T3: DIOW- data setup +// T4: DIOW- data hold +// T5: DIOR- data setup +// T6: DIOR- data hold +// T9: address hold from DIOR-/DIOW- negated +// Trd: Read data valid to IORDY asserted +// Ta: IORDY setup time +// Tb: IORDY pulse width +// +// Transfer sequence +//-------------------------------- +// 1) set address (DA, CS0-, CS1-) +// 2) wait for T1 +// 3) assert DIOR-/DIOW- +// when write action present Data (timing spec. T3 always honored), enable output enable-signal +// 4) wait for T2 +// 5) check IORDY +// when not IORDY goto 5 +// when IORDY negate DIOW-/DIOR-, latch data (if read action) +// when write, hold data for T4, disable output-enable signal +// 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest +// 7) start new cycle + +`include "timescale.v" + +module atahost_pio_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY); + // parameter declarations + parameter TWIDTH = 8; + parameter PIO_MODE0_T1 = 6; // 70ns + parameter PIO_MODE0_T2 = 28; // 290ns + parameter PIO_MODE0_T4 = 2; // 30ns + parameter PIO_MODE0_Teoc = 23; // 240ns + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + + // timing & control register settings + input IORDY_en; // use IORDY (or not) + input [TWIDTH-1:0] T1; // T1 time (in clk-ticks) + input [TWIDTH-1:0] T2; // T1 time (in clk-ticks) + input [TWIDTH-1:0] T4; // T1 time (in clk-ticks) + input [TWIDTH-1:0] Teoc; // T1 time (in clk-ticks) + + // control signals + input go; // PIO controller selected (strobe signal) + input we; // write enable signal. 1'b0 == read, 1'b1 == write + + // return signals + output oe; // output enable signal + reg oe; + output done; // finished cycle + output dstrb; // data strobe, latch data (during read) + reg dstrb; + + // ata signals + output DIOR; // IOread signal, active high + reg DIOR; + output DIOW; // IOwrite signal, active high + reg DIOW; + input IORDY; // IOrDY signal + + + // + // constant declarations + // + // PIO mode 0 settings (@100MHz clock) + wire [TWIDTH-1:0] T1_m0 = PIO_MODE0_T1; + wire [TWIDTH-1:0] T2_m0 = PIO_MODE0_T2; + wire [TWIDTH-1:0] T4_m0 = PIO_MODE0_T4; + wire [TWIDTH-1:0] Teoc_m0 = PIO_MODE0_Teoc; + + // + // variable declaration + // + reg busy, hold_go; + wire igo; + wire T1done, T2done, T4done, Teoc_done, IORDY_done; + reg hT2done; + + // + // module body + // + + // generate internal go strobe + // strecht go until ready for new cycle + always@(posedge clk or negedge nReset) + if (~nReset) + begin + busy <= #1 1'b0; + hold_go <= #1 1'b0; + end + else if (rst) + begin + busy <= #1 1'b0; + hold_go <= #1 1'b0; + end + else + begin + busy <= #1 (igo | busy) & !Teoc_done; + hold_go <= #1 (go | (hold_go & busy)) & !igo; + end + + assign igo = (go | hold_go) & !busy; + + // 1) hookup T1 counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1) + t1_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(igo), + .d(T1), + .q(), + .done(T1done) + ); + + // 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device + always@(posedge clk or negedge nReset) + if (~nReset) + begin + DIOR <= #1 1'b0; + DIOW <= #1 1'b0; + oe <= #1 1'b0; + end + else if (rst) + begin + DIOR <= #1 1'b0; + DIOW <= #1 1'b0; + oe <= #1 1'b0; + end + else + begin + DIOR <= #1 (!we & T1done) | (DIOR & !IORDY_done); + DIOW <= #1 ( we & T1done) | (DIOW & !IORDY_done); + oe <= #1 ( (we & igo) | oe) & !T4done; // negate oe when t4-done + end + + // 3) hookup T2 counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2) + t2_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(T1done), + .d(T2), + .q(), + .done(T2done) + ); + + // 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) + // hold T2done + always@(posedge clk or negedge nReset) + if (~nReset) + hT2done <= #1 1'b0; + else if (rst) + hT2done <= #1 1'b0; + else + hT2done <= #1 (T2done | hT2done) & !IORDY_done; + + assign IORDY_done = (T2done | hT2done) & (IORDY | !IORDY_en); + + // generate datastrobe, capture data at rising DIOR- edge + always@(posedge clk) + dstrb <= #1 IORDY_done; + + // hookup data hold counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4) + dhold_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(IORDY_done), + .d(T4), + .q(), + .done(T4done) + ); + + assign done = T4done; // placing done here provides the fastest return possible, + // while still guaranteeing data and address hold-times + + // 5) hookup end_of_cycle counter + ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc) + eoc_cnt( + .clk(clk), + .rst(rst), + .nReset(nReset), + .cnt_en(1'b1), + .go(IORDY_done), + .d(Teoc), + .q(), + .done(Teoc_done) + ); + +endmodule Index: ata/trunk/rtl/verilog/ocidec-2/ro_cnt.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/ro_cnt.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/ro_cnt.v (revision 33) @@ -0,0 +1,111 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Run-Once counter //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ro_cnt.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ +// +// $Date: 2002-02-18 14:26:46 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/02/16 10:42:17 rherveille +// Added disclaimer +// Added CVS information +// Changed core for new internal counter libraries (synthesis fixes). +// +// + + +/////////////////////////// +// run-once down-counter // +/////////////////////////// + +// counts D+1 cycles before generating 'DONE' + +`include "timescale.v" + +module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q); + + // parameter declaration + parameter SIZE = 8; + + parameter UD = 1'b0; // default count down + parameter ID = {SIZE{1'b0}}; // initial data after reset + + // inputs & outputs + input clk; // master clock + input nReset; // asynchronous active low reset + input rst; // synchronous active high reset + input cnt_en; // count enable + input go; // load counter and start sequence + output done; // done counting + input [SIZE-1:0] d; // load counter value + output [SIZE-1:0] q; // current counter value + + // variable declarations + reg rci; + wire nld, rco; + + // + // module body + // + + always@(posedge clk or negedge nReset) + if (~nReset) + rci <= #1 1'b0; + else if (rst) + rci <= #1 1'b0; + else //if (cnt_en) + rci <= #1 go | (rci & !rco); + + assign nld = !go; + + // hookup counter + ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en), + .ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco)); + + + // assign outputs + + assign done = rco; + +endmodule + + + Index: ata/trunk/rtl/verilog/ocidec-2/atahost_top.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/atahost_top.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/atahost_top.v (revision 33) @@ -0,0 +1,296 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores ATA/ATAPI-5 Host Controller //// +//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) Top Level //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// +// CVS Log +// +// $Id: atahost_top.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ +// +// $Date: 2002-02-18 14:26:46 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + +// +// DeviceType: OCIDEC-2: OpenCores IDE Controller type2 +// Features: PIO Compatible Timing, PIO Fast Timing 0/1 +// DeviceID: 0x02 +// RevNo : 0x00 +// + +// +// Host signals: +// Reset +// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. +// DIOW- write strobe. The rising edge latches data from DD into the device. +// DA(2:0) 3bit binary coded adress +// CS0- select command block registers +// CS1- select control block registers +// + +`include "timescale.v" + +module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o, + resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o, + cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i); + // + // Parameter declarations + // + parameter ARST_LVL = 1'b0; // asynchronous reset level + + parameter TWIDTH = 8; // counter width + // PIO mode 0 settings (@100MHz clock) + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + // + // inputs & outputs + // + + // WISHBONE SYSCON signals + input wb_clk_i; // master clock in + input arst_i; // asynchronous reset + input wb_rst_i; // synchronous reset + + // WISHBONE SLAVE signals + input wb_cyc_i; // valid bus cycle input + input wb_stb_i; // strobe/core select input + output wb_ack_o; // strobe acknowledge output + output wb_err_o; // error output + input [6:2] wb_adr_i; // A6 = '1' ATA devices selected + // A5 = '1' CS1- asserted, '0' CS0- asserted + // A4..A2 ATA address lines + // A6 = '0' ATA controller selected + input [31:0] wb_dat_i; // Databus in + output [31:0] wb_dat_o; // Databus out + input [ 3:0] wb_sel_i; // Byte select signals + input wb_we_i; // Write enable input + output wb_inta_o; // interrupt request signal + + // ATA signals + output resetn_pad_o; + input [15:0] dd_pad_i; + output [15:0] dd_pad_o; + output dd_padoe_o; + output [ 2:0] da_pad_o; + output cs0n_pad_o; + output cs1n_pad_o; + + output diorn_pad_o; + output diown_pad_o; + input iordy_pad_i; + input intrq_pad_i; + + // + // constant declarations + // + parameter [3:0] DeviceId = 4'h2; + parameter [3:0] RevisionNo = 4'h0; + + // + // Variable declarations + // + + // registers + wire IDEctrl_IDEen, IDEctrl_rst; + wire IDEctrl_FATR0, IDEctrl_FATR1; + wire [ 7:0] PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc; + wire PIO_cmdport_IORDYen; + wire [ 7:0] PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc; + wire PIO_dport0_IORDYen; + wire [ 7:0] PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc; + wire PIO_dport1_IORDYen; + + wire PIOack; + wire [15:0] PIOq; + + wire irq; // ATA bus IRQ signal + + + ///////////////// + // Module body // + ///////////////// + + // generate asynchronous reset level + // arst_signal is either a wire or a NOT-gate + wire arst_signal = arst_i ^ ARST_LVL; + + // + // hookup wishbone slave + // + atahost_wb_slave #(DeviceId, RevisionNo, PIO_mode0_T1, + PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc, 0, 0, 0) + u0 ( + // WISHBONE SYSCON signals + .clk_i(wb_clk_i), + .arst_i(arst_signal), + .rst_i(wb_rst_i), + + // WISHBONE SLAVE signals + .cyc_i(wb_cyc_i), + .stb_i(wb_stb_i), + .ack_o(wb_ack_o), + .rty_o(), + .err_o(wb_err_o), + .adr_i(wb_adr_i), + .dat_i(wb_dat_i), + .dat_o(wb_dat_o), + .sel_i(wb_sel_i), + .we_i(wb_we_i), + .inta_o(wb_inta_o), + + // PIO control inputs + .PIOsel(PIOsel), + // PIOtip is only asserted during a PIO transfer (No shit! ;) + // Since it is impossible to read the status register and access the PIO registers at the same time + // this bit is useless (besides using-up resources) + .PIOtip(1'b0), + .PIOack(PIOack), + .PIOq(PIOq), + .PIOpp_full(1'b0), // OCIDEC-2 does not support PIO-write pingpong, negate signal + .irq(irq), + + // DMA control inputs (negate all of them, OCIDEC-2 does not support DMA) + .DMAsel(), + .DMAtip(1'b0), + .DMAack(1'b0), + .DMARxEmpty(1'b0), + .DMATxFull(1'b0), + .DMA_dmarq(1'b0), + .DMAq(32'h0), + + // outputs + // control register outputs + .IDEctrl_rst(IDEctrl_rst), + .IDEctrl_IDEen(IDEctrl_IDEen), + .IDEctrl_FATR0(IDEctrl_FATR0), + .IDEctrl_FATR1(IDEctrl_FATR1), + .IDEctrl_ppen(), + + .DMActrl_DMAen(), + .DMActrl_dir(), + .DMActrl_BeLeC0(), + .DMActrl_BeLeC1(), + + // CMD port timing registers + .PIO_cmdport_T1(PIO_cmdport_T1), + .PIO_cmdport_T2(PIO_cmdport_T2), + .PIO_cmdport_T4(PIO_cmdport_T4), + .PIO_cmdport_Teoc(PIO_cmdport_Teoc), + .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen), + + // data-port0 timing registers + .PIO_dport0_T1(PIO_dport0_T1), + .PIO_dport0_T2(PIO_dport0_T2), + .PIO_dport0_T4(PIO_dport0_T4), + .PIO_dport0_Teoc(PIO_dport0_Teoc), + .PIO_dport0_IORDYen(PIO_dport0_IORDYen), + + // data-port1 timing registers + .PIO_dport1_T1(PIO_dport1_T1), + .PIO_dport1_T2(PIO_dport1_T2), + .PIO_dport1_T4(PIO_dport1_T4), + .PIO_dport1_Teoc(PIO_dport1_Teoc), + .PIO_dport1_IORDYen(PIO_dport1_IORDYen), + + // DMA device0 timing registers + .DMA_dev0_Tm(), + .DMA_dev0_Td(), + .DMA_dev0_Teoc(), + + // DMA device1 timing registers + .DMA_dev1_Tm(), + .DMA_dev1_Td(), + .DMA_dev1_Teoc() + ); + + + // + // hookup controller section + // + atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc) + u1 ( + .clk(wb_clk_i), + .nReset(arst_signal), + .rst(wb_rst_i), + .irq(irq), + .IDEctrl_rst(IDEctrl_rst), + .IDEctrl_IDEen(IDEctrl_IDEen), + .IDEctrl_FATR0(IDEctrl_FATR0), + .IDEctrl_FATR1(IDEctrl_FATR1), + .cmdport_T1(PIO_cmdport_T1), + .cmdport_T2(PIO_cmdport_T2), + .cmdport_T4(PIO_cmdport_T4), + .cmdport_Teoc(PIO_cmdport_Teoc), + .cmdport_IORDYen(PIO_cmdport_IORDYen), + .dport0_T1(PIO_dport0_T1), + .dport0_T2(PIO_dport0_T2), + .dport0_T4(PIO_dport0_T4), + .dport0_Teoc(PIO_dport0_Teoc), + .dport0_IORDYen(PIO_dport0_IORDYen), + .dport1_T1(PIO_dport1_T1), + .dport1_T2(PIO_dport1_T2), + .dport1_T4(PIO_dport1_T4), + .dport1_Teoc(PIO_dport1_Teoc), + .dport1_IORDYen(PIO_dport1_IORDYen), + .PIOreq(PIOsel), + .PIOack(PIOack), + .PIOa(wb_adr_i[5:2]), + .PIOd(wb_dat_i[15:0]), + .PIOq(PIOq), + .PIOwe(wb_we_i), + .RESETn(resetn_pad_o), + .DDi(dd_pad_i), + .DDo(dd_pad_o), + .DDoe(dd_padoe_o), + .DA(da_pad_o), + .CS0n(cs0n_pad_o), + .CS1n(cs1n_pad_o), + .DIORn(diorn_pad_o), + .DIOWn(diown_pad_o), + .IORDY(iordy_pad_i), + .INTRQ(intrq_pad_i) + ); + +endmodule + Index: ata/trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v (revision 33) @@ -0,0 +1,484 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OCIDEC-1 ATA/ATAPI-5 Controller //// +//// Wishbone Slave interface (common for all OCIDEC cores) //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// +// CVS Log +// +// $Id: atahost_wb_slave.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $ +// +// $Date: 2002-02-18 14:26:46 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module atahost_wb_slave ( + clk_i, arst_i, rst_i, cyc_i, stb_i, ack_o, rty_o, err_o, adr_i, dat_i, dat_o, sel_i, we_i, inta_o, + PIOsel, PIOtip, PIOack, PIOq, PIOpp_full, irq, + DMAsel, DMAtip, DMAack, DMARxEmpty, DMATxFull, DMA_dmarq, DMAq, + IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR1, IDEctrl_FATR0, IDEctrl_ppen, + DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1, + PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, + PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc, PIO_dport0_IORDYen, + PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc, PIO_dport1_IORDYen, + DMA_dev0_Tm, DMA_dev0_Td, DMA_dev0_Teoc, DMA_dev1_Tm, DMA_dev1_Td, DMA_dev1_Teoc + ); + + // + // Parameters + // + parameter DeviceId = 4'h0; + parameter RevisionNo = 4'h0; + + // PIO mode 0 settings (@100MHz clock) + parameter PIO_mode0_T1 = 6; // 70ns + parameter PIO_mode0_T2 = 28; // 290ns + parameter PIO_mode0_T4 = 2; // 30ns + parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + // Multiword DMA mode 0 settings (@100MHz clock) + parameter DMA_mode0_Tm = 6; // 50ns + parameter DMA_mode0_Td = 21; // 215ns + parameter DMA_mode0_Teoc = 21; // 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + + // + // inputs & outputs + // + + // WISHBONE SYSCON signals + input clk_i; // master clock in + input arst_i; // asynchronous active low reset + input rst_i; // synchronous active high reset + + // WISHBONE SLAVE signals + input cyc_i; // valid bus cycle input + input stb_i; // strobe/core select input + output ack_o; // strobe acknowledge output + output rty_o; // retry output + output err_o; // error output + input [6:2] adr_i; // A6 = '1' ATA devices selected + // A5 = '1' CS1- asserted, '0' CS0- asserted + // A4..A2 ATA address lines + // A6 = '0' ATA controller selected + input [31:0] dat_i; // Databus in + output [31:0] dat_o; // Databus out + input [ 3:0] sel_i; // Byte select signals + input we_i; // Write enable input + output inta_o; // interrupt request signal IDE0 + + // PIO control input + output PIOsel; + input PIOtip; // PIO transfer in progress + input PIOack; // PIO acknowledge signal + input [15:0] PIOq; // PIO data input + input PIOpp_full; // PIO write-ping-pong buffers full + input irq; // interrupt signal input + + // DMA control inputs + output DMAsel; + input DMAtip; // DMA transfer in progress + input DMAack; // DMA transfer acknowledge + input DMARxEmpty; // DMA receive buffer empty + input DMATxFull; // DMA transmit buffer full + input DMA_dmarq; // wishbone DMA request + input [31:0] DMAq; + + // outputs + // control register outputs + output IDEctrl_rst; + output IDEctrl_IDEen; + output IDEctrl_FATR1; + output IDEctrl_FATR0; + output IDEctrl_ppen; + output DMActrl_DMAen; + output DMActrl_dir; + output DMActrl_BeLeC0; + output DMActrl_BeLeC1; + + // CMD port timing registers + output [7:0] PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc; + output PIO_cmdport_IORDYen; + + reg [7:0] PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc; + + // data-port0 timing registers + output [7:0] PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc; + output PIO_dport0_IORDYen; + + reg [7:0] PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc; + + // data-port1 timing registers + output [7:0] PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc; + output PIO_dport1_IORDYen; + + reg [7:0] PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc; + + // DMA device0 timing registers + output [7:0] DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc; + + reg [7:0] DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc; + + // DMA device1 timing registers + output [7:0] DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc; + + reg [7:0] DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc; + + + // + // constants + // + + // addresses + `define ATA_DEV_ADR adr_i[6] + `define ATA_ADR adr_i[5:2] + + `define ATA_CTRL_REG 4'b0000 + `define ATA_STAT_REG 4'b0001 + `define ATA_PIO_CMD 4'b0010 + `define ATA_PIO_DP0 4'b0011 + `define ATA_PIO_DP1 4'b0100 + `define ATA_DMA_DEV0 4'b0101 + `define ATA_DMA_DEV1 4'b0110 + // reserved // + `define ATA_DMA_PORT 4'b1111 + + + // + // signals + // + + // registers + reg [31:0] CtrlReg; // control register + wire [31:0] StatReg; // status register + + // store ping-pong-full signal + reg store_pp_full; + + + // + // generate bus cycle / address decoder + // + wire w_acc = &sel_i[1:0]; // word access + wire dw_acc = &sel_i; // double word access + + // bus error + wire berr = `ATA_DEV_ADR ? !w_acc : !dw_acc; + + // PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong-full + wire PIOsel = cyc_i & stb_i & `ATA_DEV_ADR & w_acc & !(DMAtip | store_pp_full); + + // CON accesses only 32bit wide + wire CONsel = cyc_i & stb_i & !(`ATA_DEV_ADR) & dw_acc; + wire DMAsel = CONsel & (`ATA_ADR == `ATA_DMA_PORT); + + // bus retry (OCIDEC-3 and above) + // store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle + always@(posedge clk_i) + if (!PIOsel) + store_pp_full <= #1 PIOpp_full; + + wire brty = (`ATA_DEV_ADR & w_acc) & (DMAtip | store_pp_full); + + // + // generate registers + // + + // generate register select signals + wire sel_ctrl = CONsel & we_i & (`ATA_ADR == `ATA_CTRL_REG); + wire sel_stat = CONsel & we_i & (`ATA_ADR == `ATA_STAT_REG); + wire sel_PIO_cmdport = CONsel & we_i & (`ATA_ADR == `ATA_PIO_CMD); + wire sel_PIO_dport0 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP0); + wire sel_PIO_dport1 = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP1); + wire sel_DMA_dev0 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV0); + wire sel_DMA_dev1 = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV1); + // reserved 0x1c-0x38 + // reserved 0x3c : DMA-port + + + // generate control register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + CtrlReg[31:1] <= #1 0; + CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) + end + else if (rst_i) + begin + CtrlReg[31:1] <= #1 0; + CtrlReg[0] <= #1 1'b1; // set reset bit (ATA-RESETn line) + end + else if (sel_ctrl) + CtrlReg <= #1 dat_i; + + // assign bits + assign DMActrl_DMAen = CtrlReg[15]; + assign DMActrl_dir = CtrlReg[13]; + assign DMActrl_BeLeC1 = CtrlReg[9]; + assign DMActrl_BeLeC0 = CtrlReg[8]; + assign IDEctrl_IDEen = CtrlReg[7]; + assign IDEctrl_FATR1 = CtrlReg[6]; + assign IDEctrl_FATR0 = CtrlReg[5]; + assign IDEctrl_ppen = CtrlReg[4]; + assign PIO_dport1_IORDYen = CtrlReg[3]; + assign PIO_dport0_IORDYen = CtrlReg[2]; + assign PIO_cmdport_IORDYen = CtrlReg[1]; + assign IDEctrl_rst = CtrlReg[0]; + + + // generate status register clearable bits + reg dirq, int; + + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + int <= #1 1'b0; + dirq <= #1 1'b0; + end + else if (rst_i) + begin + int <= #1 1'b0; + dirq <= #1 1'b0; + end + else + begin + int <= #1 (int | (irq & !dirq)) & !(sel_stat & !dat_i[0]); + dirq <= #1 irq; + end + + // assign status bits + assign StatReg[31:28] = DeviceId; // set Device ID + assign StatReg[27:24] = RevisionNo; // set revision number + assign StatReg[23:16] = 0; // reserved + assign StatReg[15] = DMAtip; + assign StatReg[14:11] = 0; + assign StatReg[10] = DMARxEmpty; + assign StatReg[9] = DMATxFull; + assign StatReg[8] = DMA_dmarq; + assign StatReg[7] = PIOtip; + assign StatReg[6] = PIOpp_full; + assign StatReg[5:1] = 0; // reserved + assign StatReg[0] = int; + + + // generate PIO compatible / command-port timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + PIO_cmdport_T1 <= #1 PIO_mode0_T1; + PIO_cmdport_T2 <= #1 PIO_mode0_T2; + PIO_cmdport_T4 <= #1 PIO_mode0_T4; + PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; + end + else if (rst_i) + begin + PIO_cmdport_T1 <= #1 PIO_mode0_T1; + PIO_cmdport_T2 <= #1 PIO_mode0_T2; + PIO_cmdport_T4 <= #1 PIO_mode0_T4; + PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc; + end + else if(sel_PIO_cmdport) + begin + PIO_cmdport_T1 <= #1 dat_i[ 7: 0]; + PIO_cmdport_T2 <= #1 dat_i[15: 8]; + PIO_cmdport_T4 <= #1 dat_i[23:16]; + PIO_cmdport_Teoc <= #1 dat_i[31:24]; + end + + // generate PIO device0 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + PIO_dport0_T1 <= #1 PIO_mode0_T1; + PIO_dport0_T2 <= #1 PIO_mode0_T2; + PIO_dport0_T4 <= #1 PIO_mode0_T4; + PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; + end + else if (rst_i) + begin + PIO_dport0_T1 <= #1 PIO_mode0_T1; + PIO_dport0_T2 <= #1 PIO_mode0_T2; + PIO_dport0_T4 <= #1 PIO_mode0_T4; + PIO_dport0_Teoc <= #1 PIO_mode0_Teoc; + end + else if(sel_PIO_dport0) + begin + PIO_dport0_T1 <= #1 dat_i[ 7: 0]; + PIO_dport0_T2 <= #1 dat_i[15: 8]; + PIO_dport0_T4 <= #1 dat_i[23:16]; + PIO_dport0_Teoc <= #1 dat_i[31:24]; + end + + // generate PIO device1 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + PIO_dport1_T1 <= #1 PIO_mode0_T1; + PIO_dport1_T2 <= #1 PIO_mode0_T2; + PIO_dport1_T4 <= #1 PIO_mode0_T4; + PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; + end + else if (rst_i) + begin + PIO_dport1_T1 <= #1 PIO_mode0_T1; + PIO_dport1_T2 <= #1 PIO_mode0_T2; + PIO_dport1_T4 <= #1 PIO_mode0_T4; + PIO_dport1_Teoc <= #1 PIO_mode0_Teoc; + end + else if(sel_PIO_dport1) + begin + PIO_dport1_T1 <= #1 dat_i[ 7: 0]; + PIO_dport1_T2 <= #1 dat_i[15: 8]; + PIO_dport1_T4 <= #1 dat_i[23:16]; + PIO_dport1_Teoc <= #1 dat_i[31:24]; + end + + // generate DMA device0 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + DMA_dev0_Tm <= #1 DMA_mode0_Tm; + DMA_dev0_Td <= #1 DMA_mode0_Td; + DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; + end + else if (rst_i) + begin + DMA_dev0_Tm <= #1 DMA_mode0_Tm; + DMA_dev0_Td <= #1 DMA_mode0_Td; + DMA_dev0_Teoc <= #1 DMA_mode0_Teoc; + end + else if(sel_DMA_dev0) + begin + DMA_dev0_Tm <= #1 dat_i[ 7: 0]; + DMA_dev0_Td <= #1 dat_i[15: 8]; + DMA_dev0_Teoc <= #1 dat_i[31:24]; + end + + // generate DMA device1 timing register + always@(posedge clk_i or negedge arst_i) + if (~arst_i) + begin + DMA_dev1_Tm <= #1 DMA_mode0_Tm; + DMA_dev1_Td <= #1 DMA_mode0_Td; + DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; + end + else if (rst_i) + begin + DMA_dev1_Tm <= #1 DMA_mode0_Tm; + DMA_dev1_Td <= #1 DMA_mode0_Td; + DMA_dev1_Teoc <= #1 DMA_mode0_Teoc; + end + else if(sel_DMA_dev1) + begin + DMA_dev1_Tm <= #1 dat_i[ 7: 0]; + DMA_dev1_Td <= #1 dat_i[15: 8]; + DMA_dev1_Teoc <= #1 dat_i[31:24]; + end + + // + // generate WISHBONE interconnect signals + // + reg [31:0] Q; + + // generate acknowledge signal + assign ack_o = PIOack | CONsel; // | DMAack; // since DMAack is derived from CONsel this is OK + + // generate error signal + assign err_o = cyc_i & stb_i & berr; + + // generate retry signal (for OCIDEC-3 and above only) + assign rty_o = cyc_i & stb_i & brty; + + // generate interrupt signal + assign inta_o = StatReg[0]; + + // generate output multiplexor + always@(`ATA_ADR or CtrlReg or StatReg or + PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc or + PIO_dport0_T1 or PIO_dport0_T2 or PIO_dport0_T4 or PIO_dport0_Teoc or + PIO_dport1_T1 or PIO_dport1_T2 or PIO_dport1_T4 or PIO_dport1_Teoc or + DMA_dev0_Tm or DMA_dev0_Td or DMA_dev0_Teoc or + DMA_dev1_Tm or DMA_dev1_Td or DMA_dev1_Teoc or + DMAq + ) + case (`ATA_ADR) // synopsis full_case parallel_case + `ATA_CTRL_REG: Q = CtrlReg; + `ATA_STAT_REG: Q = StatReg; + `ATA_PIO_CMD : Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1}; + `ATA_PIO_DP0 : Q = {PIO_dport0_Teoc, PIO_dport0_T4, PIO_dport0_T2, PIO_dport0_T1}; + `ATA_PIO_DP1 : Q = {PIO_dport1_Teoc, PIO_dport1_T4, PIO_dport1_T2, PIO_dport1_T1}; + `ATA_DMA_DEV0: Q = {DMA_dev0_Teoc, 8'h0, DMA_dev0_Td, DMA_dev0_Tm}; + `ATA_DMA_DEV1: Q = {DMA_dev1_Teoc, 8'h0, DMA_dev1_Td, DMA_dev1_Tm}; + `ATA_DMA_PORT: Q = DMAq; + default: Q = 0; + endcase + + // assign DAT_O output + assign dat_o = `ATA_DEV_ADR ? {16'h0, PIOq} : Q; + +endmodule + + Index: ata/trunk/rtl/verilog/ocidec-2/timescale.v =================================================================== --- ata/trunk/rtl/verilog/ocidec-2/timescale.v (nonexistent) +++ ata/trunk/rtl/verilog/ocidec-2/timescale.v (revision 33) @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + Index: ata/trunk/rtl/vhdl/ocidec1/atahost_controller.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/atahost_controller.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/atahost_controller.vhd (revision 33) @@ -0,0 +1,318 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller (OCIDEC-1) ---- +---- PIO Contoller ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 18th, 2001 +-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools +-- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0' +-- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device. +-- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). +-- +-- +-- CVS Log +-- +-- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:06:48 rherveille Exp $ +-- +-- $Date: 2002-05-19 06:06:48 $ +-- $Revision: 1.2 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + + +-- OCIDEC1 supports: +-- -Common Compatible timing access to all connected devices +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + irq : out std_logic; -- interrupt request signal + + -- control / registers + IDEctrl_rst, + IDEctrl_IDEen : in std_logic; + + -- PIO registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : in unsigned(7 downto 0); -- PIO command timing + PIO_cmdport_IORDYen : in std_logic; + + PIOreq : in std_logic; -- PIO transfer request + PIOack : buffer std_logic; -- PIO transfer ended + PIOa : in unsigned(3 downto 0); -- PIO address + PIOd : in std_logic_vector(15 downto 0); -- PIO data in + PIOq : out std_logic_vector(15 downto 0); -- PIO data out + PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read + + -- ATA signals + RESETn : out std_logic; + DDi : in std_logic_vector(15 downto 0); + DDo : out std_logic_vector(15 downto 0); + DDoe : out std_logic; + DA : out unsigned(2 downto 0); + CS0n : out std_logic; + CS1n : out std_logic; + + DIORn : out std_logic; + DIOWn : out std_logic; + IORDY : in std_logic; + INTRQ : in std_logic + ); +end entity atahost_controller; + +architecture structural of atahost_controller is + -- + -- Component declarations + -- + component atahost_pio_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing/control register settings + IORDY_en : in std_logic; -- use IORDY (or not) + T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) + T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) + T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- PIO controller selected (strobe signal) + we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device + + -- return signals + oe : buffer std_logic; -- output enable signal + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe, latch data (during read) + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic; -- IOwrite signal, active high + IORDY : in std_logic -- IORDY signal + ); + end component atahost_pio_tctrl; + + -- + -- signals + -- + signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller + signal PIOdone : std_logic; -- PIO timing controller done + + -- PIO signals + signal PIOdior, PIOdiow : std_logic; + signal PIOoe : std_logic; + + -- Timing settings + signal dstrb : std_logic; + signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0); + signal IORDYen : std_logic; + + -- synchronized ATA inputs + signal sIORDY : std_logic; + +begin + + -- + -- synchronize incoming signals + -- + synch_incoming: block + signal cIORDY : std_logic; -- capture IORDY + signal cINTRQ : std_logic; -- capture INTRQ + begin + process(clk) + begin + if (clk'event and clk = '1') then + cIORDY <= IORDY; + cINTRQ <= INTRQ; + + sIORDY <= cIORDY; + irq <= cINTRQ; + end if; + end process; + end block synch_incoming; + + -- + -- generate ATA signals + -- + gen_ata_sigs: block + begin + -- generate registers for ATA signals + gen_regs: process(clk, nReset) + begin + if (nReset = '0') then + RESETn <= '0'; + DIORn <= '1'; + DIOWn <= '1'; + DA <= (others => '0'); + CS0n <= '1'; + CS1n <= '1'; + DDo <= (others => '0'); + DDoe <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + RESETn <= '0'; + DIORn <= '1'; + DIOWn <= '1'; + DA <= (others => '0'); + CS0n <= '1'; + CS1n <= '1'; + DDo <= (others => '0'); + DDoe <= '0'; + else + RESETn <= not IDEctrl_rst; + DA <= PIOa(2 downto 0); + CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0' + CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1' + + DDo <= PIOd; + DDoe <= PIOoe; + DIORn <= not PIOdior; + DIOWn <= not PIOdiow; + end if; + end if; + end process gen_regs; + end block gen_ata_sigs; + + + -- + -------------------------- + -- PIO transfer control -- + -------------------------- + -- + -- capture ATA data for PIO access + gen_PIOq: process(clk) + begin + if (clk'event and clk = '1') then + if (dstrb = '1') then + PIOq <= DDi; + end if; + end if; + end process gen_PIOq; + + -- generate PIOgo signal + gen_PIOgo: process(clk, nReset) + begin + if (nReset = '0') then + dPIOreq <= '0'; + PIOgo <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + dPIOreq <= '0'; + PIOgo <= '0'; + else + dPIOreq <= PIOreq and not PIOack; + PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen; + end if; + end + end process gen_PIOgo; + + -- set Timing signals + T1 <= PIO_cmdport_T1; + T2 <= PIO_cmdport_T2; + T4 <= PIO_cmdport_T4; + Teoc <= PIO_cmdport_Teoc; + IORDYen <= PIO_cmdport_IORDYen; + + -- + -- hookup timing controller + -- + PIO_timing_controller: atahost_pio_tctrl + generic map ( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + IORDY_en => IORDYen, + T1 => T1, + T2 => T2, + T4 => T4, + Teoc => Teoc, + go => PIOgo, + we => PIOwe, + oe => PIOoe, + done => PIOdone, + dstrb => dstrb, + DIOR => PIOdior, + DIOW => PIOdiow, + IORDY => sIORDY + ); + + -- generate acknowledge + gen_ack: process(clk) + begin + if (clk'event and clk = '1') then + PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request) + end if; + end process gen_ack; +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec1/revision_history.txt =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/revision_history.txt (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/revision_history.txt (revision 33) @@ -0,0 +1,77 @@ +----------------------------- +Revision: 1.0 +Date: march 22nd, 2001 +Author: Richard Herveille +- initial release +----------------------------- + +----------------------------- +Revision: 1.0a +Date: april 12th, 2001 +Author: Richard Herveille +- removed records.vhd +- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools +- fixed a minor bug where core didn't respond to IDEen bit. +----------------------------- + +----------------------------- +Revision: 1.1 +Date: June 18th, 2001 +Author: Richard Herveille +- Changed PIOack generation. Avoid asserting PIOack continuosly when IDEen = '0' +- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) +----------------------------- + + +----------------------------- +Revision: 1.1a +Date: June 19th, 2001 +Author: Richard Herveille +- Missed a reference to ADR_I(4). Simplified DAT_O output multiplexor. +----------------------------- + +----------------------------- +Revision: 1.2 +Date: June 26th, 2001 +Author: Richard Herveille +- Changed dPIOreq generation (controller.vhd). Wishbone burst accesses to ata device were not handled correctly +- Change PIOack from "out" to "buffer" (controller.vhd + ata.vhd) +----------------------------- + +----------------------------- +Revision: 1.3 +Date: July 11th, 2001 +Author: Richard Herveille +- renamed 'ata.vhd' to 'atahost.vhd' +- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous +- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). +----------------------------- + +----------------------------- +Revision: 1.4 +Date: Februar 17th, 2002 +Author: Richard Herveille +- renamed 'atahost.vhd' to 'atahost_top.vhd' +- renamed 'controller.vhd' to 'atahost_controller.vhd' +- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' +- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' +- changed resD input to generic RESD in ud_cnt.vhd +- changed ID input to generic ID in ro_cnt.vhd +- changed core to reflect changes in ro_cnt.vhd +- removed references to 'count' library +- changed IO names +- added disclaimer +- added CVS log +- moved registers and wishbone signals into 'atahost_wb_slave.vhd' +- core is now equivalent to verilog version +----------------------------- + + +----------------------------- +Revision: 1.5 +Date: May 19th, 2002. +Author: Richard Herveille +- Fixed a potential bug that forced the core into an unknown state + when an asynchronous reset was given without a running clock +----------------------------- + Index: ata/trunk/rtl/vhdl/ocidec1/ro_cnt.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/ro_cnt.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/ro_cnt.vhd (revision 33) @@ -0,0 +1,131 @@ +--------------------------------------------------------------------- +---- ---- +---- Run-Once Counter ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:48:22 rherveille Exp $ +-- +-- $Date: 2002-03-01 03:48:22 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); +end entity ro_cnt; + +architecture structural of ro_cnt is + component ud_cnt is + generic( + SIZE : natural := 8; + RESD : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0); -- current counter value + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); + end component ud_cnt; + + signal rci, rco, nld : std_logic; +begin + gen_ctrl: process(clk, nReset) + begin + if (nReset = '0') then + rci <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + rci <= '0'; + else + rci <= go or (rci and not rco); + end if; + end if; + end process; + + nld <= not go; + + -- hookup counter + cnt : ud_cnt + generic map ( + SIZE => SIZE, + RESD => ID + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + cnt_en => cnt_en, + ud => UD, + nld => nld, + D => D, + Q => Q, + rci => rci, + rco => rco + ); + + done <= rco; +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec1/ud_cnt.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/ud_cnt.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/ud_cnt.vhd (revision 33) @@ -0,0 +1,102 @@ +--------------------------------------------------------------------- +---- ---- +---- Generic Up/Down counter (ripple carry architecture) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: ud_cnt.vhd,v 1.1 2002-03-01 03:48:22 rherveille Exp $ +-- +-- $Date: 2002-03-01 03:48:22 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ud_cnt is + generic( + SIZE : natural := 8; + RESD : natural := 0 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0); -- current counter value + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); +end entity ud_cnt; + +architecture structural of ud_cnt is + signal Qi : unsigned(SIZE -1 downto 0); + signal val : unsigned(SIZE downto 0); +begin + val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); + + regs: process(clk, nReset) + begin + if (nReset = '0') then + Qi <= conv_unsigned(RESD, SIZE); + elsif (clk'event and clk = '1') then + if (rst = '1') then + Qi <= conv_unsigned(RESD, SIZE); + else + if (nld = '0') then + Qi <= D; + elsif (cnt_en = '1') then + Qi <= val(SIZE -1 downto 0); + end if; + end if; + end if; + end process regs; + + -- assign outputs + Q <= Qi; + rco <= val(SIZE); +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd (revision 33) @@ -0,0 +1,285 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores ATA/ATAPI-5 Host Controller ---- +---- PIO Timing Controller (common for all OCIDEC cores) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 7th, 2001. Initial release +-- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation. +-- +-- +-- CVS Log +-- +-- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:29:38 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- +-- + +-- +--------------------------- +-- PIO Timing controller -- +--------------------------- +-- + +-- +-- Timing PIO mode transfers +---------------------------------------------- +-- T0: cycle time +-- T1: address valid to DIOR-/DIOW- +-- T2: DIOR-/DIOW- pulse width +-- T2i: DIOR-/DIOW- recovery time +-- T3: DIOW- data setup +-- T4: DIOW- data hold +-- T5: DIOR- data setup +-- T6: DIOR- data hold +-- T9: address hold from DIOR-/DIOW- negated +-- Trd: Read data valid to IORDY asserted +-- Ta: IORDY setup time +-- Tb: IORDY pulse width +-- +-- Transfer sequence +---------------------------------- +-- 1) set address (DA, CS0-, CS1-) +-- 2) wait for T1 +-- 3) assert DIOR-/DIOW- +-- when write action present Data (timing spec. T3 always honored), enable output enable-signal +-- 4) wait for T2 +-- 5) check IORDY +-- when not IORDY goto 5 +-- when IORDY negate DIOW-/DIOR-, latch data (if read action) +-- when write, hold data for T4, disable output-enable signal +-- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest +-- 7) start new cycle + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_pio_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing/control register settings + IORDY_en : in std_logic; -- use IORDY (or not) + T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) + T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) + T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- PIO controller selected (strobe signal) + we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device + + -- return signals + oe : buffer std_logic; -- output enable signal + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe, latch data (during read) + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic; -- IOwrite signal, active high + IORDY : in std_logic -- IORDY signal + ); +end entity atahost_pio_tctrl; + +architecture structural of atahost_pio_tctrl is + component ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); + end component ro_cnt; + + signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic; + signal busy, hold_go, igo, hT2done : std_logic; +begin + -- generate internal go strobe + -- strecht go until ready for new cycle + process(clk, nReset) + begin + if (nReset = '0') then + busy <= '0'; + hold_go <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + busy <= '0'; + hold_go <= '0'; + else + busy <= (igo or busy) and not Teoc_done; + hold_go <= (go or (hold_go and busy)) and not igo; + end if; + end if; + end process; + igo <= (go or hold_go) and not busy; + + -- 1) hookup T1 counter + t1_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T1 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => igo, + D => T1, + done => T1done + ); + + -- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device + T2proc: process(clk, nReset) + begin + if (nReset = '0') then + DIOR <= '0'; + DIOW <= '0'; + oe <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + DIOR <= '0'; + DIOW <= '0'; + oe <= '0'; + else + DIOR <= (not we and T1done) or (DIOR and not IORDY_done); + DIOW <= ( we and T1done) or (DIOW and not IORDY_done); + oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done + end if; + end if; + end process T2proc; + + -- 3) hookup T2 counter + t2_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T2 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => T1done, + D => T2, + done => T2done + ); + + -- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) + -- hold T2done + gen_hT2done: process(clk, nReset) + begin + if (nReset = '0') then + hT2done <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + hT2done <= '0'; + else + hT2done <= (T2done or hT2done) and not IORDY_done; + end if; + end if; + end process gen_hT2done; + IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en); + + -- generate datastrobe, capture data at rising DIOR- edge + gen_dstrb: process(clk) + begin + if (clk'event and clk = '1') then + dstrb <= IORDY_done; + end if; + end process gen_dstrb; + + -- hookup data hold counter + dhold_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T4 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => IORDY_done, + D => T4, + done => T4done + ); + done <= T4done; -- placing done here provides the fastest return possible, + -- while still guaranteeing data and address hold-times + + -- 5) hookup end_of_cycle counter + eoc_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => IORDY_done, + D => Teoc, + done => Teoc_done + ); + +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec1/atahost_top.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/atahost_top.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/atahost_top.vhd (revision 33) @@ -0,0 +1,426 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ATA/ATAPI-5 (OCIDEC-1) ---- +---- Top Level ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 22nd, 2001. Initial release +-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools +-- rev.: 1.1 june 18th, 2001. Changed wishbone address-input from (A4..A0) to (A6..A2) +-- rev.: 1.1a june 19th, 2001. Missed a reference to ADR_I(4). Simplified DAT_O output multiplexor. +-- +-- +-- CVS Log +-- +-- $Id: atahost_top.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:29:38 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- +-- +-- + +-- DeviceType: OCIDEC-1: OpenCores IDE Controller type1 +-- Features: PIO Compatible Timing +-- DeviceID: 0x01 +-- RevNo : 0x00 + +-- +-- Host signals: +-- Reset +-- DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. +-- DIOW- write strobe. The rising edge latches data from DD into the device. +-- DA(2:0) 3bit binary coded adress +-- CS0- select command block registers +-- CS1- select control block registers + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_top is + generic( + ARST_LVL : std_logic := '0'; -- asynchronous reset level + + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + -- WISHBONE SYSCON signals + wb_clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + wb_cyc_i : in std_logic; -- valid bus cycle input + wb_stb_i : in std_logic; -- strobe/core select input + wb_ack_o : out std_logic; -- strobe acknowledge output + wb_err_o : out std_logic; -- error output + wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in + wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out + wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + wb_we_i : in std_logic; -- Write enable input + wb_inta_o : out std_logic; -- interrupt request signal IDE0 + + -- ATA signals + resetn_pad_o : out std_logic; + dd_pad_i : in std_logic_vector(15 downto 0); + dd_pad_o : out std_logic_vector(15 downto 0); + dd_padoe_o : out std_logic; + da_pad_o : out unsigned(2 downto 0); + cs0n_pad_o : out std_logic; + cs1n_pad_o : out std_logic; + + diorn_pad_o : out std_logic; + diown_pad_o : out std_logic; + iordy_pad_i : in std_logic; + intrq_pad_i : in std_logic + ); +end entity atahost_top; + +architecture structural of atahost_top is + -- + -- constants + -- + + -- Device ID + constant DeviceId : unsigned(3 downto 0) := x"1"; + constant RevisionNo : unsigned(3 downto 0) := x"0"; + + -- + -- component declarations + -- + component atahost_wb_slave is + generic( + DeviceID : unsigned(3 downto 0) := x"0"; + RevisionNo : unsigned(3 downto 0) := x"0"; + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + cyc_i : in std_logic; -- valid bus cycle input + stb_i : in std_logic; -- strobe/core select input + ack_o : out std_logic; -- strobe acknowledge output + rty_o : out std_logic; -- retry output + err_o : out std_logic; -- error output + adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + dat_i : in std_logic_vector(31 downto 0); -- Databus in + dat_o : out std_logic_vector(31 downto 0); -- Databus out + sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + we_i : in std_logic; -- Write enable input + inta_o : out std_logic; -- interrupt request signal IDE0 + + -- PIO control input + PIOsel : buffer std_logic; + PIOtip, -- PIO transfer in progress + PIOack : in std_logic; -- PIO acknowledge signal + PIOq : in std_logic_vector(15 downto 0); -- PIO data input + PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full + irq : in std_logic; -- interrupt signal input + + -- DMA control inputs + DMAsel : out std_logic; + DMAtip, -- DMA transfer in progress + DMAack, -- DMA transfer acknowledge + DMARxEmpty, -- DMA receive buffer empty + DMATxFull, -- DMA transmit buffer full + DMA_dmarq : in std_logic; -- wishbone DMA request + DMAq : in std_logic_vector(31 downto 0); + + -- outputs + -- control register outputs + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR1, + IDEctrl_FATR0, + IDEctrl_ppen, + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : out std_logic; + + -- CMD port timing registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : buffer unsigned(7 downto 0); + PIO_cmdport_IORDYen : out std_logic; + + -- data-port0 timing registers + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : buffer unsigned(7 downto 0); + PIO_dport0_IORDYen : out std_logic; + + -- data-port1 timing registers + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : buffer unsigned(7 downto 0); + PIO_dport1_IORDYen : out std_logic; + + -- DMA device0 timing registers + DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc : buffer unsigned(7 downto 0); + + -- DMA device1 timing registers + DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc : buffer unsigned(7 downto 0) + ); + end component atahost_wb_slave; + + + component atahost_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + irq : out std_logic; -- interrupt request signal + + -- control / registers + IDEctrl_rst, + IDEctrl_IDEen : in std_logic; + + -- PIO registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : in unsigned(7 downto 0); -- PIO command timing + PIO_cmdport_IORDYen : in std_logic; + + PIOreq : in std_logic; -- PIO transfer request + PIOack : buffer std_logic; -- PIO transfer ended + PIOa : in unsigned(3 downto 0); -- PIO address + PIOd : in std_logic_vector(15 downto 0); -- PIO data in + PIOq : out std_logic_vector(15 downto 0); -- PIO data out + PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read + + -- ATA signals + RESETn : out std_logic; + DDi : in std_logic_vector(15 downto 0); + DDo : out std_logic_vector(15 downto 0); + DDoe : out std_logic; + DA : out unsigned(2 downto 0); + CS0n : out std_logic; + CS1n : out std_logic; + + DIORn : out std_logic; + DIOWn : out std_logic; + IORDY : in std_logic; + INTRQ : in std_logic + ); + end component atahost_controller; + + -- asynchronous reset signal + signal arst_signal : std_logic; + + -- primary address decoder + signal PIOsel : std_logic; -- controller select, IDE devices select + + -- registers + signal IDEctrl_IDEen, IDEctrl_rst: std_logic; + signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0); + signal PIO_cmdport_IORDYen : std_logic; + signal PIOack : std_logic; + signal PIOq : std_logic_vector(15 downto 0); + + signal irq : std_logic; -- ATA bus IRQ signal + +begin + -- generate asynchronous reset level + arst_signal <= arst_i xor ARST_LVL; + + -- + -- hookup wishbone slave + -- + u0: atahost_wb_slave + generic map( + DeviceID => DeviceID, + RevisionNo => RevisionNo, + + -- PIO mode 0 settings + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc, + + -- Multiword DMA mode 0 settings + -- OCIDEC-1 does not support DMA, set registers to zero + DMA_mode0_Tm => 0, + DMA_mode0_Td => 0, + DMA_mode0_Teoc => 0 + ) + port map( + -- WISHBONE SYSCON signals + clk_i => wb_clk_i, + arst_i => arst_signal, + rst_i => wb_rst_i, + + -- WISHBONE SLAVE signals + cyc_i => wb_cyc_i, + stb_i => wb_stb_i, + ack_o => wb_ack_o, + err_o => wb_err_o, + adr_i => wb_adr_i, + dat_i => wb_dat_i, + dat_o => wb_dat_o, + sel_i => wb_sel_i, + we_i => wb_we_i, + inta_o => wb_inta_o, + + -- PIO control input + -- PIOtip is only asserted during a PIO transfer (No shit! ;) + -- Since it is impossible to read the status register and access the PIO registers at the same time + -- this bit is useless (besides using-up resources) + PIOtip => '0', + PIOack => PIOack, + PIOq => PIOq, + PIOsel => PIOsel, + PIOpp_full => '0', -- OCIDEC-1 does not support PIO-write PingPong, negate signal + irq => irq, + + -- DMA control inputs (negate all of them) + DMAtip => '0', + DMAack => '0', + DMARxEmpty => '0', + DMATxFull => '0', + DMA_dmarq => '0', + DMAq => x"00000000", + + -- outputs + -- control register outputs + IDEctrl_rst => IDEctrl_rst, + IDEctrl_IDEen => IDEctrl_IDEen, + + -- CMD port timing registers + PIO_cmdport_T1 => PIO_cmdport_T1, + PIO_cmdport_T2 => PIO_cmdport_T2, + PIO_cmdport_T4 => PIO_cmdport_T4, + PIO_cmdport_Teoc => PIO_cmdport_Teoc, + PIO_cmdport_IORDYen => PIO_cmdport_IORDYen + ); + + -- + -- hookup controller section + -- + u1: atahost_controller + generic map( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map( + clk => wb_clk_i, + nReset => arst_signal, + rst => wb_rst_i, + irq => irq, + IDEctrl_rst => IDEctrl_rst, + IDEctrl_IDEen => IDEctrl_IDEen, + PIO_cmdport_T1 => PIO_cmdport_T1, + PIO_cmdport_T2 => PIO_cmdport_T2, + PIO_cmdport_T4 => PIO_cmdport_T4, + PIO_cmdport_Teoc => PIO_cmdport_Teoc, + PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, + PIOreq => PIOsel, + PIOack => PIOack, + PIOa => wb_adr_i(5 downto 2), + PIOd => wb_dat_i(15 downto 0), + PIOq => PIOq, + PIOwe => wb_we_i, + RESETn => resetn_pad_o, + DDi => dd_pad_i, + DDo => dd_pad_o, + DDoe => dd_padoe_o, + DA => da_pad_o, + CS0n => cs0n_pad_o, + CS1n => cs1n_pad_o, + DIORn => diorn_pad_o, + DIOWn => diown_pad_o, + IORDY => iordy_pad_i, + INTRQ => intrq_pad_i + ); + +end architecture structural; + + + + + + Index: ata/trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd (revision 33) @@ -0,0 +1,467 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- Wishbone Slave (common for all OCIDEC cores) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:29:38 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:29:38 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_wb_slave is + generic( + DeviceID : unsigned(3 downto 0) := x"0"; + RevisionNo : unsigned(3 downto 0) := x"0"; + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + cyc_i : in std_logic; -- valid bus cycle input + stb_i : in std_logic; -- strobe/core select input + ack_o : out std_logic; -- strobe acknowledge output + rty_o : out std_logic; -- retry output + err_o : out std_logic; -- error output + adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + dat_i : in std_logic_vector(31 downto 0); -- Databus in + dat_o : out std_logic_vector(31 downto 0); -- Databus out + sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + we_i : in std_logic; -- Write enable input + inta_o : out std_logic; -- interrupt request signal IDE0 + + -- PIO control input + PIOsel : buffer std_logic; + PIOtip, -- PIO transfer in progress + PIOack : in std_logic; -- PIO acknowledge signal + PIOq : in std_logic_vector(15 downto 0); -- PIO data input + PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full + irq : in std_logic; -- interrupt signal input + + -- DMA control inputs + DMAsel : out std_logic; + DMAtip, -- DMA transfer in progress + DMAack, -- DMA transfer acknowledge + DMARxEmpty, -- DMA receive buffer empty + DMATxFull, -- DMA transmit buffer full + DMA_dmarq : in std_logic; -- wishbone DMA request + DMAq : in std_logic_vector(31 downto 0); + + -- outputs + -- control register outputs + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR1, + IDEctrl_FATR0, + IDEctrl_ppen, + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : out std_logic; + + -- CMD port timing registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : buffer unsigned(7 downto 0); + PIO_cmdport_IORDYen : out std_logic; + + -- data-port0 timing registers + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : buffer unsigned(7 downto 0); + PIO_dport0_IORDYen : out std_logic; + + -- data-port1 timing registers + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : buffer unsigned(7 downto 0); + PIO_dport1_IORDYen : out std_logic; + + -- DMA device0 timing registers + DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc : buffer unsigned(7 downto 0); + + -- DMA device1 timing registers + DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc : buffer unsigned(7 downto 0) + ); +end entity atahost_wb_slave; + +architecture structural of atahost_wb_slave is + -- + -- constants + -- + + -- addresses + alias ATA_DEV_ADR : std_logic is adr_i(6); + alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2); + + constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000"; + constant ATA_STAT_REG : unsigned(3 downto 0) := "0001"; + constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010"; + constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011"; + constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100"; + constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101"; + constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110"; + -- reserved -- + constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111"; + + -- + -- function declarations + -- + -- overload '=' to compare two unsigned numbers + function "=" (a, b : unsigned) return std_logic is + alias la: unsigned(1 to a'length) is a; + alias lb: unsigned(1 to b'length) is b; + variable result : std_logic; + begin + -- check vector length + assert a'length = b'length + report "std_logic_vector comparison: operands of unequal lengths" + severity FAILURE; + + result := '1'; + for n in 1 to a'length loop + result := result and not (la(n) xor lb(n)); + end loop; + + return result; + end; + + -- primary address decoder + signal CONsel : std_logic; -- controller select, IDE devices select + signal berr, brty : std_logic; -- bus error, bus retry + + -- registers + signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers + +begin + -- + -- generate bus cycle / address decoder + -- + gen_bc_dec: block + signal w_acc, dw_acc : std_logic; -- word access, double word access + signal store_pp_full : std_logic; + begin + -- word / double word + w_acc <= sel_i(1) and sel_i(0); + dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0); + + -- bus error + berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc; + + -- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full + PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full); + + -- CON accesses only 32bit wide + CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc; + DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT); + + -- bus retry (OCIDEC-3 and above) + -- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle + process(clk_i) + begin + if (clk_i'event and clk_i = '1') then + if (PIOsel = '0') then + store_pp_full <= PIOpp_full; + end if; + end if; + end process; + brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full); + end block gen_bc_dec; + + -- + -- generate registers + -- + register_block : block + signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers + signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers + signal sel_ctrl, sel_stat : std_logic; -- control / status register + begin + -- generate register select signals + sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG); + sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG); + sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD); + sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0); + sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1); + sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0); + sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1); + -- reserved 0x1C-0x38 -- + -- reserved 0x3C : DMA port -- + + -- generate control register + gen_ctrl_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + CtrlReg(31 downto 1) <= (others => '0'); + CtrlReg(0) <= '1'; -- set reset bit + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + CtrlReg(31 downto 1) <= (others => '0'); + CtrlReg(0) <= '1'; -- set reset bit + elsif (sel_ctrl = '1') then + CtrlReg <= dat_i; + end if; + end if; + end process gen_ctrl_reg; + -- assign bits + DMActrl_DMAen <= CtrlReg(15); + DMActrl_dir <= CtrlReg(13); + DMActrl_BeLeC1 <= CtrlReg(9); + DMActrl_BeLeC0 <= CtrlReg(8); + IDEctrl_IDEen <= CtrlReg(7); + IDEctrl_FATR1 <= CtrlReg(6); + IDEctrl_FATR0 <= CtrlReg(5); + IDEctrl_ppen <= CtrlReg(4); + PIO_dport1_IORDYen <= CtrlReg(3); + PIO_dport0_IORDYen <= CtrlReg(2); + PIO_cmdport_IORDYen <= CtrlReg(1); + IDEctrl_rst <= CtrlReg(0); + + -- generate status register clearable bits + gen_stat_reg: block + signal dirq, int : std_logic; + begin + gen_irq: process(clk_i, arst_i) + begin + if (arst_i = '0') then + int <= '0'; + dirq <= '0'; + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + int <= '0'; + dirq <= '0'; + else + int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0)); + dirq <= irq; + end if; + end if; + end process gen_irq; + + gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full) + begin + StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0') + + StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID + StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number + StatReg(15) <= DMAtip; + StatReg(10) <= DMARxEmpty; + StatReg(9) <= DMATxFull; + StatReg(8) <= DMA_dmarq; + StatReg(7) <= PIOtip; + StatReg(6) <= PIOpp_full; + StatReg(0) <= int; + end process; + end block gen_stat_reg; + + -- generate PIO compatible / command-port timing register + gen_PIO_cmdport_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_cmdport = '1') then + PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8)); + PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16)); + PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_cmdport_reg; + + -- generate PIO device0 timing register + gen_PIO_dport0_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_dport0 = '1') then + PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_dport0_T2 <= unsigned(dat_i(15 downto 8)); + PIO_dport0_T4 <= unsigned(dat_i(23 downto 16)); + PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_dport0_reg; + + -- generate PIO device1 timing register + gen_PIO_dport1_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_dport1 = '1') then + PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_dport1_T2 <= unsigned(dat_i(15 downto 8)); + PIO_dport1_T4 <= unsigned(dat_i(23 downto 16)); + PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_dport1_reg; + + -- generate DMA device0 timing register + gen_DMA_dev0_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (sel_DMA_dev0 = '1') then + DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0)); + DMA_dev0_Td <= unsigned(dat_i(15 downto 8)); + DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_DMA_dev0_reg; + + -- generate DMA device1 timing register + gen_DMA_dev1_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (sel_DMA_dev1 = '1') then + DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0)); + DMA_dev1_Td <= unsigned(dat_i(15 downto 8)); + DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_DMA_dev1_reg; + + end block register_block; + + -- + -- generate WISHBONE interconnect signals + -- + gen_WB_sigs: block + signal Q : std_logic_vector(31 downto 0); + begin + -- generate acknowledge signal + ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK + + -- generate error signal + err_o <= cyc_i and stb_i and berr; + + -- generate retry signal + rty_o <= cyc_i and stb_i and brty; + + -- assign interrupt signal + inta_o <= StatReg(0); + + -- generate output multiplexor + with ATA_ADR select + Q <= CtrlReg when ATA_CTRL_REG, -- control register + StatReg when ATA_STAT_REG, -- status register + std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register + std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0 + std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1 + std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0 + std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1 + DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register + (others => '0') when others; + + dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q; + end block gen_WB_sigs; + +end architecture structural; \ No newline at end of file Index: ata/trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd (revision 33) @@ -0,0 +1,252 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- PIO Access Controller (common for OCIDEC 2 and above) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws --- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 9th, 2001 +-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd +-- +-- +-- CVS Log +-- +-- $Id: atahost_pio_actrl.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $ +-- +-- $Date: 2002-05-19 06:07:09 $ +-- $Revision: 1.2 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + +-- +--------------------------- +-- PIO Access controller -- +--------------------------- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_pio_actrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + SelDev : in std_logic; -- Selected device + + go : in std_logic; -- Start transfer sequence + done : out std_logic; -- Transfer sequence done + dir : in std_logic; -- Transfer direction '1'=write, '0'=read + a : in unsigned(3 downto 0); -- PIO transfer address + q : out std_logic_vector(15 downto 0); -- Data read from ATA devices + + DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus + oe : buffer std_logic; -- DDbus output-enable signal + + DIOR, + DIOW : buffer std_logic; + IORDY : in std_logic + ); +end entity atahost_pio_actrl; + +architecture structural of atahost_pio_actrl is + -- + -- Component declarations + -- + component atahost_pio_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing/control register settings + IORDY_en : in std_logic; -- use IORDY (or not) + T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) + T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) + T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- PIO controller selected (strobe signal) + we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device + + -- return signals + oe : buffer std_logic; -- output enable signal + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe, latch data (during read) + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic; -- IOwrite signal, active high + IORDY : in std_logic -- IORDY signal + ); + end component atahost_pio_tctrl; + + signal dstrb : std_logic; + signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0); + signal IORDYen : std_logic; + +begin + -- + -------------------------- + -- PIO transfer control -- + -------------------------- + -- + -- capture ATA data for PIO access + gen_PIOq: process(clk) + begin + if (clk'event and clk = '1') then + if (dstrb = '1') then + q <= DDi; + end if; + end if; + end process gen_PIOq; + + -- + -- PIO timing controllers + -- + + -- select timing settings for the addressed port + sel_port_t: process(clk) + variable Asel : std_logic; -- address selected + variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0); + variable iIORDYen : std_logic; + begin + -- initially set timing registers to compatible timing + iT1 := cmdport_T1; + iT2 := cmdport_T2; + iT4 := cmdport_T4; + iTeoc := cmdport_Teoc; + iIORDYen := cmdport_IORDYen; + + -- detect data-port access + Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port + if (Asel = '1') then -- data port selected, 16bit transfers + if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ? + iT1 := dport1_T1; + iT2 := dport1_T2; + iT4 := dport1_T4; + iTeoc := dport1_Teoc; + iIORDYen := dport1_IORDYen; + elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ? + iT1 := dport0_T1; + iT2 := dport0_T2; + iT4 := dport0_T4; + iTeoc := dport0_Teoc; + iIORDYen := dport0_IORDYen; + end if; + end if; + + if (clk'event and clk = '1') then + T1 <= iT1; + T2 <= iT2; + T4 <= iT4; + Teoc <= iTeoc; + IORDYen <= iIORDYen; + end if; + end process sel_port_t; + + -- + -- hookup timing controller + -- + PIO_timing_controller: atahost_pio_tctrl + generic map ( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + IORDY_en => IORDYen, + T1 => T1, + T2 => T2, + T4 => T4, + Teoc => Teoc, + go => go, + we => dir, + oe => oe, + done => done, + dstrb => dstrb, + DIOR => dior, + DIOW => diow, + IORDY => IORDY + ); +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec2/atahost_controller.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/atahost_controller.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/atahost_controller.vhd (revision 33) @@ -0,0 +1,350 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- ATA/ATAPI-5 Controller (OCIDEC-2) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 18th, 2001. Initial release +-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd +-- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0' +-- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device. +-- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). +-- +-- CVS Log +-- +-- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:07:09 rherveille Exp $ +-- +-- $Date: 2002-05-19 06:07:09 $ +-- $Revision: 1.2 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +-- +-- OCIDEC2 supports: +-- -Common Compatible timing access to all connected devices +-- -Separate timing accesses to data port +-- -No DMA support + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + irq : out std_logic; -- interrupt request signal + + -- control / registers + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + -- PIO registers + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + PIOreq : in std_logic; -- PIO transfer request + PIOack : buffer std_logic; -- PIO transfer ended + PIOa : in unsigned(3 downto 0); -- PIO address + PIOd : in std_logic_vector(15 downto 0); -- PIO data in + PIOq : out std_logic_vector(15 downto 0); -- PIO data out + PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read + + -- ATA signals + RESETn : out std_logic; + DDi : in std_logic_vector(15 downto 0); + DDo : out std_logic_vector(15 downto 0); + DDoe : out std_logic; + DA : out unsigned(2 downto 0); + CS0n : out std_logic; + CS1n : out std_logic; + + DIORn : out std_logic; + DIOWn : out std_logic; + IORDY : in std_logic; + INTRQ : in std_logic + ); +end entity atahost_controller; + +architecture structural of atahost_controller is + -- + -- component declarations + -- + component atahost_pio_actrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + SelDev : in std_logic; -- Selected device + + go : in std_logic; -- Start transfer sequence + done : out std_logic; -- Transfer sequence done + dir : in std_logic; -- Transfer direction '1'=write, '0'=read + a : in unsigned(3 downto 0); -- PIO transfer address + q : out std_logic_vector(15 downto 0); -- Data read from ATA devices + + DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus + oe : buffer std_logic; -- DDbus output-enable signal + + DIOR, + DIOW : buffer std_logic; + IORDY : in std_logic + ); + end component atahost_pio_actrl; + + -- + -- signals + -- + signal SelDev : std_logic; -- selected device + + signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller + signal PIOdone : std_logic; -- PIO timing controller done + + -- PIO signals + signal PIOdior, PIOdiow : std_logic; + signal PIOoe : std_logic; + + -- synchronized ATA inputs + signal sIORDY : std_logic; + +begin + + -- + -- synchronize incoming signals + -- + synch_incoming: block + signal cIORDY : std_logic; -- capture IORDY + signal cINTRQ : std_logic; -- capture INTRQ + begin + process(clk) + begin + if (clk'event and clk = '1') then + cIORDY <= IORDY; + cINTRQ <= INTRQ; + + sIORDY <= cIORDY; + irq <= cINTRQ; + end if; + end process; + end block synch_incoming; + + -- + -- generate ATA signals + -- + gen_ata_sigs: block + begin + -- generate registers for ATA signals + gen_regs: process(clk, nReset) + begin + if (nReset = '0') then + RESETn <= '0'; + DIORn <= '1'; + DIOWn <= '1'; + DA <= (others => '0'); + CS0n <= '1'; + CS1n <= '1'; + DDo <= (others => '0'); + DDoe <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + RESETn <= '0'; + DIORn <= '1'; + DIOWn <= '1'; + DA <= (others => '0'); + CS0n <= '1'; + CS1n <= '1'; + DDo <= (others => '0'); + DDoe <= '0'; + else + RESETn <= not IDEctrl_rst; + DA <= PIOa(2 downto 0); + CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0' + CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1' + + DDo <= PIOd; + DDoe <= PIOoe; + DIORn <= not PIOdior; + DIOWn <= not PIOdiow; + end if; + end if; + end process gen_regs; + end block gen_ata_sigs; + + -- + -- generate selected device + -- + gen_seldev: process(clk) + variable Asel : std_logic; -- address selected + begin + Asel := not PIOa(3) and PIOa(2) and PIOa(1) and not PIOa(0); -- header/device register + + if (clk'event and clk = '1') then + if ( (PIOdone = '1') and (Asel = '1') and (PIOwe = '1') ) then + SelDev <= PIOd(4); + end if; + end if; + end process gen_seldev; + + -- generate PIOgo signal + gen_PIOgo: process(clk, nReset) + begin + if (nReset = '0') then + dPIOreq <= '0'; + PIOgo <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + dPIOreq <= '0'; + PIOgo <= '0'; + else + dPIOreq <= PIOreq and not PIOack; + PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen; + end if; + end + end process gen_PIOgo; + -- + -- Hookup PIO access controller + -- + PIO_access_control: atahost_pio_actrl + generic map( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map( + clk => clk, + nReset => nReset, + rst => rst, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + cmdport_T1 => cmdport_T1, + cmdport_T2 => cmdport_T2, + cmdport_T4 => cmdport_T4, + cmdport_Teoc => cmdport_Teoc, + cmdport_IORDYen => cmdport_IORDYen, + dport0_T1 => dport0_T1, + dport0_T2 => dport0_T2, + dport0_T4 => dport0_T4, + dport0_Teoc => dport0_Teoc, + dport0_IORDYen => dport0_IORDYen, + dport1_T1 => dport1_T1, + dport1_T2 => dport1_T2, + dport1_T4 => dport1_T4, + dport1_Teoc => dport1_Teoc, + dport1_IORDYen => dport1_IORDYen, + SelDev => SelDev, + go => PIOgo, + done => PIOdone, + dir => PIOwe, + a => PIOa, + q => PIOq, + DDi => DDi, + oe => PIOoe, + DIOR => PIOdior, + DIOW => PIOdiow, + IORDY => sIORDY + ); + + -- generate acknowledge + gen_ack: process(clk) + begin + if (clk'event and clk = '1') the + PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request) + end if; + end process gen_ack; +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec2/revision_history.txt =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/revision_history.txt (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/revision_history.txt (revision 33) @@ -0,0 +1,74 @@ +----------------------------- +Revision: 1.0 +Date: march 22nd, 2001 +Author: Richard Herveille +- initial release +----------------------------- + +----------------------------- +Revision: 1.0a +Date: april 12th, 2001 +Author: Richard Herveille +- removed records.vhd +- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools +- fixed a minor bug where core didn't respond to IDEen bit. +----------------------------- + +----------------------------- +Revision: 1.1 +Date: June 18th, 2001 +Author: Richard Herveille +- Changed PIOack generation. Avoid asserting PIOack continuosly when IDEen = '0' +- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) +----------------------------- + +----------------------------- +Revision: 1.1a +Date: June 19th, 2001 +Author: Richard Herveille +- Simplified DAT_O output multiplexor +----------------------------- + +----------------------------- +Revision: 1.2 +Date: June 26th, 2001 +Author: Richard Herveille +- Changed dPIOreq generation (controller.vhd). Wishbone burst accesses to ata device were not handled correctly +- Change PIOack from "out" to "buffer" (controller.vhd + ata.vhd) +----------------------------- + +----------------------------- +Revision: 1.3 +Date: July 11th, 2001 +Author: Richard Herveille +- renamed 'ata.vhd' to 'atahost.vhd' +- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous +- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). +----------------------------- + +----------------------------- +Revision: 1.4 +Date: Februar 17th, 2002 +Author: Richard Herveille +- renamed 'atahost.vhd' to 'atahost_top.vhd' +- renamed 'controller.vhd' to 'atahost_controller.vhd' +- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' +- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' +- changed resD input to generic RESD in ud_cnt.vhd +- changed ID input to generic ID in ro_cnt.vhd +- changed core to reflect changes in ro_cnt.vhd +- removed references to 'count' library +- changed IO names +- added disclaimer +- added CVS log +- moved registers and wishbone signals into 'atahost_wb_slave.vhd' +----------------------------- + +----------------------------- +Revision: 1.5 +Date: May 19th, 2002. +Author: Richard Herveille +- Fixed a potential bug that forced the core into an unknown state + when an asynchronous reset was given without a running clock +----------------------------- + Index: ata/trunk/rtl/vhdl/ocidec2/ro_cnt.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/ro_cnt.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/ro_cnt.vhd (revision 33) @@ -0,0 +1,131 @@ +--------------------------------------------------------------------- +---- ---- +---- Run-Once Counter ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:49:03 rherveille Exp $ +-- +-- $Date: 2002-03-01 03:49:03 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); +end entity ro_cnt; + +architecture structural of ro_cnt is + component ud_cnt is + generic( + SIZE : natural := 8; + RESD : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0); -- current counter value + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); + end component ud_cnt; + + signal rci, rco, nld : std_logic; +begin + gen_ctrl: process(clk, nReset) + begin + if (nReset = '0') then + rci <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + rci <= '0'; + else + rci <= go or (rci and not rco); + end if; + end if; + end process; + + nld <= not go; + + -- hookup counter + cnt : ud_cnt + generic map ( + SIZE => SIZE, + RESD => ID + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + cnt_en => cnt_en, + ud => UD, + nld => nld, + D => D, + Q => Q, + rci => rci, + rco => rco + ); + + done <= rco; +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec2/ud_cnt.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/ud_cnt.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/ud_cnt.vhd (revision 33) @@ -0,0 +1,102 @@ +--------------------------------------------------------------------- +---- ---- +---- Generic Up/Down counter (ripple carry architecture) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: ud_cnt.vhd,v 1.1 2002-03-01 03:49:03 rherveille Exp $ +-- +-- $Date: 2002-03-01 03:49:03 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ud_cnt is + generic( + SIZE : natural := 8; + RESD : natural := 0 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0); -- current counter value + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); +end entity ud_cnt; + +architecture structural of ud_cnt is + signal Qi : unsigned(SIZE -1 downto 0); + signal val : unsigned(SIZE downto 0); +begin + val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); + + regs: process(clk, nReset) + begin + if (nReset = '0') then + Qi <= conv_unsigned(RESD, SIZE); + elsif (clk'event and clk = '1') then + if (rst = '1') then + Qi <= conv_unsigned(RESD, SIZE); + else + if (nld = '0') then + Qi <= D; + elsif (cnt_en = '1') then + Qi <= val(SIZE -1 downto 0); + end if; + end if; + end if; + end process regs; + + -- assign outputs + Q <= Qi; + rco <= val(SIZE); +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd (revision 33) @@ -0,0 +1,285 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores ATA/ATAPI-5 Host Controller ---- +---- PIO Timing Controller (common for all OCIDEC cores) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 7th, 2001. Initial release +-- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation. +-- +-- +-- CVS Log +-- +-- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:30:48 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:30:48 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- +-- + +-- +--------------------------- +-- PIO Timing controller -- +--------------------------- +-- + +-- +-- Timing PIO mode transfers +---------------------------------------------- +-- T0: cycle time +-- T1: address valid to DIOR-/DIOW- +-- T2: DIOR-/DIOW- pulse width +-- T2i: DIOR-/DIOW- recovery time +-- T3: DIOW- data setup +-- T4: DIOW- data hold +-- T5: DIOR- data setup +-- T6: DIOR- data hold +-- T9: address hold from DIOR-/DIOW- negated +-- Trd: Read data valid to IORDY asserted +-- Ta: IORDY setup time +-- Tb: IORDY pulse width +-- +-- Transfer sequence +---------------------------------- +-- 1) set address (DA, CS0-, CS1-) +-- 2) wait for T1 +-- 3) assert DIOR-/DIOW- +-- when write action present Data (timing spec. T3 always honored), enable output enable-signal +-- 4) wait for T2 +-- 5) check IORDY +-- when not IORDY goto 5 +-- when IORDY negate DIOW-/DIOR-, latch data (if read action) +-- when write, hold data for T4, disable output-enable signal +-- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest +-- 7) start new cycle + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_pio_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing/control register settings + IORDY_en : in std_logic; -- use IORDY (or not) + T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) + T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) + T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- PIO controller selected (strobe signal) + we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device + + -- return signals + oe : buffer std_logic; -- output enable signal + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe, latch data (during read) + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic; -- IOwrite signal, active high + IORDY : in std_logic -- IORDY signal + ); +end entity atahost_pio_tctrl; + +architecture structural of atahost_pio_tctrl is + component ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); + end component ro_cnt; + + signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic; + signal busy, hold_go, igo, hT2done : std_logic; +begin + -- generate internal go strobe + -- strecht go until ready for new cycle + process(clk, nReset) + begin + if (nReset = '0') then + busy <= '0'; + hold_go <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + busy <= '0'; + hold_go <= '0'; + else + busy <= (igo or busy) and not Teoc_done; + hold_go <= (go or (hold_go and busy)) and not igo; + end if; + end if; + end process; + igo <= (go or hold_go) and not busy; + + -- 1) hookup T1 counter + t1_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T1 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => igo, + D => T1, + done => T1done + ); + + -- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device + T2proc: process(clk, nReset) + begin + if (nReset = '0') then + DIOR <= '0'; + DIOW <= '0'; + oe <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + DIOR <= '0'; + DIOW <= '0'; + oe <= '0'; + else + DIOR <= (not we and T1done) or (DIOR and not IORDY_done); + DIOW <= ( we and T1done) or (DIOW and not IORDY_done); + oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done + end if; + end if; + end process T2proc; + + -- 3) hookup T2 counter + t2_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T2 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => T1done, + D => T2, + done => T2done + ); + + -- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) + -- hold T2done + gen_hT2done: process(clk, nReset) + begin + if (nReset = '0') then + hT2done <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + hT2done <= '0'; + else + hT2done <= (T2done or hT2done) and not IORDY_done; + end if; + end if; + end process gen_hT2done; + IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en); + + -- generate datastrobe, capture data at rising DIOR- edge + gen_dstrb: process(clk) + begin + if (clk'event and clk = '1') then + dstrb <= IORDY_done; + end if; + end process gen_dstrb; + + -- hookup data hold counter + dhold_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T4 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => IORDY_done, + D => T4, + done => T4done + ); + done <= T4done; -- placing done here provides the fastest return possible, + -- while still guaranteeing data and address hold-times + + -- 5) hookup end_of_cycle counter + eoc_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => IORDY_done, + D => Teoc, + done => Teoc_done + ); + +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec2/atahost_top.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/atahost_top.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/atahost_top.vhd (revision 33) @@ -0,0 +1,469 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- ATA/ATAPI-5 Controller (OCIDEC-2) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0a Removed references to records.vhd, make core compatible with VHDL to Verilog translator tools +-- rev.: 1.1 june 18th, 2001. Changed wishbone address input from ADR_I(4 downto 0) to ADR_I(6 downto 2) +-- rev.: 1.1a june 19th, 2001. Simplified DAT_O output multiplexor. +-- +-- CVS Log +-- +-- $Id: atahost_top.vhd,v 1.1 2002-02-18 14:30:48 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:30:48 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + + +-- +-- DeviceType: OCIDEC-2: OpenCores IDE Controller type2 +-- Features: PIO Compatible Timing, PIO Fast Timing 0/1 +-- DeviceID: 0x02 +-- RevNo : 0x00 + +-- +-- Host signals: +-- Reset +-- DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. +-- DIOW- write strobe. The rising edge latches data from DD into the device. +-- DA(2:0) 3bit binary coded adress +-- CS0- select command block registers +-- CS1- select control block registers + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_top is + generic( + ARST_LVL : std_logic := '0'; -- asynchronous reset level + + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + -- WISHBONE SYSCON signals + wb_clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + wb_cyc_i : in std_logic; -- valid bus cycle input + wb_stb_i : in std_logic; -- strobe/core select input + wb_ack_o : out std_logic; -- strobe acknowledge output + wb_err_o : out std_logic; -- error output + wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in + wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out + wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + wb_we_i : in std_logic; -- Write enable input + wb_inta_o : out std_logic; -- interrupt request signal IDE0 + + -- ATA signals + resetn_pad_o : out std_logic; + dd_pad_i : in std_logic_vector(15 downto 0); + dd_pad_o : out std_logic_vector(15 downto 0); + dd_padoe_o : out std_logic; + da_pad_o : out unsigned(2 downto 0); + cs0n_pad_o : out std_logic; + cs1n_pad_o : out std_logic; + + diorn_pad_o : out std_logic; + diown_pad_o : out std_logic; + iordy_pad_i : in std_logic; + intrq_pad_i : in std_logic + ); +end entity atahost_top; + +architecture structural of atahost_top is + -- + -- constants + -- + + -- Device ID + constant DeviceId : unsigned(3 downto 0) := x"2"; + constant RevisionNo : unsigned(3 downto 0) := x"0"; + + -- + -- component declarations + -- + component atahost_wb_slave is + generic( + DeviceID : unsigned(3 downto 0) := x"0"; + RevisionNo : unsigned(3 downto 0) := x"0"; + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + cyc_i : in std_logic; -- valid bus cycle input + stb_i : in std_logic; -- strobe/core select input + ack_o : out std_logic; -- strobe acknowledge output + rty_o : out std_logic; -- retry output + err_o : out std_logic; -- error output + adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + dat_i : in std_logic_vector(31 downto 0); -- Databus in + dat_o : out std_logic_vector(31 downto 0); -- Databus out + sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + we_i : in std_logic; -- Write enable input + inta_o : out std_logic; -- interrupt request signal IDE0 + + -- PIO control input + PIOsel : buffer std_logic; + PIOtip, -- PIO transfer in progress + PIOack : in std_logic; -- PIO acknowledge signal + PIOq : in std_logic_vector(15 downto 0); -- PIO data input + PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full + irq : in std_logic; -- interrupt signal input + + -- DMA control inputs + DMAsel : out std_logic; + DMAtip, -- DMA transfer in progress + DMAack, -- DMA transfer acknowledge + DMARxEmpty, -- DMA receive buffer empty + DMATxFull, -- DMA transmit buffer full + DMA_dmarq : in std_logic; -- wishbone DMA request + DMAq : in std_logic_vector(31 downto 0); + + -- outputs + -- control register outputs + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR1, + IDEctrl_FATR0, + IDEctrl_ppen, + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : out std_logic; + + -- CMD port timing registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : buffer unsigned(7 downto 0); + PIO_cmdport_IORDYen : out std_logic; + + -- data-port0 timing registers + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : buffer unsigned(7 downto 0); + PIO_dport0_IORDYen : out std_logic; + + -- data-port1 timing registers + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : buffer unsigned(7 downto 0); + PIO_dport1_IORDYen : out std_logic; + + -- DMA device0 timing registers + DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc : buffer unsigned(7 downto 0); + + -- DMA device1 timing registers + DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc : buffer unsigned(7 downto 0) + ); + end component atahost_wb_slave; + + + component atahost_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + irq : out std_logic; -- interrupt request signal + + -- control / registers + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + -- PIO registers + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + PIOreq : in std_logic; -- PIO transfer request + PIOack : buffer std_logic; -- PIO transfer ended + PIOa : in unsigned(3 downto 0); -- PIO address + PIOd : in std_logic_vector(15 downto 0); -- PIO data in + PIOq : out std_logic_vector(15 downto 0); -- PIO data out + PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read + + -- ATA signals + RESETn : out std_logic; + DDi : in std_logic_vector(15 downto 0); + DDo : out std_logic_vector(15 downto 0); + DDoe : out std_logic; + DA : out unsigned(2 downto 0); + CS0n : out std_logic; + CS1n : out std_logic; + + DIORn : out std_logic; + DIOWn : out std_logic; + IORDY : in std_logic; + INTRQ : in std_logic + ); + end component atahost_controller; + + -- asynchronous reset signal + signal arst_signal : std_logic; + + -- primary address decoder + signal PIOsel : std_logic; -- controller select, IDE devices select + + -- registers + -- control register + signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic; + -- compatible mode timing register + signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0); + signal PIO_cmdport_IORDYen : std_logic; + -- data port0 timing register + signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : unsigned(7 downto 0); + signal PIO_dport0_IORDYen : std_logic; + -- data port1 timing register + signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : unsigned(7 downto 0); + signal PIO_dport1_IORDYen : std_logic; + + signal PIOack : std_logic; + signal PIOq : std_logic_vector(15 downto 0); + + signal irq : std_logic; -- ATA bus IRQ signal + +begin + -- generate asynchronous reset level + arst_signal <= arst_i xor ARST_LVL; + + -- + -- hookup wishbone slave + -- + u0: atahost_wb_slave + generic map( + DeviceID => DeviceID, + RevisionNo => RevisionNo, + + -- PIO mode 0 settings + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc, + + -- Multiword DMA mode 0 settings + -- OCIDEC-1 does not support DMA, set registers to zero + DMA_mode0_Tm => 0, + DMA_mode0_Td => 0, + DMA_mode0_Teoc => 0 + ) + port map( + -- WISHBONE SYSCON signals + clk_i => wb_clk_i, + arst_i => arst_signal, + rst_i => wb_rst_i, + + -- WISHBONE SLAVE signals + cyc_i => wb_cyc_i, + stb_i => wb_stb_i, + ack_o => wb_ack_o, + err_o => wb_err_o, + adr_i => wb_adr_i, + dat_i => wb_dat_i, + dat_o => wb_dat_o, + sel_i => wb_sel_i, + we_i => wb_we_i, + inta_o => wb_inta_o, + + -- PIO control input + -- PIOtip is only asserted during a PIO transfer (No shit! ;) + -- Since it is impossible to read the status register and access the PIO registers at the same time + -- this bit is useless (besides using-up resources) + PIOtip => '0', + PIOack => PIOack, + PIOq => PIOq, + PIOsel => PIOsel, + PIOpp_full => '0', -- OCIDEC-1 does not support PIO-write PingPong, negate signal + irq => irq, + + -- DMA control inputs (negate all of them) + DMAtip => '0', + DMAack => '0', + DMARxEmpty => '0', + DMATxFull => '0', + DMA_dmarq => '0', + DMAq => x"00000000", + + -- outputs + -- control register outputs + IDEctrl_rst => IDEctrl_rst, + IDEctrl_IDEen => IDEctrl_IDEen, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + + -- CMD port timing registers + PIO_cmdport_T1 => PIO_cmdport_T1, + PIO_cmdport_T2 => PIO_cmdport_T2, + PIO_cmdport_T4 => PIO_cmdport_T4, + PIO_cmdport_Teoc => PIO_cmdport_Teoc, + PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, + + -- data-port0 timing registers + PIO_dport0_T1 => PIO_dport0_T1, + PIO_dport0_T2 => PIO_dport0_T2, + PIO_dport0_T4 => PIO_dport0_T4, + PIO_dport0_Teoc => PIO_dport0_Teoc, + PIO_dport0_IORDYen => PIO_dport0_IORDYen, + + -- data-port1 timing registers + PIO_dport1_T1 => PIO_dport1_T1, + PIO_dport1_T2 => PIO_dport1_T2, + PIO_dport1_T4 => PIO_dport1_T4, + PIO_dport1_Teoc => PIO_dport1_Teoc, + PIO_dport1_IORDYen => PIO_dport1_IORDYen + ); + + -- + -- hookup controller section + -- + u1: atahost_controller + generic map( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map( + clk => wb_clk_i, + nReset => arst_signal, + rst => wb_rst_i, + irq => irq, + IDEctrl_rst => IDEctrl_rst, + IDEctrl_IDEen => IDEctrl_IDEen, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + cmdport_T1 => PIO_cmdport_T1, + cmdport_T2 => PIO_cmdport_T2, + cmdport_T4 => PIO_cmdport_T4, + cmdport_Teoc => PIO_cmdport_Teoc, + cmdport_IORDYen => PIO_cmdport_IORDYen, + dport0_T1 => PIO_dport0_T1, + dport0_T2 => PIO_dport0_T2, + dport0_T4 => PIO_dport0_T4, + dport0_Teoc => PIO_dport0_Teoc, + dport0_IORDYen => PIO_dport0_IORDYen, + dport1_T1 => PIO_dport1_T1, + dport1_T2 => PIO_dport1_T2, + dport1_T4 => PIO_dport1_T4, + dport1_Teoc => PIO_dport1_Teoc, + dport1_IORDYen => PIO_dport1_IORDYen, + PIOreq => PIOsel, + PIOack => PIOack, + PIOa => wb_adr_i(5 downto 2), + PIOd => wb_dat_i(15 downto 0), + PIOq => PIOq, + PIOwe => wb_we_i, + RESETn => resetn_pad_o, + DDi => dd_pad_i, + DDo => dd_pad_o, + DDoe => dd_padoe_o, + DA => da_pad_o, + CS0n => cs0n_pad_o, + CS1n => cs1n_pad_o, + DIORn => diorn_pad_o, + DIOWn => diown_pad_o, + IORDY => iordy_pad_i, + INTRQ => intrq_pad_i + ); +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd (revision 33) @@ -0,0 +1,467 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- Wishbone Slave (common for all OCIDEC cores) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:30:48 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:30:48 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_wb_slave is + generic( + DeviceID : unsigned(3 downto 0) := x"0"; + RevisionNo : unsigned(3 downto 0) := x"0"; + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + cyc_i : in std_logic; -- valid bus cycle input + stb_i : in std_logic; -- strobe/core select input + ack_o : out std_logic; -- strobe acknowledge output + rty_o : out std_logic; -- retry output + err_o : out std_logic; -- error output + adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + dat_i : in std_logic_vector(31 downto 0); -- Databus in + dat_o : out std_logic_vector(31 downto 0); -- Databus out + sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + we_i : in std_logic; -- Write enable input + inta_o : out std_logic; -- interrupt request signal IDE0 + + -- PIO control input + PIOsel : buffer std_logic; + PIOtip, -- PIO transfer in progress + PIOack : in std_logic; -- PIO acknowledge signal + PIOq : in std_logic_vector(15 downto 0); -- PIO data input + PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full + irq : in std_logic; -- interrupt signal input + + -- DMA control inputs + DMAsel : out std_logic; + DMAtip, -- DMA transfer in progress + DMAack, -- DMA transfer acknowledge + DMARxEmpty, -- DMA receive buffer empty + DMATxFull, -- DMA transmit buffer full + DMA_dmarq : in std_logic; -- wishbone DMA request + DMAq : in std_logic_vector(31 downto 0); + + -- outputs + -- control register outputs + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR1, + IDEctrl_FATR0, + IDEctrl_ppen, + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : out std_logic; + + -- CMD port timing registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : buffer unsigned(7 downto 0); + PIO_cmdport_IORDYen : out std_logic; + + -- data-port0 timing registers + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : buffer unsigned(7 downto 0); + PIO_dport0_IORDYen : out std_logic; + + -- data-port1 timing registers + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : buffer unsigned(7 downto 0); + PIO_dport1_IORDYen : out std_logic; + + -- DMA device0 timing registers + DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc : buffer unsigned(7 downto 0); + + -- DMA device1 timing registers + DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc : buffer unsigned(7 downto 0) + ); +end entity atahost_wb_slave; + +architecture structural of atahost_wb_slave is + -- + -- constants + -- + + -- addresses + alias ATA_DEV_ADR : std_logic is adr_i(6); + alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2); + + constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000"; + constant ATA_STAT_REG : unsigned(3 downto 0) := "0001"; + constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010"; + constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011"; + constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100"; + constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101"; + constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110"; + -- reserved -- + constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111"; + + -- + -- function declarations + -- + -- overload '=' to compare two unsigned numbers + function "=" (a, b : unsigned) return std_logic is + alias la: unsigned(1 to a'length) is a; + alias lb: unsigned(1 to b'length) is b; + variable result : std_logic; + begin + -- check vector length + assert a'length = b'length + report "std_logic_vector comparison: operands of unequal lengths" + severity FAILURE; + + result := '1'; + for n in 1 to a'length loop + result := result and not (la(n) xor lb(n)); + end loop; + + return result; + end; + + -- primary address decoder + signal CONsel : std_logic; -- controller select, IDE devices select + signal berr, brty : std_logic; -- bus error, bus retry + + -- registers + signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers + +begin + -- + -- generate bus cycle / address decoder + -- + gen_bc_dec: block + signal w_acc, dw_acc : std_logic; -- word access, double word access + signal store_pp_full : std_logic; + begin + -- word / double word + w_acc <= sel_i(1) and sel_i(0); + dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0); + + -- bus error + berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc; + + -- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full + PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full); + + -- CON accesses only 32bit wide + CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc; + DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT); + + -- bus retry (OCIDEC-3 and above) + -- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle + process(clk_i) + begin + if (clk_i'event and clk_i = '1') then + if (PIOsel = '0') then + store_pp_full <= PIOpp_full; + end if; + end if; + end process; + brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full); + end block gen_bc_dec; + + -- + -- generate registers + -- + register_block : block + signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers + signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers + signal sel_ctrl, sel_stat : std_logic; -- control / status register + begin + -- generate register select signals + sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG); + sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG); + sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD); + sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0); + sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1); + sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0); + sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1); + -- reserved 0x1C-0x38 -- + -- reserved 0x3C : DMA port -- + + -- generate control register + gen_ctrl_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + CtrlReg(31 downto 1) <= (others => '0'); + CtrlReg(0) <= '1'; -- set reset bit + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + CtrlReg(31 downto 1) <= (others => '0'); + CtrlReg(0) <= '1'; -- set reset bit + elsif (sel_ctrl = '1') then + CtrlReg <= dat_i; + end if; + end if; + end process gen_ctrl_reg; + -- assign bits + DMActrl_DMAen <= CtrlReg(15); + DMActrl_dir <= CtrlReg(13); + DMActrl_BeLeC1 <= CtrlReg(9); + DMActrl_BeLeC0 <= CtrlReg(8); + IDEctrl_IDEen <= CtrlReg(7); + IDEctrl_FATR1 <= CtrlReg(6); + IDEctrl_FATR0 <= CtrlReg(5); + IDEctrl_ppen <= CtrlReg(4); + PIO_dport1_IORDYen <= CtrlReg(3); + PIO_dport0_IORDYen <= CtrlReg(2); + PIO_cmdport_IORDYen <= CtrlReg(1); + IDEctrl_rst <= CtrlReg(0); + + -- generate status register clearable bits + gen_stat_reg: block + signal dirq, int : std_logic; + begin + gen_irq: process(clk_i, arst_i) + begin + if (arst_i = '0') then + int <= '0'; + dirq <= '0'; + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + int <= '0'; + dirq <= '0'; + else + int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0)); + dirq <= irq; + end if; + end if; + end process gen_irq; + + gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full) + begin + StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0') + + StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID + StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number + StatReg(15) <= DMAtip; + StatReg(10) <= DMARxEmpty; + StatReg(9) <= DMATxFull; + StatReg(8) <= DMA_dmarq; + StatReg(7) <= PIOtip; + StatReg(6) <= PIOpp_full; + StatReg(0) <= int; + end process; + end block gen_stat_reg; + + -- generate PIO compatible / command-port timing register + gen_PIO_cmdport_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_cmdport = '1') then + PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8)); + PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16)); + PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_cmdport_reg; + + -- generate PIO device0 timing register + gen_PIO_dport0_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_dport0 = '1') then + PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_dport0_T2 <= unsigned(dat_i(15 downto 8)); + PIO_dport0_T4 <= unsigned(dat_i(23 downto 16)); + PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_dport0_reg; + + -- generate PIO device1 timing register + gen_PIO_dport1_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_dport1 = '1') then + PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_dport1_T2 <= unsigned(dat_i(15 downto 8)); + PIO_dport1_T4 <= unsigned(dat_i(23 downto 16)); + PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_dport1_reg; + + -- generate DMA device0 timing register + gen_DMA_dev0_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (sel_DMA_dev0 = '1') then + DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0)); + DMA_dev0_Td <= unsigned(dat_i(15 downto 8)); + DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_DMA_dev0_reg; + + -- generate DMA device1 timing register + gen_DMA_dev1_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (sel_DMA_dev1 = '1') then + DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0)); + DMA_dev1_Td <= unsigned(dat_i(15 downto 8)); + DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_DMA_dev1_reg; + + end block register_block; + + -- + -- generate WISHBONE interconnect signals + -- + gen_WB_sigs: block + signal Q : std_logic_vector(31 downto 0); + begin + -- generate acknowledge signal + ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK + + -- generate error signal + err_o <= cyc_i and stb_i and berr; + + -- generate retry signal + rty_o <= cyc_i and stb_i and brty; + + -- assign interrupt signal + inta_o <= StatReg(0); + + -- generate output multiplexor + with ATA_ADR select + Q <= CtrlReg when ATA_CTRL_REG, -- control register + StatReg when ATA_STAT_REG, -- status register + std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register + std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0 + std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1 + std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0 + std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1 + DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register + (others => '0') when others; + + dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q; + end block gen_WB_sigs; + +end architecture structural; \ No newline at end of file Index: ata/trunk/rtl/vhdl/ocidec3/ro_cnt.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/ro_cnt.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/ro_cnt.vhd (revision 33) @@ -0,0 +1,131 @@ +--------------------------------------------------------------------- +---- ---- +---- Run-Once Counter ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: ro_cnt.vhd,v 1.1 2002-03-01 03:49:25 rherveille Exp $ +-- +-- $Date: 2002-03-01 03:49:25 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); +end entity ro_cnt; + +architecture structural of ro_cnt is + component ud_cnt is + generic( + SIZE : natural := 8; + RESD : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0); -- current counter value + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); + end component ud_cnt; + + signal rci, rco, nld : std_logic; +begin + gen_ctrl: process(clk, nReset) + begin + if (nReset = '0') then + rci <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + rci <= '0'; + else + rci <= go or (rci and not rco); + end if; + end if; + end process; + + nld <= not go; + + -- hookup counter + cnt : ud_cnt + generic map ( + SIZE => SIZE, + RESD => ID + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + cnt_en => cnt_en, + ud => UD, + nld => nld, + D => D, + Q => Q, + rci => rci, + rco => rco + ); + + done <= rco; +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec3/ud_cnt.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/ud_cnt.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/ud_cnt.vhd (revision 33) @@ -0,0 +1,102 @@ +--------------------------------------------------------------------- +---- ---- +---- Generic Up/Down counter (ripple carry architecture) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: ud_cnt.vhd,v 1.1 2002-03-01 03:49:25 rherveille Exp $ +-- +-- $Date: 2002-03-01 03:49:25 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity ud_cnt is + generic( + SIZE : natural := 8; + RESD : natural := 0 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + ud : in std_logic := '0'; -- up / not down + nld : in std_logic := '1'; -- synchronous active low load + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0); -- current counter value + + rci : in std_logic := '1'; -- carry input + rco : out std_logic -- carry output + ); +end entity ud_cnt; + +architecture structural of ud_cnt is + signal Qi : unsigned(SIZE -1 downto 0); + signal val : unsigned(SIZE downto 0); +begin + val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci); + + regs: process(clk, nReset) + begin + if (nReset = '0') then + Qi <= conv_unsigned(RESD, SIZE); + elsif (clk'event and clk = '1') then + if (rst = '1') then + Qi <= conv_unsigned(RESD, SIZE); + else + if (nld = '0') then + Qi <= D; + elsif (cnt_en = '1') then + Qi <= val(SIZE -1 downto 0); + end if; + end if; + end if; + end process regs; + + -- assign outputs + Q <= Qi; + rco <= val(SIZE); +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd (revision 33) @@ -0,0 +1,255 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- PIO Access Controller (common for OCIDEC 2 and above) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws --- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 9th, 2001 +-- rev.: 1.0a april 12th, 2001 Removed references to records.vhd +-- +-- +-- CVS Log +-- +-- $Id: atahost_pio_actrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ + +-- +--------------------------- +-- PIO Access controller -- +--------------------------- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_pio_actrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + SelDev : in std_logic; -- Selected device + + go : in std_logic; -- Start transfer sequence + done : out std_logic; -- Transfer sequence done + dir : in std_logic; -- Transfer direction '1'=write, '0'=read + a : in unsigned(3 downto 0); -- PIO transfer address + q : out std_logic_vector(15 downto 0); -- Data read from ATA devices + + DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus + oe : buffer std_logic; -- DDbus output-enable signal + + DIOR, + DIOW : buffer std_logic; + IORDY : in std_logic + ); +end entity atahost_pio_actrl; + +architecture structural of atahost_pio_actrl is + -- + -- Component declarations + -- + component atahost_pio_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing/control register settings + IORDY_en : in std_logic; -- use IORDY (or not) + T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) + T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) + T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- PIO controller selected (strobe signal) + we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device + + -- return signals + oe : buffer std_logic; -- output enable signal + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe, latch data (during read) + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic; -- IOwrite signal, active high + IORDY : in std_logic -- IORDY signal + ); + end component atahost_pio_tctrl; + + signal dstrb : std_logic; + signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0); + signal IORDYen : std_logic; + +begin + -- + -------------------------- + -- PIO transfer control -- + -------------------------- + -- + -- capture ATA data for PIO access + gen_PIOq: process(clk) + begin + if (clk'event and clk = '1') then + if (dstrb = '1') then + q <= DDi; + end if; + end if; + end process gen_PIOq; + + -- + -- PIO timing controllers + -- + + -- select timing settings for the addressed port + sel_port_t: process(clk, a, SelDev, IDEctrl_FATR1, IDEctrl_FATR0, + cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen, + dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen, + dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen) + variable Asel : std_logic; -- address selected + variable iT1, iT2, iT4, iTeoc : unsigned(TWIDTH -1 downto 0); + variable iIORDYen : std_logic; + begin + -- initially set timing registers to compatible timing + iT1 := cmdport_T1; + iT2 := cmdport_T2; + iT4 := cmdport_T4; + iTeoc := cmdport_Teoc; + iIORDYen := cmdport_IORDYen; + + -- detect data-port access + Asel := not a(3) and not a(2) and not a(1) and not a(0); -- data port + if (Asel = '1') then -- data port selected, 16bit transfers + if ((SelDev = '1') and (IDEctrl_FATR1 = '1')) then -- data port1 selected and enabled ? + iT1 := dport1_T1; + iT2 := dport1_T2; + iT4 := dport1_T4; + iTeoc := dport1_Teoc; + iIORDYen := dport1_IORDYen; + elsif((SelDev = '0') and (IDEctrl_FATR0 = '1')) then -- data port0 selected and enabled ? + iT1 := dport0_T1; + iT2 := dport0_T2; + iT4 := dport0_T4; + iTeoc := dport0_Teoc; + iIORDYen := dport0_IORDYen; + end if; + end if; + + if (clk'event and clk = '1') then + T1 <= iT1; + T2 <= iT2; + T4 <= iT4; + Teoc <= iTeoc; + IORDYen <= iIORDYen; + end if; + end process sel_port_t; + + -- + -- hookup timing controller + -- + PIO_timing_controller: atahost_pio_tctrl + generic map ( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + IORDY_en => IORDYen, + T1 => T1, + T2 => T2, + T4 => T4, + Teoc => Teoc, + go => go, + we => dir, + oe => oe, + done => done, + dstrb => dstrb, + DIOR => dior, + DIOW => diow, + IORDY => IORDY + ); +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd (revision 33) @@ -0,0 +1,285 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores ATA/ATAPI-5 Host Controller ---- +---- PIO Timing Controller (common for all OCIDEC cores) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 7th, 2001. Initial release +-- rev.: 1.1 July 11th, 2001. Changed 'igo' & 'hold_go' signal generation. +-- +-- +-- CVS Log +-- +-- $Id: atahost_pio_tctrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- +-- + +-- +--------------------------- +-- PIO Timing controller -- +--------------------------- +-- + +-- +-- Timing PIO mode transfers +---------------------------------------------- +-- T0: cycle time +-- T1: address valid to DIOR-/DIOW- +-- T2: DIOR-/DIOW- pulse width +-- T2i: DIOR-/DIOW- recovery time +-- T3: DIOW- data setup +-- T4: DIOW- data hold +-- T5: DIOR- data setup +-- T6: DIOR- data hold +-- T9: address hold from DIOR-/DIOW- negated +-- Trd: Read data valid to IORDY asserted +-- Ta: IORDY setup time +-- Tb: IORDY pulse width +-- +-- Transfer sequence +---------------------------------- +-- 1) set address (DA, CS0-, CS1-) +-- 2) wait for T1 +-- 3) assert DIOR-/DIOW- +-- when write action present Data (timing spec. T3 always honored), enable output enable-signal +-- 4) wait for T2 +-- 5) check IORDY +-- when not IORDY goto 5 +-- when IORDY negate DIOW-/DIOR-, latch data (if read action) +-- when write, hold data for T4, disable output-enable signal +-- 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest +-- 7) start new cycle + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_pio_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing/control register settings + IORDY_en : in std_logic; -- use IORDY (or not) + T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks) + T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks) + T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- PIO controller selected (strobe signal) + we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device + + -- return signals + oe : buffer std_logic; -- output enable signal + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe, latch data (during read) + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic; -- IOwrite signal, active high + IORDY : in std_logic -- IORDY signal + ); +end entity atahost_pio_tctrl; + +architecture structural of atahost_pio_tctrl is + component ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); + end component ro_cnt; + + signal T1done, T2done, T4done, Teoc_done, IORDY_done : std_logic; + signal busy, hold_go, igo, hT2done : std_logic; +begin + -- generate internal go strobe + -- strecht go until ready for new cycle + process(clk, nReset) + begin + if (nReset = '0') then + busy <= '0'; + hold_go <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + busy <= '0'; + hold_go <= '0'; + else + busy <= (igo or busy) and not Teoc_done; + hold_go <= (go or (hold_go and busy)) and not igo; + end if; + end if; + end process; + igo <= (go or hold_go) and not busy; + + -- 1) hookup T1 counter + t1_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T1 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => igo, + D => T1, + done => T1done + ); + + -- 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device + T2proc: process(clk, nReset) + begin + if (nReset = '0') then + DIOR <= '0'; + DIOW <= '0'; + oe <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + DIOR <= '0'; + DIOW <= '0'; + oe <= '0'; + else + DIOR <= (not we and T1done) or (DIOR and not IORDY_done); + DIOW <= ( we and T1done) or (DIOW and not IORDY_done); + oe <= ( (we and igo) or oe) and not T4done; -- negate oe when t4-done + end if; + end if; + end process T2proc; + + -- 3) hookup T2 counter + t2_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T2 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => T1done, + D => T2, + done => T2done + ); + + -- 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-) + -- hold T2done + gen_hT2done: process(clk, nReset) + begin + if (nReset = '0') then + hT2done <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + hT2done <= '0'; + else + hT2done <= (T2done or hT2done) and not IORDY_done; + end if; + end if; + end process gen_hT2done; + IORDY_done <= (T2done or hT2done) and (IORDY or not IORDY_en); + + -- generate datastrobe, capture data at rising DIOR- edge + gen_dstrb: process(clk) + begin + if (clk'event and clk = '1') then + dstrb <= IORDY_done; + end if; + end process gen_dstrb; + + -- hookup data hold counter + dhold_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_T4 + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => IORDY_done, + D => T4, + done => T4done + ); + done <= T4done; -- placing done here provides the fastest return possible, + -- while still guaranteeing data and address hold-times + + -- 5) hookup end_of_cycle counter + eoc_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => PIO_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => IORDY_done, + D => Teoc, + done => Teoc_done + ); + +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec3/atahost_top.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_top.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_top.vhd (revision 33) @@ -0,0 +1,577 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- ATA/ATAPI-5 IDE controller with DMA support ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- rev.: 1.0 Alpha version Januar 1st, 2001 +-- rev.: 1.0a Removed all references to records.vhd. Make core compatible with VHDL to Verilog translator tools +-- Changed DMA_req signal generation. Make the core compatible with the latest version of the OpenCores DMA engine +-- rev.: 1.1 june 18th, 2001. Changed wishbone address-input from ADR_I(4 downto 0) to ADR(6 downto 2) +-- rev.: 1.1a june 19th, 2001. Simplified DAT_O output multiplexor +-- +-- CVS Log +-- +-- $Id: atahost_top.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +-- +-- DeviceType: OCIDEC-3: OpenCores IDE Controller type3 +-- Features: PIO Compatible Timing, PIO Fast Timing 0/1, Single/Multiword DMA Timing 0/1 +-- DeviceID: 0x03 +-- RevNo : 0x00 + +-- +-- Host signals: +-- Reset +-- DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host. +-- DIOW- write strobe. The rising edge latches data from DD into the device. +-- DMACK- DMA acknowledge +-- DA(2:0) 3bit binary coded adress +-- CS0- select command block registers +-- CS1- select control block registers + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_top is + generic( + ARST_LVL : std_logic := '0'; -- asynchronous reset level + + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + wb_clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + wb_cyc_i : in std_logic; -- valid bus cycle input + wb_stb_i : in std_logic; -- strobe/core select input + wb_ack_o : out std_logic; -- strobe acknowledge output + wb_rty_o : out std_logic; -- retry output + wb_err_o : out std_logic; -- error output + wb_adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + wb_dat_i : in std_logic_vector(31 downto 0); -- Databus in + wb_dat_o : out std_logic_vector(31 downto 0); -- Databus out + wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + wb_we_i : in std_logic; -- Write enable input + wb_inta_o : out std_logic; -- interrupt request signal IDE0 + + -- DMA engine signals + DMA_req : out std_logic; -- DMA request + DMA_Ack : in std_logic; -- DMA acknowledge + + -- ATA signals + resetn_pad_o : out std_logic; + dd_pad_i : in std_logic_vector(15 downto 0); + dd_pad_o : out std_logic_vector(15 downto 0); + dd_padoe_o : out std_logic; + da_pad_o : out unsigned(2 downto 0); + cs0n_pad_o : out std_logic; + cs1n_pad_o : out std_logic; + + diorn_pad_o : out std_logic; + diown_pad_o : out std_logic; + iordy_pad_i : in std_logic; + intrq_pad_i : in std_logic; + + dmarq_pad_i : in std_logic; + dmackn_pad_o : out std_logic + ); +end entity atahost_top; + +architecture structural of atahost_top is + -- + -- Device ID + -- + constant DeviceId : unsigned(3 downto 0) := x"3"; + constant RevisionNo : unsigned(3 downto 0) := x"0"; + + -- + -- component declarations + -- + component atahost_wb_slave is + generic( + DeviceID : unsigned(3 downto 0) := x"0"; + RevisionNo : unsigned(3 downto 0) := x"0"; + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + cyc_i : in std_logic; -- valid bus cycle input + stb_i : in std_logic; -- strobe/core select input + ack_o : out std_logic; -- strobe acknowledge output + rty_o : out std_logic; -- retry output + err_o : out std_logic; -- error output + adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + dat_i : in std_logic_vector(31 downto 0); -- Databus in + dat_o : out std_logic_vector(31 downto 0); -- Databus out + sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + we_i : in std_logic; -- Write enable input + inta_o : out std_logic; -- interrupt request signal IDE0 + + -- PIO control input + PIOsel : buffer std_logic; + PIOtip, -- PIO transfer in progress + PIOack : in std_logic; -- PIO acknowledge signal + PIOq : in std_logic_vector(15 downto 0); -- PIO data input + PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full + irq : in std_logic; -- interrupt signal input + + -- DMA control inputs + DMAsel : out std_logic; + DMAtip, -- DMA transfer in progress + DMAack, + DMARxEmpty, -- DMA receive buffer empty + DMATxFull, -- DMA transmit buffer full + DMA_dmarq : in std_logic; -- wishbone DMA request + DMAq : in std_logic_vector(31 downto 0); + + -- outputs + -- control register outputs + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR1, + IDEctrl_FATR0, + IDEctrl_ppen, + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : out std_logic; + + -- CMD port timing registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : buffer unsigned(7 downto 0); + PIO_cmdport_IORDYen : out std_logic; + + -- data-port0 timing registers + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : buffer unsigned(7 downto 0); + PIO_dport0_IORDYen : out std_logic; + + -- data-port1 timing registers + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : buffer unsigned(7 downto 0); + PIO_dport1_IORDYen : out std_logic; + + -- DMA device0 timing registers + DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc : buffer unsigned(7 downto 0); + + -- DMA device1 timing registers + DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc : buffer unsigned(7 downto 0) + ); + end component atahost_wb_slave; + + component atahost_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + irq : out std_logic; -- interrupt request signal + + -- control / registers + IDEctrl_IDEen, + IDEctrl_rst, + IDEctrl_ppen, + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; -- control register settings + + a : in unsigned(3 downto 0); -- address input + d : in std_logic_vector(31 downto 0); -- data input + we : in std_logic; -- write enable input '1'=write, '0'=read + + -- PIO registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : in unsigned(7 downto 0); + PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings + + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : in unsigned(7 downto 0); + PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings + + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : in unsigned(7 downto 0); + PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings + + PIOsel : in std_logic; -- PIO controller select + PIOack : out std_logic; -- PIO controller acknowledge + PIOq : out std_logic_vector(15 downto 0); -- PIO data out + PIOtip : buffer std_logic; -- PIO transfer in progress + PIOpp_full : out std_logic; -- PIO Write PingPong full + + -- DMA registers + DMA_dev0_Td, + DMA_dev0_Tm, + DMA_dev0_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device0 + + DMA_dev1_Td, + DMA_dev1_Tm, + DMA_dev1_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device1 + + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : in std_logic; -- DMA settings + + DMAsel : in std_logic; -- DMA controller select + DMAack : out std_logic; -- DMA controller acknowledge + DMAq : out std_logic_vector(31 downto 0); -- DMA data out + DMAtip : buffer std_logic; -- DMA transfer in progress + DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line + + DMATxFull : buffer std_logic; -- DMA transmit buffer full + DMARxEmpty : buffer std_logic; -- DMA receive buffer empty + + DMA_req : out std_logic; -- DMA request to external DMA engine + DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine + + -- ATA signals + RESETn : out std_logic; + DDi : in std_logic_vector(15 downto 0); + DDo : out std_logic_vector(15 downto 0); + DDoe : out std_logic; + DA : out unsigned(2 downto 0); + CS0n : out std_logic; + CS1n : out std_logic; + + DMARQ : in std_logic; + DMACKn : out std_logic; + DIORn : out std_logic; + DIOWn : out std_logic; + IORDY : in std_logic; + INTRQ : in std_logic + ); + end component atahost_controller; + + -- asynchronous reset signal + signal arst_signal : std_logic; + + -- primary address decoder + signal PIOsel, DMAsel : std_logic; -- controller select, IDE devices select + + -- registers + -- IDE control register + signal IDEctrl_IDEen, IDEctrl_rst, IDEctrl_ppen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic; + -- PIO compatible timing settings + signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0); + signal PIO_cmdport_IORDYen : std_logic; + -- PIO data register device0 timing settings + signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : unsigned(7 downto 0); + signal PIO_dport0_IORDYen : std_logic; + -- PIO data register device1 timing settings + signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : unsigned(7 downto 0); + signal PIO_dport1_IORDYen : std_logic; + -- DMA control register + signal DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1 : std_logic; + -- DMA data port device0 timing settings + signal DMA_dev0_Td, DMA_dev0_Tm, DMA_dev0_Teoc : unsigned(7 downto 0); + -- DMA data port device1 timing settings + signal DMA_dev1_Td, DMA_dev1_Tm, DMA_dev1_Teoc : unsigned(7 downto 0); + + signal PIOack, DMAack, PIOtip, DMAtip : std_logic; + signal PIOq : std_logic_vector(15 downto 0); + signal PIOpp_full : std_logic; + signal DMAq : std_logic_vector(31 downto 0); + signal DMA_dmarq : std_logic; -- synchronized version of DMARQ + + signal DMATxFull, DMARxEmpty : std_logic; + + signal irq : std_logic; -- ATA bus IRQ signal + +begin + -- generate asynchronous reset level + arst_signal <= arst_i xor ARST_LVL; + + -- + -- hookup wishbone slave + -- + u0: atahost_wb_slave + generic map( + DeviceID => DeviceID, + RevisionNo => RevisionNo, + + -- PIO mode 0 settings + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc, + + -- Multiword DMA mode 0 settings + -- OCIDEC-1 does not support DMA, set registers to zero + DMA_mode0_Tm => 0, + DMA_mode0_Td => 0, + DMA_mode0_Teoc => 0 + ) + port map( + -- WISHBONE SYSCON signals + clk_i => wb_clk_i, + arst_i => arst_signal, + rst_i => wb_rst_i, + + -- WISHBONE SLAVE signals + cyc_i => wb_cyc_i, + stb_i => wb_stb_i, + ack_o => wb_ack_o, + rty_o => wb_rty_o, + err_o => wb_err_o, + adr_i => wb_adr_i, + dat_i => wb_dat_i, + dat_o => wb_dat_o, + sel_i => wb_sel_i, + we_i => wb_we_i, + inta_o => wb_inta_o, + + -- PIO control inputs + PIOsel => PIOsel, + PIOtip => PIOtip, + PIOack => PIOack, + PIOq => PIOq, + PIOpp_full => PIOpp_full, + irq => irq, + + -- DMA control inputs + DMAsel => DMAsel, + DMAtip => DMAtip, + DMAack => DMAack, + DMARxEmpty => DMARxEmpty, + DMATxFull => DMATxFull, + DMA_dmarq => DMA_dmarq, + DMAq => DMAq, + + -- outputs + -- control register outputs + IDEctrl_rst => IDEctrl_rst, + IDEctrl_IDEen => IDEctrl_IDEen, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + IDEctrl_ppen => IDEctrl_ppen, + + DMActrl_DMAen => DMActrl_DMAen, + DMActrl_dir => DMActrl_dir, + DMActrl_BeLeC0 => DMActrl_BeLeC0, + DMActrl_BeLeC1 => DMActrl_BeLeC1, + + -- CMD port timing registers + PIO_cmdport_T1 => PIO_cmdport_T1, + PIO_cmdport_T2 => PIO_cmdport_T2, + PIO_cmdport_T4 => PIO_cmdport_T4, + PIO_cmdport_Teoc => PIO_cmdport_Teoc, + PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, + + -- data-port0 timing registers + PIO_dport0_T1 => PIO_dport0_T1, + PIO_dport0_T2 => PIO_dport0_T2, + PIO_dport0_T4 => PIO_dport0_T4, + PIO_dport0_Teoc => PIO_dport0_Teoc, + PIO_dport0_IORDYen => PIO_dport0_IORDYen, + + -- data-port1 timing registers + PIO_dport1_T1 => PIO_dport1_T1, + PIO_dport1_T2 => PIO_dport1_T2, + PIO_dport1_T4 => PIO_dport1_T4, + PIO_dport1_Teoc => PIO_dport1_Teoc, + PIO_dport1_IORDYen => PIO_dport1_IORDYen, + + -- DMA device0 timing registers + DMA_dev0_Tm => DMA_dev0_Tm, + DMA_dev0_Td => DMA_dev0_Td, + DMA_dev0_Teoc => DMA_dev0_Teoc, + + -- DMA device1 timing registers + DMA_dev1_Tm => DMA_dev1_Tm, + DMA_dev1_Td => DMA_dev1_Td, + DMA_dev1_Teoc => DMA_dev1_Teoc + ); + + + -- + -- hookup controller section + -- + u1: atahost_controller + generic map( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc, + DMA_mode0_Tm => DMA_mode0_Tm, + DMA_mode0_Td => DMA_mode0_Td, + DMA_mode0_Teoc => DMA_mode0_Teoc + ) + port map( + clk => wb_clk_i, + nReset => arst_signal, + rst => wb_rst_i, + irq => irq, + IDEctrl_IDEen => IDEctrl_IDEen, + IDEctrl_rst => IDEctrl_rst, + IDEctrl_ppen => IDEctrl_ppen, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + a => wb_adr_i(5 downto 2), + d => wb_dat_i, + we => wb_we_i, + PIO_cmdport_T1 => PIO_cmdport_T1, + PIO_cmdport_T2 => PIO_cmdport_T2, + PIO_cmdport_T4 => PIO_cmdport_T4, + PIO_cmdport_Teoc => PIO_cmdport_Teoc, + PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, + PIO_dport0_T1 => PIO_dport0_T1, + PIO_dport0_T2 => PIO_dport0_T2, + PIO_dport0_T4 => PIO_dport0_T4, + PIO_dport0_Teoc => PIO_dport0_Teoc, + PIO_dport0_IORDYen => PIO_dport0_IORDYen, + PIO_dport1_T1 => PIO_dport1_T1, + PIO_dport1_T2 => PIO_dport1_T2, + PIO_dport1_T4 => PIO_dport1_T4, + PIO_dport1_Teoc => PIO_dport1_Teoc, + PIO_dport1_IORDYen => PIO_dport1_IORDYen, + PIOsel => PIOsel, + PIOack => PIOack, + PIOq => PIOq, + PIOtip => PIOtip, + PIOpp_full => PIOpp_full, + DMActrl_DMAen => DMActrl_DMAen, + DMActrl_dir => DMActrl_dir, + DMActrl_BeLeC0 => DMActrl_BeLeC0, + DMActrl_BeLeC1 => DMActrl_BeLeC1, + DMA_dev0_Td => DMA_dev0_Td, + DMA_dev0_Tm => DMA_dev0_Tm, + DMA_dev0_Teoc => DMA_dev0_Teoc, + DMA_dev1_Td => DMA_dev1_Td, + DMA_dev1_Tm => DMA_dev1_Tm, + DMA_dev1_Teoc => DMA_dev1_Teoc, + DMAsel => DMAsel, + DMAack => DMAack, + DMAq => DMAq, + DMAtip => DMAtip, + DMA_dmarq => DMA_dmarq, + DMATxFull => DMATxFull, + DMARxEmpty => DMARxEmpty, + DMA_req => DMA_req, + DMA_ack => DMA_ack, + RESETn => resetn_pad_o, + DDi => dd_pad_i, + DDo => dd_pad_o, + DDoe => dd_padoe_o, + DA => da_pad_o, + CS0n => cs0n_pad_o, + CS1n => cs1n_pad_o, + DIORn => diorn_pad_o, + DIOWn => diown_pad_o, + IORDY => iordy_pad_i, + INTRQ => intrq_pad_i, + DMARQ => dmarq_pad_i, + DMACKn => dmackn_pad_o + ); + +end architecture structural; + + + Index: ata/trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd (revision 33) @@ -0,0 +1,467 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- Wishbone Slave (common for all OCIDEC cores) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- +-- CVS Log +-- +-- $Id: atahost_wb_slave.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_wb_slave is + generic( + DeviceID : unsigned(3 downto 0) := x"0"; + RevisionNo : unsigned(3 downto 0) := x"0"; + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + -- WISHBONE SYSCON signals + clk_i : in std_logic; -- master clock in + arst_i : in std_logic := '1'; -- asynchronous active low reset + rst_i : in std_logic := '0'; -- synchronous active high reset + + -- WISHBONE SLAVE signals + cyc_i : in std_logic; -- valid bus cycle input + stb_i : in std_logic; -- strobe/core select input + ack_o : out std_logic; -- strobe acknowledge output + rty_o : out std_logic; -- retry output + err_o : out std_logic; -- error output + adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected + -- A5 = '1' CS1- asserted, '0' CS0- asserted + -- A4..A2 ATA address lines + -- A6 = '0' ATA controller selected + dat_i : in std_logic_vector(31 downto 0); -- Databus in + dat_o : out std_logic_vector(31 downto 0); -- Databus out + sel_i : in std_logic_vector(3 downto 0); -- Byte select signals + we_i : in std_logic; -- Write enable input + inta_o : out std_logic; -- interrupt request signal IDE0 + + -- PIO control input + PIOsel : buffer std_logic; + PIOtip, -- PIO transfer in progress + PIOack : in std_logic; -- PIO acknowledge signal + PIOq : in std_logic_vector(15 downto 0); -- PIO data input + PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full + irq : in std_logic; -- interrupt signal input + + -- DMA control inputs + DMAsel : out std_logic; + DMAtip, -- DMA transfer in progress + DMAack, -- DMA transfer acknowledge + DMARxEmpty, -- DMA receive buffer empty + DMATxFull, -- DMA transmit buffer full + DMA_dmarq : in std_logic; -- wishbone DMA request + DMAq : in std_logic_vector(31 downto 0); + + -- outputs + -- control register outputs + IDEctrl_rst, + IDEctrl_IDEen, + IDEctrl_FATR1, + IDEctrl_FATR0, + IDEctrl_ppen, + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : out std_logic; + + -- CMD port timing registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : buffer unsigned(7 downto 0); + PIO_cmdport_IORDYen : out std_logic; + + -- data-port0 timing registers + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : buffer unsigned(7 downto 0); + PIO_dport0_IORDYen : out std_logic; + + -- data-port1 timing registers + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : buffer unsigned(7 downto 0); + PIO_dport1_IORDYen : out std_logic; + + -- DMA device0 timing registers + DMA_dev0_Tm, + DMA_dev0_Td, + DMA_dev0_Teoc : buffer unsigned(7 downto 0); + + -- DMA device1 timing registers + DMA_dev1_Tm, + DMA_dev1_Td, + DMA_dev1_Teoc : buffer unsigned(7 downto 0) + ); +end entity atahost_wb_slave; + +architecture structural of atahost_wb_slave is + -- + -- constants + -- + + -- addresses + alias ATA_DEV_ADR : std_logic is adr_i(6); + alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2); + + constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000"; + constant ATA_STAT_REG : unsigned(3 downto 0) := "0001"; + constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010"; + constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011"; + constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100"; + constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101"; + constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110"; + -- reserved -- + constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111"; + + -- + -- function declarations + -- + -- overload '=' to compare two unsigned numbers + function "=" (a, b : unsigned) return std_logic is + alias la: unsigned(1 to a'length) is a; + alias lb: unsigned(1 to b'length) is b; + variable result : std_logic; + begin + -- check vector length + assert a'length = b'length + report "std_logic_vector comparison: operands of unequal lengths" + severity FAILURE; + + result := '1'; + for n in 1 to a'length loop + result := result and not (la(n) xor lb(n)); + end loop; + + return result; + end; + + -- primary address decoder + signal CONsel : std_logic; -- controller select, IDE devices select + signal berr, brty : std_logic; -- bus error, bus retry + + -- registers + signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers + +begin + -- + -- generate bus cycle / address decoder + -- + gen_bc_dec: block + signal w_acc, dw_acc : std_logic; -- word access, double word access + signal store_pp_full : std_logic; + begin + -- word / double word + w_acc <= sel_i(1) and sel_i(0); + dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0); + + -- bus error + berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc; + + -- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full + PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full); + + -- CON accesses only 32bit wide + CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc; + DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT); + + -- bus retry (OCIDEC-3 and above) + -- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle + process(clk_i) + begin + if (clk_i'event and clk_i = '1') then + if (PIOsel = '0') then + store_pp_full <= PIOpp_full; + end if; + end if; + end process; + brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full); + end block gen_bc_dec; + + -- + -- generate registers + -- + register_block : block + signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers + signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers + signal sel_ctrl, sel_stat : std_logic; -- control / status register + begin + -- generate register select signals + sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG); + sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG); + sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD); + sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0); + sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1); + sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0); + sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1); + -- reserved 0x1C-0x38 -- + -- reserved 0x3C : DMA port -- + + -- generate control register + gen_ctrl_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + CtrlReg(31 downto 1) <= (others => '0'); + CtrlReg(0) <= '1'; -- set reset bit + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + CtrlReg(31 downto 1) <= (others => '0'); + CtrlReg(0) <= '1'; -- set reset bit + elsif (sel_ctrl = '1') then + CtrlReg <= dat_i; + end if; + end if; + end process gen_ctrl_reg; + -- assign bits + DMActrl_DMAen <= CtrlReg(15); + DMActrl_dir <= CtrlReg(13); + DMActrl_BeLeC1 <= CtrlReg(9); + DMActrl_BeLeC0 <= CtrlReg(8); + IDEctrl_IDEen <= CtrlReg(7); + IDEctrl_FATR1 <= CtrlReg(6); + IDEctrl_FATR0 <= CtrlReg(5); + IDEctrl_ppen <= CtrlReg(4); + PIO_dport1_IORDYen <= CtrlReg(3); + PIO_dport0_IORDYen <= CtrlReg(2); + PIO_cmdport_IORDYen <= CtrlReg(1); + IDEctrl_rst <= CtrlReg(0); + + -- generate status register clearable bits + gen_stat_reg: block + signal dirq, int : std_logic; + begin + gen_irq: process(clk_i, arst_i) + begin + if (arst_i = '0') then + int <= '0'; + dirq <= '0'; + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + int <= '0'; + dirq <= '0'; + else + int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0)); + dirq <= irq; + end if; + end if; + end process gen_irq; + + gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full) + begin + StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0') + + StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID + StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number + StatReg(15) <= DMAtip; + StatReg(10) <= DMARxEmpty; + StatReg(9) <= DMATxFull; + StatReg(8) <= DMA_dmarq; + StatReg(7) <= PIOtip; + StatReg(6) <= PIOpp_full; + StatReg(0) <= int; + end process; + end block gen_stat_reg; + + -- generate PIO compatible / command-port timing register + gen_PIO_cmdport_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_cmdport = '1') then + PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8)); + PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16)); + PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_cmdport_reg; + + -- generate PIO device0 timing register + gen_PIO_dport0_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_dport0 = '1') then + PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_dport0_T2 <= unsigned(dat_i(15 downto 8)); + PIO_dport0_T4 <= unsigned(dat_i(23 downto 16)); + PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_dport0_reg; + + -- generate PIO device1 timing register + gen_PIO_dport1_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8); + PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8); + PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8); + PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8); + elsif (sel_PIO_dport1 = '1') then + PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0)); + PIO_dport1_T2 <= unsigned(dat_i(15 downto 8)); + PIO_dport1_T4 <= unsigned(dat_i(23 downto 16)); + PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_PIO_dport1_reg; + + -- generate DMA device0 timing register + gen_DMA_dev0_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (sel_DMA_dev0 = '1') then + DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0)); + DMA_dev0_Td <= unsigned(dat_i(15 downto 8)); + DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_DMA_dev0_reg; + + -- generate DMA device1 timing register + gen_DMA_dev1_reg: process(clk_i, arst_i) + begin + if (arst_i = '0') then + DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (clk_i'event and clk_i = '1') then + if (rst_i = '1') then + DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8); + DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8); + DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8); + elsif (sel_DMA_dev1 = '1') then + DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0)); + DMA_dev1_Td <= unsigned(dat_i(15 downto 8)); + DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24)); + end if; + end if; + end process gen_DMA_dev1_reg; + + end block register_block; + + -- + -- generate WISHBONE interconnect signals + -- + gen_WB_sigs: block + signal Q : std_logic_vector(31 downto 0); + begin + -- generate acknowledge signal + ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK + + -- generate error signal + err_o <= cyc_i and stb_i and berr; + + -- generate retry signal + rty_o <= cyc_i and stb_i and brty; + + -- assign interrupt signal + inta_o <= StatReg(0); + + -- generate output multiplexor + with ATA_ADR select + Q <= CtrlReg when ATA_CTRL_REG, -- control register + StatReg when ATA_STAT_REG, -- status register + std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register + std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0 + std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1 + std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0 + std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1 + DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register + (others => '0') when others; + + dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q; + end block gen_WB_sigs; + +end architecture structural; \ No newline at end of file Index: ata/trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd (revision 33) @@ -0,0 +1,170 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- synchronous single clock fifo, uses LFSR pointers ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 12th, 2001. Initial release +-- +-- CVS Log +-- +-- $Id: atahost_fifo.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_fifo is + generic( + DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range + -- 3, 7, 15, 31, 63 ... 65535 + SIZE : natural := 32 -- data width + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + rreq : in std_logic; -- read request + wreq : in std_logic; -- write request + + empty : out std_logic; -- fifo empty + full : out std_logic; -- fifo full + + D : in std_logic_vector(SIZE -1 downto 0); -- data input + Q : out std_logic_vector(SIZE -1 downto 0) -- data output + ); +end entity atahost_fifo; + +architecture structural of atahost_fifo is + -- + -- function declarations + -- + function bitsize(n : in natural) return natural is + variable tmp : unsigned(32 downto 1); + variable cnt : integer; + begin + tmp := conv_unsigned(n, 32); + cnt := 32; + + while ( (tmp(cnt) = '0') and (cnt > 0) ) loop + cnt := cnt -1; + end loop; + + return natural(cnt); + end function bitsize; + + -- + -- component declarations + -- + component atahost_lfsr is + generic( + TAPS : positive range 16 downto 3 :=8; + OFFSET : natural := 0 + ); + port( + clk : in std_logic; -- clock input + ena : in std_logic; -- count enable + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + Q : out unsigned(TAPS downto 1); -- count value + Qprev : out unsigned(TAPS downto 1) -- previous count value + ); + end component atahost_lfsr; + + constant ADEPTH : natural := bitsize(DEPTH); + + -- memory block + type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0); +-- shared variable mem : memory; -- VHDL'93 PREFERED + signal mem : memory; -- VHDL'87 + + -- address pointers + signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0); + +begin + -- generate write address; hookup write_pointer counter + wr_ptr_lfsr: atahost_lfsr + generic map( + TAPS => ADEPTH, + OFFSET => 0 + ) + port map( + clk => clk, + ena => wreq, + nReset => nReset, + rst => rst, + Q => wr_ptr, + Qprev => dwr_ptr + ); + + -- generate read address; hookup read_pointer counter + rd_ptr_lfsr: atahost_lfsr + generic map( + TAPS => ADEPTH, + OFFSET => 0 + ) + port map( + clk => clk, + ena => rreq, + nReset => nReset, + rst => rst, + Q => rd_ptr, + Qprev => drd_ptr + ); + + -- generate full/empty signal + full <= '1' when (wr_ptr = drd_ptr) else '0'; + empty <= '1' when (rd_ptr = wr_ptr) else '0'; + + -- generate memory structure + gen_mem: process(clk) + begin + if (clk'event and clk = '1') then + if (wreq = '1') then + mem(conv_integer(wr_ptr)) <= D; + end if; + end if; + end process gen_mem; + Q <= mem(conv_integer(rd_ptr)); +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec3/atahost_controller.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_controller.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_controller.vhd (revision 33) @@ -0,0 +1,575 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- ATA/ATAPI-5 Host controller (OCIDEC-3) ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 8th, 2001. Initial release +-- +-- CVS Log +-- +-- $Id: atahost_controller.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + + -- Multiword DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + irq : out std_logic; -- interrupt request signal + + -- control / registers + IDEctrl_IDEen, + IDEctrl_rst, + IDEctrl_ppen, + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; -- control register settings + + a : in unsigned(3 downto 0); -- address input + d : in std_logic_vector(31 downto 0); -- data input + we : in std_logic; -- write enable input '1'=write, '0'=read + + -- PIO registers + PIO_cmdport_T1, + PIO_cmdport_T2, + PIO_cmdport_T4, + PIO_cmdport_Teoc : in unsigned(7 downto 0); + PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings + + PIO_dport0_T1, + PIO_dport0_T2, + PIO_dport0_T4, + PIO_dport0_Teoc : in unsigned(7 downto 0); + PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings + + PIO_dport1_T1, + PIO_dport1_T2, + PIO_dport1_T4, + PIO_dport1_Teoc : in unsigned(7 downto 0); + PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings + + PIOsel : in std_logic; -- PIO controller select + PIOack : out std_logic; -- PIO controller acknowledge + PIOq : out std_logic_vector(15 downto 0); -- PIO data out + PIOtip : buffer std_logic; -- PIO transfer in progress + PIOpp_full : out std_logic; -- PIO Write PingPong full + + -- DMA registers + DMA_dev0_Td, + DMA_dev0_Tm, + DMA_dev0_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device0 + + DMA_dev1_Td, + DMA_dev1_Tm, + DMA_dev1_Teoc : in unsigned(7 downto 0); -- DMA timing settings for device1 + + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : in std_logic; -- DMA settings + + DMAsel : in std_logic; -- DMA controller select + DMAack : out std_logic; -- DMA controller acknowledge + DMAq : out std_logic_vector(31 downto 0); -- DMA data out + DMAtip : buffer std_logic; -- DMA transfer in progress + DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line + + DMATxFull : buffer std_logic; -- DMA transmit buffer full + DMARxEmpty : buffer std_logic; -- DMA receive buffer empty + + DMA_req : out std_logic; -- DMA request to external DMA engine + DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine + + -- ATA signals + RESETn : out std_logic; + DDi : in std_logic_vector(15 downto 0); + DDo : out std_logic_vector(15 downto 0); + DDoe : out std_logic; + DA : out unsigned(2 downto 0); + CS0n : out std_logic; + CS1n : out std_logic; + + DMARQ : in std_logic; + DMACKn : out std_logic; + DIORn : out std_logic; + DIOWn : out std_logic; + IORDY : in std_logic; + INTRQ : in std_logic + ); +end entity atahost_controller; + +architecture structural of atahost_controller is + -- + -- component declarations + -- + component atahost_pio_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + -- control / registers + IDEctrl_IDEen, + IDEctrl_ppen, + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + -- PIO registers + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + sel : in std_logic; -- PIO controller selected + ack : out std_logic; -- PIO controller acknowledge + a : in unsigned(3 downto 0); -- lower address bits + we : in std_logic; -- write enable input + d : in std_logic_vector(15 downto 0); + q : out std_logic_vector(15 downto 0); + + PIOreq : out std_logic; -- PIO transfer request + PPFull : out std_logic; -- PIO Write PingPong Full + go : in std_logic; -- start PIO transfer + done : buffer std_logic; -- done with PIO transfer + + PIOa : out unsigned(3 downto 0); -- PIO address, address lines towards ATA devices + PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices + + SelDev : buffer std_logic; -- Selected Device, Dev-bit in ATA Device/Head register + + DDi : in std_logic_vector(15 downto 0); + DDoe : buffer std_logic; + + DIOR : buffer std_logic; + DIOW : buffer std_logic; + IORDY : in std_logic + ); + end component atahost_pio_controller; + + component atahost_dma_actrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst' + + sel : in std_logic; -- DMA buffers selected + we : in std_logic; -- write enable input + ack : out std_logic; -- acknowledge output + + dev0_Tm, + dev0_Td, + dev0_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 0 + dev1_Tm, + dev1_Td, + dev1_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 1 + + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : in std_logic; -- control register settings + + TxD : in std_logic_vector(31 downto 0); -- DMA transmit data + TxFull : buffer std_logic; -- DMA transmit buffer full + RxQ : out std_logic_vector(31 downto 0); -- DMA receive data + RxEmpty : buffer std_logic; -- DMA receive buffer empty + RxFull : out std_logic; -- DMA receive buffer full + DMA_req : out std_logic; -- DMA request to external DMA engine + DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine + + DMARQ : in std_logic; -- ATA devices request DMA transfer + + SelDev : in std_logic; -- Selected device + + Go : in std_logic; -- Start transfer sequence + Done : out std_logic; -- Transfer sequence done + + DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus + DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus + + DIOR, + DIOW : buffer std_logic + ); + end component atahost_dma_actrl; + + -- + -- signals + -- + signal SelDev : std_logic; -- selected device + signal DMARxFull : std_logic; -- DMA receive buffer full + + -- PIO / DMA signals + signal PIOgo, DMAgo : std_logic; -- start PIO / DMA timing controller + signal PIOdone, DMAdone : std_logic; -- PIO / DMA timing controller done + + -- PIO signals + signal PIOdior, PIOdiow : std_logic; + signal PIOoe : std_logic; + + -- PIO pingpong signals + signal PIOd : std_logic_vector(15 downto 0); + signal PIOa : unsigned(3 downto 0); + signal PIOreq : std_logic; + + -- DMA signals + signal DMAd : std_logic_vector(15 downto 0); + signal DMAdior, DMAdiow : std_logic; + + -- synchronized ATA inputs + signal sDMARQ, sIORDY : std_logic; + +begin + + -- + -- synchronize incoming signals + -- + synch_incoming: block + signal cDMARQ : std_logic; -- capture DMARQ + signal cIORDY : std_logic; -- capture IORDY + signal cINTRQ : std_logic; -- capture INTRQ + begin + process(clk) + begin + if (clk'event and clk = '1') then + cDMARQ <= DMARQ; + cIORDY <= IORDY; + cINTRQ <= INTRQ; + + sDMARQ <= cDMARQ; + sIORDY <= cIORDY; + irq <= cINTRQ; + end if; + end process; + + DMA_dmarq <= sDMARQ; + end block synch_incoming; + + -- + -- generate ATA signals + -- + gen_ata_sigs: block + signal iDDo : std_logic_vector(15 downto 0); + begin + -- generate registers for ATA signals + gen_regs: process(clk, nReset) + begin + if (nReset = '0') then + RESETn <= '0'; + DIORn <= '1'; + DIOWn <= '1'; + DA <= (others => '0'); + CS0n <= '1'; + CS1n <= '1'; + DDo <= (others => '0'); + DDoe <= '0'; + DMACKn <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + RESETn <= '0'; + DIORn <= '1'; + DIOWn <= '1'; + DA <= (others => '0'); + CS0n <= '1'; + CS1n <= '1'; + DDo <= (others => '0'); + DDoe <= '0'; + DMACKn <= '1'; + else + RESETn <= not IDEctrl_rst; + DA <= PIOa(2 downto 0); + CS0n <= not (not PIOa(3) and PIOtip); -- CS0 asserted when A(3) = '0', negate during DMA transfers + CS1n <= not ( PIOa(3) and PIOtip); -- CS1 asserted when A(3) = '1', negate during DMA transfers + + if (PIOtip = '1') then + DDo <= PIOd; + DDoe <= PIOoe; + DIORn <= not PIOdior; + DIOWn <= not PIOdiow; + else + DDo <= DMAd; + DDoe <= DMActrl_dir and DMAtip; + DIORn <= not DMAdior; + DIOWn <= not DMAdiow; + end if; + + DMACKn <= not DMAtip; + end if; + end if; + end process gen_regs; + end block gen_ata_sigs; + + -- + -- generate bus controller statemachine + -- + statemachine: block + type states is (idle, PIO_state, DMA_state); + signal nxt_state, c_state : states; -- next_state, current_state + + signal iPIOgo, iDMAgo : std_logic; + begin + -- generate next state decoder + output decoder + gen_nxt_state: process(c_state, DMActrl_DMAen, DMActrl_dir, PIOreq, sDMARQ, DMATxFull, DMARxFull, PIOdone, DMAdone) + begin + nxt_state <= c_state; -- initialy stay in current state + + iPIOgo <= '0'; + iDMAgo <= '0'; + + case c_state is + -- idle + when idle => + -- DMA transfer pending ? + if ( (sDMARQ = '1') and (DMActrl_DMAen = '1') ) then + if (( (DMActrl_dir = '1') and (DMATxFull = '1') ) or ( (DMActrl_dir = '0') and (DMARxFull = '0') )) then + nxt_state <= DMA_state; -- DMA transfer + iDMAgo <= '1'; -- start DMA timing controller + end if; + -- PIO transfer pending ? + elsif (PIOreq = '1') then + nxt_state <= PIO_state; -- PIO transfer + iPIOgo <= '1'; + end if; + + -- PIO transfer + when PIO_state => + if (PIOdone = '1') then + nxt_state <= idle; + end if; + + -- DMA transfer + when DMA_state => + if (DMAdone = '1') then + nxt_state <= idle; + end if; + + when others => + nxt_state <= idle; -- go to idle state + + end case; + end process gen_nxt_state; + + -- generate registers + gen_regs: process(clk, nReset) + begin + if (nReset = '0') then + c_state <= idle; + PIOgo <= '0'; + DMAgo <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + c_state <= idle; + PIOgo <= '0'; + DMAgo <= '0'; + else + c_state <= nxt_state; + PIOgo <= iPIOgo; + DMAgo <= iDMAgo; + end if; + end if; + end process gen_regs; + + -- generate PIOtip / DMAtip + gen_tip: process(clk, nReset) + begin + if (nReset = '0') then + PIOtip <= '0'; + DMAtip <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + PIOtip <= '0'; + DMAtip <= '0'; + else + PIOtip <= iPIOgo or (PIOtip and not PIOdone); + DMAtip <= iDMAgo or (DMAtip and not ((DMAdone and DMActrl_dir) or (DMAdone and not sDMARQ and not DMActrl_dir)) ); + end if; + end if; + end process gen_tip; + end block statemachine; + + -- + -- Hookup PIO controller + -- + PIO_control: atahost_pio_controller + generic map( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map( + clk => clk, + nReset => nReset, + rst => rst, + IDEctrl_IDEen => IDEctrl_IDEen, + IDEctrl_ppen => IDEctrl_ppen, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + cmdport_T1 => PIO_cmdport_T1, + cmdport_T2 => PIO_cmdport_T2, + cmdport_T4 => PIO_cmdport_T4, + cmdport_Teoc => PIO_cmdport_Teoc, + cmdport_IORDYen => PIO_cmdport_IORDYen, + dport0_T1 => PIO_dport0_T1, + dport0_T2 => PIO_dport0_T2, + dport0_T4 => PIO_dport0_T4, + dport0_Teoc => PIO_dport0_Teoc, + dport0_IORDYen => PIO_dport0_IORDYen, + dport1_T1 => PIO_dport1_T1, + dport1_T2 => PIO_dport1_T2, + dport1_T4 => PIO_dport1_T4, + dport1_Teoc => PIO_dport1_Teoc, + dport1_IORDYen => PIO_dport1_IORDYen, + sel => PIOsel, + ack => PIOack, + a => a, + we => we, + d => d(15 downto 0), + q => PIOq, + PIOreq => PIOreq, + PPFull => PIOpp_full, + go => PIOgo, + done => PIOdone, + PIOa => PIOa, + PIOd => PIOd, + SelDev => SelDev, + DDi => DDi, + DDoe => PIOoe, + DIOR => PIOdior, + DIOW => PIOdiow, + IORDY => sIORDY + ); + + -- + -- Hookup DMA access controller + -- + DMA_control: atahost_dma_actrl + generic map( + TWIDTH => TWIDTH, + DMA_mode0_Tm => DMA_mode0_Tm, + DMA_mode0_Td => DMA_mode0_Td, + DMA_mode0_Teoc => DMA_mode0_Teoc + ) + port map( + clk => clk, + nReset => nReset, + rst => rst, + IDEctrl_rst => IDEctrl_rst, + DMActrl_DMAen => DMActrl_DMAen, + DMActrl_dir => DMActrl_dir, + DMActrl_BeLeC0 => DMActrl_BeLeC0, + DMActrl_BeLeC1 => DMActrl_BeLeC1, + dev0_Td => DMA_dev0_Td, + dev0_Tm => DMA_dev0_Tm, + dev0_Teoc => DMA_dev0_Teoc, + dev1_Td => DMA_dev1_Td, + dev1_Tm => DMA_dev1_Tm, + dev1_Teoc => DMA_dev1_Teoc, + sel => DMAsel, + ack => DMAack, + we => we, + TxD => d, + TxFull => DMATxFull, + RxQ => DMAq, + RxFull => DMARxFull, + RxEmpty => DMARxEmpty, + DMA_req => DMA_req, + DMA_ack => DMA_ack, + SelDev => SelDev, + Go => DMAgo, + Done => DMAdone, + DDi => DDi, + DDo => DMAd, + DIOR => DMAdior, + DIOW => DMAdiow, + DMARQ => sDMARQ + ); +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd (revision 33) @@ -0,0 +1,465 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- DMA (single- and multiword) mode access controller ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 9th, 2001. Initial release +-- +-- CVS Log +-- +-- $Id: atahost_dma_actrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- +-- + + +-- Host accesses to DMA ports are 32bit wide. Accesses are made by 2 consecutive 16bit accesses to the ATA +-- device's DataPort. The MSB HostData(31:16) is transfered first, then the LSB HostData(15:0) is transfered. + +-- +--------------------------- +-- DMA Access Controller -- +--------------------------- +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_dma_actrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst' + + sel : in std_logic; -- DMA buffers selected + we : in std_logic; -- write enable input + ack : out std_logic; -- acknowledge output + + dev0_Tm, + dev0_Td, + dev0_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 0 + dev1_Tm, + dev1_Td, + dev1_Teoc : in unsigned(7 downto 0); -- DMA mode timing device 1 + + DMActrl_DMAen, + DMActrl_dir, + DMActrl_BeLeC0, + DMActrl_BeLeC1 : in std_logic; -- control register settings + + TxD : in std_logic_vector(31 downto 0); -- DMA transmit data + TxFull : buffer std_logic; -- DMA transmit buffer full + RxQ : out std_logic_vector(31 downto 0); -- DMA receive data + RxEmpty : buffer std_logic; -- DMA receive buffer empty + RxFull : out std_logic; -- DMA receive buffer full + DMA_req : out std_logic; -- DMA request to external DMA engine + DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine + + DMARQ : in std_logic; -- ATA devices request DMA transfer + + SelDev : in std_logic; -- Selected device + + Go : in std_logic; -- Start transfer sequence + Done : out std_logic; -- Transfer sequence done + + DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus + DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus + + DIOR, + DIOW : buffer std_logic + ); +end entity atahost_dma_actrl; + +architecture structural of atahost_dma_actrl is + -- + -- component declarations + -- + component atahost_dma_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 6; -- 70ns + DMA_mode0_Td : natural := 28; -- 290ns + DMA_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing register settings + Tm : in unsigned(TWIDTH -1 downto 0); -- Tm time (in clk-ticks) + Td : in unsigned(TWIDTH -1 downto 0); -- Td time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- DMA controller selected (strobe signal) + we : in std_logic; -- DMA direction '1' = write, '0' = read + + -- return signals + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic -- IOwrite signal, active high + ); + end component atahost_dma_tctrl; + + component atahost_reg_buf is + generic ( + WIDTH : natural := 8 + ); + port( + clk : in std_logic; + nReset : in std_logic; + rst : in std_logic; + + D : in std_logic_vector(WIDTH -1 downto 0); + Q : out std_logic_vector(WIDTH -1 downto 0); + rd : in std_logic; + wr : in std_logic; + valid : buffer std_logic + ); + end component atahost_reg_buf; + + component atahost_fifo is + generic( + DEPTH : natural := 32; -- fifo depth + SIZE : natural := 32 -- data width + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + rreq : in std_logic; -- read request + wreq : in std_logic; -- write request + + empty : out std_logic; -- fifo empty + full : out std_logic; -- fifo full + + D : in std_logic_vector(SIZE -1 downto 0); -- data input + Q : out std_logic_vector(SIZE -1 downto 0) -- data output + ); + end component atahost_fifo; + + signal Tdone, Tfw : std_logic; + signal RxWr, TxRd : std_logic; + signal dstrb, rd_dstrb, wr_dstrb : std_logic; + signal TxbufQ, RxbufD : std_logic_vector(31 downto 0); + +begin + + -- note: *fw = *first_word, *lw = *last_word + + + -- + -- generate DDi/DDo controls + -- + gen_DMA_sigs: block + signal writeDfw, writeDlw : std_logic_vector(15 downto 0); + signal readDfw, readDlw : std_logic_vector(15 downto 0); + signal BeLeC : std_logic; -- BigEndian <-> LittleEndian conversion + begin + -- generate byte_swap signal + BeLeC <= (not SelDev and DMActrl_BeLeC0) or (SelDev and DMActrl_BeLeC1); + + -- generate Tfw (Transfering first word) + gen_Tfw: process(clk, nReset) + begin + if (nReset = '0') then + Tfw <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + Tfw <= '0'; + else + Tfw <= go or (Tfw and not Tdone); + end if; + end if; + end process gen_Tfw; + + -- transmit data part + gen_writed_pipe:process(clk) + begin + if (clk'event and clk = '1') then + if (TxRd = '1') then -- reload registers + if (BeLeC = '1') then -- Do big<->little endian conversion + writeDfw(15 downto 8) <= TxbufQ( 7 downto 0); -- TxbufQ = data from transmit buffer + writeDfw( 7 downto 0) <= TxbufQ(15 downto 8); + writeDlw(15 downto 8) <= TxbufQ(23 downto 16); + writeDlw( 7 downto 0) <= TxbufQ(31 downto 24); + else -- don't do big<->little endian conversion + writeDfw <= TxbufQ(31 downto 16); + writeDlw <= TxbufQ(15 downto 0); + end if; + elsif (wr_dstrb = '1') then -- next word to transfer + writeDfw <= writeDlw; + end if; + end if; + end process gen_writed_pipe; + DDo <= writeDfw; -- assign DMA data out + + -- generate transmit register read request + gen_Tx_rreq: process(clk, nReset) + begin + if (nReset = '0') then + TxRd <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + TxRd <= '0'; + else + TxRd <= go and DMActrl_dir; + end if; + end if; + end process gen_Tx_rreq; + + -- receive + gen_readd_pipe:process(clk) + begin + if (clk'event and clk = '1') then + if (rd_dstrb = '1') then + + readDfw <= readDlw; -- shift previous read word to msb + if (BeLeC = '1') then -- swap bytes + readDlw(15 downto 8) <= DDi( 7 downto 0); + readDlw( 7 downto 0) <= DDi(15 downto 8); + else -- don't swap bytes + readDlw <= DDi; + end if; + end if; + end if; + end process gen_readd_pipe; + -- RxD = data to receive buffer + RxbufD <= (readDfw & readDlw) when (BeLeC = '0') else (readDlw & readDfw); + + -- generate receive register write request + gen_Rx_wreq: process(clk, nReset) + begin + if (nReset = '0') then + RxWr <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + RxWr <= '0'; + else + RxWr <= not Tfw and rd_dstrb; + end if; + end if; + end process gen_Rx_wreq; + end block gen_DMA_sigs; + + + -- + -- Hookup DMA read / write buffers + -- + gen_DMAbuf: block + signal DMArst : std_logic; + signal RxRd, TxWr : std_logic; + signal iRxEmpty : std_logic; + begin + -- generate DMA reset signal + DMArst <= rst or IDEctrl_rst; + + Txbuf: atahost_reg_buf + generic map (WIDTH => 32) + port map ( + clk => clk, + nReset => nReset, + rst => DMArst, + D => TxD, + Q => TxbufQ, + rd => TxRd, + wr => TxWr, + valid => TxFull + ); + + Rxbuf: atahost_fifo + generic map (DEPTH => 7, SIZE => 32) + port map ( + clk => clk, + nReset => nReset, + rst => DMArst, + D => RxbufD, + Q => RxQ, + rreq => RxRd, + wreq => RxWr, + empty => iRxEmpty, + full => RxFull + ); + + RxEmpty <= iRxEmpty; -- avoid 'cannot associate OUT port with BUFFER port' error + + -- + -- generate DMA buffer access signals + -- + RxRd <= sel and not we and not RxEmpty; + TxWr <= sel and we and not TxFull; + + ack <= RxRd or TxWr; -- DMA buffer access acknowledge + end block gen_DMAbuf; + + -- + -- generate request signal for external DMA engine + -- + gen_DMA_req: block + signal hgo : std_logic; + signal iDMA_req : std_logic; + signal request : std_logic; + begin + -- generate hold-go + gen_hgo : process(clk, nReset) + begin + if (nReset = '0') then + hgo <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + hgo <= '0'; + else + hgo <= go or (hgo and not (wr_dstrb and not Tfw) and DMActrl_dir); + end if; + end if; + end process gen_hgo; + + request <= (DMActrl_dir and DMARQ and not TxFull and not hgo) or not RxEmpty; + process(clk, nReset) + begin + if (nReset = '0') then + iDMA_req <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + iDMA_req <= '0'; + else + iDMA_req <= DMActrl_DMAen and not DMA_ack and (request or iDMA_req); +-- DMA_req <= (DMActrl_DMAen and DMActrl_dir and DMARQ and not TxFull and not hgo) or not RxEmpty; + end if; + end if; + end process; + DMA_req <= iDMA_req; + end block gen_DMA_req; + + + -- + -- DMA timing controller + -- + DMA_timing_ctrl: block + signal Tm, Td, Teoc, Tdmack_ext : unsigned(TWIDTH -1 downto 0); + signal dTfw, igo : std_logic; + begin + -- + -- generate internal GO signal + -- + gen_igo : process(clk, nReset) + begin + if (nReset = '0') then + igo <= '0'; + dTfw <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + igo <= '0'; + dTfw <= '0'; + else + igo <= go or (not Tfw and dTfw); + dTfw <= Tfw; + end if; + end if; + end process gen_igo; + + -- + -- select timing settings for the addressed device + -- + sel_dev_t: process(clk) + begin + if (clk'event and clk = '1') then + if (SelDev = '1') then -- device1 selected + Tm <= dev1_Tm; + Td <= dev1_Td; + Teoc <= dev1_Teoc; + else -- device0 selected + Tm <= dev0_Tm; + Td <= dev0_Td; + Teoc <= dev0_Teoc; + end if; + end if; + end process sel_dev_t; + + -- + -- hookup timing controller + -- + DMA_timing_ctrl: atahost_dma_tctrl + generic map ( + TWIDTH => TWIDTH, + DMA_mode0_Tm => DMA_mode0_Tm, + DMA_mode0_Td => DMA_mode0_Td, + DMA_mode0_Teoc => DMA_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + Tm => Tm, + Td => Td, + Teoc => Teoc, + go => igo, + we => DMActrl_dir, + done => Tdone, + dstrb => dstrb, + DIOR => dior, + DIOW => diow + ); + + done <= Tdone and not Tfw; -- done transfering last word + rd_dstrb <= dstrb and not DMActrl_dir; -- read data strobe + wr_dstrb <= dstrb and DMActrl_dir; -- write data strobe + end block DMA_timing_ctrl; + +end architecture structural; + Index: ata/trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd (revision 33) @@ -0,0 +1,144 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- Linear Feedback Shift Register ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 12th, 2001. Initial release +-- +-- CVS Log +-- +-- $Id: atahost_lfsr.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_lfsr is + generic( + TAPS : positive range 16 downto 3 :=8; + OFFSET : natural := 0 + ); + port( + clk : in std_logic; -- clock input + ena : in std_logic; -- count enable + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + Q : out unsigned(TAPS downto 1); -- count value + Qprev : out unsigned(TAPS downto 1) -- previous count value + ); +end entity atahost_lfsr; + +architecture dataflow of atahost_lfsr is + function lsb(tap : positive range 16 downto 3; Q : unsigned(TAPS downto 1) ) return std_logic is + begin + case tap is + when 3 => + return Q(3) xnor Q(2); + when 4 => + return Q(4) xnor Q(3); + when 5 => + return Q(5) xnor Q(3); + when 6 => + return Q(6) xnor Q(5); + when 7 => + return Q(7) xnor Q(6); + when 8 => + return (Q(8) xnor Q(6)) xnor (Q(5) xnor Q(4)); + when 9 => + return Q(9) xnor Q(5); + when 10 => + return Q(10) xnor Q(7); + when 11 => + return Q(11) xnor Q(9); + when 12 => + return (Q(12) xnor Q(6)) xnor (Q(4) xnor Q(1)); + when 13 => + return (Q(13) xnor Q(4)) xnor (Q(3) xnor Q(1)); + when 14 => + return (Q(14) xnor Q(5)) xnor (Q(3) xnor Q(1)); + when 15 => + return Q(15) xnor Q(14); + when 16 => + return (Q(16) xnor Q(15)) xnor (Q(13) xnor Q(4)); + end case; + end function lsb; + + signal msb : std_logic; + signal iQ : unsigned(TAPS downto 1); + +begin + -- + -- generate register + -- + gen_regs: process(clk, nReset) + variable tmpQ : unsigned(TAPS downto 1); + variable tmpmsb : std_logic; + begin + tmpQ := (others => '0'); + tmpmsb := '1'; + + for n in 1 to offset loop + tmpQ := (tmpQ(TAPS -1 downto 1) & lsb(TAPS, tmpQ) ); + tmpmsb := tmpQ(TAPS); + end loop; + + if (nReset = '0') then + iQ <= tmpQ; + msb <= tmpmsb; + elsif (clk'event and clk = '1') then + if (rst = '1') then + iQ <= tmpQ; + msb <= tmpmsb; + elsif (ena = '1') then + iQ <= (iQ(TAPS -1 downto 1) & lsb(TAPS, iq) ); + msb <= iQ(TAPS); + end if; + end if; + end process gen_regs; + + -- assign outputs + Q <= iQ; + Qprev <= (msb & iQ(TAPS downto 2)); +end architecture dataflow; + Index: ata/trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd (revision 33) @@ -0,0 +1,222 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- DMA (single- and multiword) mode timing statemachine ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 7th, 2001. Initial release +-- +-- CVS Log +-- +-- $Id: atahost_dma_tctrl.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +-- +--------------------------- +-- DMA Timing Controller -- +--------------------------- +-- + +-- +-- Timing DMA mode transfers +---------------------------------------------- +-- T0: cycle time +-- Td: DIOR-/DIOW- asserted pulse width +-- Te: DIOR- data access +-- Tf: DIOR- data hold +-- Tg: DIOR-/DIOW- data setup +-- Th: DIOW- data hold +-- Ti: DMACK to DIOR-/DIOW- setup +-- Tj: DIOR-/DIOW- to DMACK hold +-- Tkr: DIOR- negated pulse width +-- Tkw: DIOW- negated pulse width +-- Tm: CS(1:0) valid to DIOR-/DIOW- +-- Tn: CS(1:0) hold +-- +-- +-- Transfer sequence +---------------------------------- +-- 1) wait for Tm +-- 2) assert DIOR-/DIOW- +-- when write action present data (Timing spec. Tg always honored) +-- output enable is controlled by DMA-direction and DMACK- +-- 3) wait for Td +-- 4) negate DIOR-/DIOW- +-- when read action, latch data +-- 5) wait for Teoc (T0 - Td - Tm) or Tkw, whichever is greater +-- Th, Tj, Tk, Tn always honored +-- 6) start new cycle +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_dma_tctrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- DMA mode 0 settings (@100MHz clock) + DMA_mode0_Tm : natural := 4; -- 50ns + DMA_mode0_Td : natural := 21; -- 215ns + DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + -- timing register settings + Tm : in unsigned(TWIDTH -1 downto 0); -- Tm time (in clk-ticks) + Td : in unsigned(TWIDTH -1 downto 0); -- Td time (in clk-ticks) + Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time + + -- control signals + go : in std_logic; -- DMA controller selected (strobe signal) + we : in std_logic; -- DMA direction '1' = write, '0' = read + + -- return signals + done : out std_logic; -- finished cycle + dstrb : out std_logic; -- data strobe + + -- ATA signals + DIOR, -- IOread signal, active high + DIOW : buffer std_logic -- IOwrite signal, active high + ); +end entity atahost_dma_tctrl; + +architecture structural of atahost_dma_tctrl is + component ro_cnt is + generic( + SIZE : natural := 8; + UD : std_logic := '0'; -- default count down + ID : natural := 0 -- initial data after reset + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + cnt_en : in std_logic := '1'; -- count enable + go : in std_logic; -- load counter and start sequence + done : out std_logic; -- done counting + d : in unsigned(SIZE -1 downto 0); -- load counter value + q : out unsigned(SIZE -1 downto 0) -- current counter value + ); + end component ro_cnt; + + signal Tmdone, Tddone : std_logic; +begin + + -- 1) hookup Tm counter + tm_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => DMA_mode0_Tm + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => go, + D => Tm, + done => Tmdone + ); + + -- 2) set (and reset) DIOR-/DIOW- + T2proc: process(clk, nReset) + begin + if (nReset = '0') then + DIOR <= '0'; + DIOW <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + DIOR <= '0'; + DIOW <= '0'; + else + DIOR <= (not we and Tmdone) or (DIOR and not Tddone); + DIOW <= ( we and Tmdone) or (DIOW and not Tddone); + end if; + end if; + end process T2proc; + + -- 3) hookup Td counter + td_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => DMA_mode0_Td + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => Tmdone, + D => Td, + done => Tddone + ); + + -- generate data_strobe + gen_dstrb: process(clk) + begin + if (clk'event and clk = '1') then + dstrb <= Tddone; -- capture data at rising edge of DIOR- + end if; + end process gen_dstrb; + + -- 4) negate DIOR-/DIOW- when Tddone + -- 5) hookup end_of_cycle counter + eoc_cnt : ro_cnt + generic map ( + SIZE => TWIDTH, + UD => '0', + ID => DMA_mode0_Teoc + ) + port map ( + clk => clk, + nReset => nReset, + rst => rst, + go => Tddone, + D => Teoc, + done => done + ); +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd (revision 33) @@ -0,0 +1,89 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: atahost_reg_buf.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + + +library ieee; +use ieee.std_logic_1164.all; + +entity atahost_reg_buf is + generic ( + WIDTH : natural := 8 + ); + port( + clk : in std_logic; + nReset : in std_logic; + rst : in std_logic; + + D : in std_logic_vector(WIDTH -1 downto 0); + Q : out std_logic_vector(WIDTH -1 downto 0); + rd : in std_logic; + wr : in std_logic; + valid : buffer std_logic + ); +end entity atahost_reg_buf; + +architecture structural of atahost_reg_buf is +begin + process(clk, nReset) + begin + if (nReset = '0') then + Q <= (others => '0'); + valid <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + Q <= (others => '0'); + valid <= '0'; + else + if (wr = '1') then + Q <= D; + end if; + valid <= wr or (valid and not rd); + end if; + end if; + end process; +end architecture structural; Index: ata/trunk/rtl/vhdl/ocidec3/revision_history.txt =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/revision_history.txt (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/revision_history.txt (revision 33) @@ -0,0 +1,53 @@ +----------------------------- +Revision: 1.0 +Date: march 22nd, 2001 +Author: Richard Herveille +- initial release +----------------------------- + +----------------------------- +Revision: 1.0a +Date: april 12th, 2001 +Author: Richard Herveille +- removed records.vhd +- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools +- fixed a minor bug where core didn't respond to IDEen bit. +----------------------------- + +----------------------------- +Revision: 1.1 +Date: june 18th, 2001 +Author: Richard Herveille +- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2) +----------------------------- + +----------------------------- +Revision: 1.1a +Date: june 19th, 2001 +Author: Richard Herveille +- Simplified DAT_O output multiplexor +----------------------------- + +----------------------------- +Revision: 1.3 +Date: July 11th, 2001 +Author: Richard Herveille +- renamed 'ata.vhd' to 'atahost.vhd' +- Changed 'go' & 'igo' generation (pio_tctrl.vhdl). +----------------------------- + +----------------------------- +Revision: 1.4 +Date: Februar 17th, 2002 +Author: Richard Herveille +- renamed all files to 'atahost_***.vhd' +- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' +- changed resD input to generic RESD in ud_cnt.vhd +- changed ID input to generic ID in ro_cnt.vhd +- changed core to reflect changes in ro_cnt.vhd +- removed references to 'count' library +- changed IO names +- added disclaimer +- added CVS log +- moved registers and wishbone signals into 'atahost_wb_slave.vhd' +----------------------------- Index: ata/trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd =================================================================== --- ata/trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd (nonexistent) +++ ata/trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd (revision 33) @@ -0,0 +1,380 @@ +--------------------------------------------------------------------- +---- ---- +---- OpenCores IDE Controller ---- +---- ATA/ATAPI-5 PIO controller with write PingPong ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2001, 2002 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- rev.: 1.0 march 8th, 2001. Initial release +-- +-- CVS Log +-- +-- $Id: atahost_pio_controller.vhd,v 1.1 2002-02-18 14:32:12 rherveille Exp $ +-- +-- $Date: 2002-02-18 14:32:12 $ +-- $Revision: 1.1 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity atahost_pio_controller is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock in + nReset : in std_logic := '1'; -- asynchronous active low reset + rst : in std_logic := '0'; -- synchronous active high reset + + -- control / registers + IDEctrl_IDEen, + IDEctrl_ppen, + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + -- PIO registers + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + sel : in std_logic; -- PIO controller selected + ack : out std_logic; -- PIO controller acknowledge + a : in unsigned(3 downto 0); -- lower address bits + we : in std_logic; -- write enable input + d : in std_logic_vector(15 downto 0); + q : out std_logic_vector(15 downto 0); + + PIOreq : out std_logic; -- PIO transfer request + PPFull : out std_logic; -- PIO Write PingPong Full + go : in std_logic; -- start PIO transfer + done : buffer std_logic; -- done with PIO transfer + + PIOa : out unsigned(3 downto 0); -- PIO address, address lines towards ATA devices + PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices + + SelDev : buffer std_logic; -- Selected Device, Dev-bit in ATA Device/Head register + + DDi : in std_logic_vector(15 downto 0); + DDoe : buffer std_logic; + + DIOR : buffer std_logic; + DIOW : buffer std_logic; + IORDY : in std_logic + ); +end entity atahost_pio_controller; + +architecture structural of atahost_pio_controller is + -- + -- component declarations + -- + component atahost_pio_actrl is + generic( + TWIDTH : natural := 8; -- counter width + + -- PIO mode 0 settings (@100MHz clock) + PIO_mode0_T1 : natural := 6; -- 70ns + PIO_mode0_T2 : natural := 28; -- 290ns + PIO_mode0_T4 : natural := 2; -- 30ns + PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240 + ); + port( + clk : in std_logic; -- master clock + nReset : in std_logic; -- asynchronous active low reset + rst : in std_logic; -- synchronous active high reset + + IDEctrl_FATR0, + IDEctrl_FATR1 : in std_logic; + + cmdport_T1, + cmdport_T2, + cmdport_T4, + cmdport_Teoc : in unsigned(7 downto 0); + cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing + + dport0_T1, + dport0_T2, + dport0_T4, + dport0_Teoc : in unsigned(7 downto 0); + dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0 + + dport1_T1, + dport1_T2, + dport1_T4, + dport1_Teoc : in unsigned(7 downto 0); + dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1 + + SelDev : in std_logic; -- Selected device + + go : in std_logic; -- Start transfer sequence + done : out std_logic; -- Transfer sequence done + dir : in std_logic; -- Transfer direction '1'=write, '0'=read + a : in unsigned(3 downto 0); -- PIO transfer address + q : out std_logic_vector(15 downto 0); -- Data read from ATA devices + + DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus + oe : buffer std_logic; -- DDbus output-enable signal + + DIOR, + DIOW : buffer std_logic; + IORDY : in std_logic + ); + end component atahost_pio_actrl; + + -- + -- signals + -- + + -- PIO pingpong signals + signal pp_d : std_logic_vector(15 downto 0); + signal pp_a : unsigned(3 downto 0); + signal pp_we : std_logic; + signal idone : std_logic; + +begin + -- + -- generate selected device + -- + gen_seldev: process(clk, pp_a) + variable Asel : std_logic; -- address selected + begin + Asel := not pp_a(3) and pp_a(2) and pp_a(1) and not pp_a(0); -- header/device register + + if (clk'event and clk = '1') then + if ( (idone = '1') and (Asel = '1') and (pp_we = '1') ) then + SelDev <= pp_d(4); + end if; + end if; + end process gen_seldev; + + -- + -- generate PIO write pingpong system + -- + gen_pingpong: block + signal ping_d, pong_d : std_logic_vector(15 downto 0); + signal ping_a, pong_a : unsigned(3 downto 0); + signal ping_we, pong_we : std_logic; + signal ping_valid, pong_valid : std_logic; + signal dping_valid, dpong_valid : std_logic; + signal wpp, rpp : std_logic; + + signal dsel, sel_strb : std_logic; + + signal iack : std_logic; + begin + -- generate PIO acknowledge + gen_ack: process(clk, ping_valid, dping_valid, pong_valid, dpong_valid, we) + variable ping_re, ping_fe, pong_re, pong_fe : std_logic; + begin + -- detect rising edge of ping_valid and pong_valid + ping_re := ping_valid and not dping_valid and we; + pong_re := pong_valid and not dpong_valid and we; + + -- detect falling edge of ping_valid and pong_valid + ping_fe := not ping_valid and dping_valid; + pong_fe := not pong_valid and dpong_valid; + + if (clk'event and clk = '1') then + if ((pp_we = '1') and (IDEctrl_ppen = '1')) then -- write sequence + if (wpp = '1') then + iack <= ping_re; + else + iack <= pong_re; + end if; + else -- read sequence + if (rpp = '1') then + iack <= ping_fe; + else + iack <= pong_fe; + end if; + end if; + end if; + end process gen_ack; + ack <= (iack or not IDEctrl_IDEen) and sel; -- acknowledge access when not enabled (discard access) + + -- generate select-strobe, hold sel_strb until pingpong system ready for new data + gen_sel_strb: process(clk, nReset) + begin + if (nReset = '0') then + dsel <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + dsel <= '0'; + else + dsel <= sel_strb or (dsel and sel); + end if; + end if; + end process gen_sel_strb; + sel_strb <= sel and not dsel and IDEctrl_IDEen and ((wpp and not ping_valid) or (not wpp and not pong_valid)); + + -- generate pingpong control + gen_pp : process(clk, nReset) + begin + if (nReset = '0') then + wpp <= '0'; + rpp <= '0'; + ping_valid <= '0'; + pong_valid <= '0'; + dping_valid <= '0'; + dpong_valid <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + wpp <= '0'; + rpp <= '0'; + ping_valid <= '0'; + pong_valid <= '0'; + dping_valid <= '0'; + dpong_valid <= '0'; + else + wpp <= (wpp xor (iack and we)) and IDEctrl_ppen; + rpp <= (rpp xor (idone and pp_we)) and IDEctrl_ppen; + ping_valid <= (( wpp and sel_strb) or ping_valid) and not ( rpp and idone); + pong_valid <= ((not wpp and sel_strb) or pong_valid) and not (not rpp and idone); + dping_valid <= ping_valid; + dpong_valid <= pong_valid; + end if; + end if; + end process gen_pp; + + -- generate pingpong full signal + PPFull <= (ping_valid and pong_valid) when (IDEctrl_ppen = '1') else pong_valid; + + -- fill ping/pong registers + fill_pp: process(clk) + begin + if (clk'event and clk = '1') then + if (sel = '1') then + if (wpp = '1') then + if (ping_valid = '0') then + ping_d <= d; + ping_a <= a; + ping_we <= we; + end if; + else + if (pong_valid = '0') then + pong_d <= d; + pong_a <= a; + pong_we <= we; + end if; + end if; + end if; + end if; + end process fill_pp; + + -- multiplex pingpong data to pp_d, pp_a, pp_we + pp_d <= ping_d when (rpp = '1') else pong_d; + pp_a <= ping_a when (rpp = '1') else pong_a; + pp_we <= ping_we when (rpp = '1') else pong_we; + + -- generate PIOreq + PIOreq <= (ping_valid and not idone) when (rpp = '1') else (pong_valid and not idone); + end block gen_pingpong; + + -- + -- Hookup PIO access controller + -- + PIO_access_control: atahost_pio_actrl + generic map( + TWIDTH => TWIDTH, + PIO_mode0_T1 => PIO_mode0_T1, + PIO_mode0_T2 => PIO_mode0_T2, + PIO_mode0_T4 => PIO_mode0_T4, + PIO_mode0_Teoc => PIO_mode0_Teoc + ) + port map( + clk => clk, + nReset => nReset, + rst => rst, + IDEctrl_FATR0 => IDEctrl_FATR0, + IDEctrl_FATR1 => IDEctrl_FATR1, + cmdport_T1 => cmdport_T1, + cmdport_T2 => cmdport_T2, + cmdport_T4 => cmdport_T4, + cmdport_Teoc => cmdport_Teoc, + cmdport_IORDYen => cmdport_IORDYen, + dport0_T1 => dport0_T1, + dport0_T2 => dport0_T2, + dport0_T4 => dport0_T4, + dport0_Teoc => dport0_Teoc, + dport0_IORDYen => dport0_IORDYen, + dport1_T1 => dport1_T1, + dport1_T2 => dport1_T2, + dport1_T4 => dport1_T4, + dport1_Teoc => dport1_Teoc, + dport1_IORDYen => dport1_IORDYen, + SelDev => SelDev, + go => go, + done => idone, + dir => pp_we, + a => pp_a, + q => Q, + DDi => DDi, + oe => DDoe, + DIOR => dior, + DIOW => diow, + IORDY => IORDY + ); + + -- + -- assign outputs + -- + PIOa <= pp_a; + PIOd <= pp_d; + Done <= idone; +end architecture structural; + Index: ata/trunk/bench/verilog/ata_device.v =================================================================== --- ata/trunk/bench/verilog/ata_device.v (nonexistent) +++ ata/trunk/bench/verilog/ata_device.v (revision 33) @@ -0,0 +1,397 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// ATA (IDE) Device Model //// +//// This Model Supports PIO cycles only ! //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ata/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ata_device.v,v 1.2 2002-02-25 06:07:21 rherveille Exp $ +// +// $Date: 2002-02-25 06:07:21 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/16 10:01:05 rudi +// +// - Added Test Bench +// - Added Synthesis scripts for Design Compiler +// - Fixed minor bug in atahost_top +// +// +// +// +// + +`timescale 1ns / 10ps + +module ata_device( ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1, + ata_dior_, ata_diow_, ata_iordy, ata_intrq ); +input ata_rst_; +inout [15:0] ata_data; +input [2:0] ata_da; +input ata_cs0, ata_cs1; +input ata_dior_, ata_diow_; +output ata_iordy; +output ata_intrq; + +integer mode; +integer n; +reg ata_iordy; +reg iordy_enable; +integer iordy_delay; + +reg [15:0] mem[32:0]; +reg [15:0] dout; +reg dout_en; +wire ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4; +wire [4:0] addr; +wire ata_dior, ata_diow; + +initial + begin + dout_en = 0; + mode = 0; + iordy_enable = 0; + iordy_delay = 0; + ata_iordy = 1; + end + +assign ata_dior = !ata_dior_; +assign ata_diow = !ata_diow_; + +assign ata_intrq = 0; + +assign ata_data = dout_en ? dout : 16'hzzzz; + +assign addr = {~ata_cs1, ~ata_cs0, ata_da}; + +always @(posedge ata_rst_) + dout_en = 0; + +always @(posedge ata_dior) + begin + dout = mem[ addr ]; + dout_en = 1; + end + +always @(posedge ata_dior) + begin + dout_en = 0; + end + +always @(posedge ata_diow) + begin + mem[ addr ] = ata_data; + end + +always @(posedge ata_dior or posedge ata_diow) + begin + ata_iordy = 1'b0; + #(iordy_delay); + ata_iordy = 1'b1; + end + +task init_mem; + +begin + +for(n=0;n<32;n=n+1) + mem[n] = n; +end +endtask + +assign ata_rst_m0 = ata_rst_ & (mode==0); +assign ata_rst_m1 = ata_rst_ & (mode==1); +assign ata_rst_m2 = ata_rst_ & (mode==2); +assign ata_rst_m3 = ata_rst_ & (mode==3); +assign ata_rst_m4 = ata_rst_ & (mode==4); + +specify + specparam // ATA Mode 0 Timing + M0_DioCycle = 600, // T0 + M0_AddrSetup = 70, // T1 + M0_DioHigh = 290, // T2 + M0_WrSetup = 60, // T3 + M0_WrHold = 30, // T4 + M0_DoutSetup = 50, // T5 + M0_DoutHold = 5, // T6 + M0_AddrHold = 20, // T9 + + // ATA Mode 1 Timing + M1_DioCycle = 383, // T0 + M1_AddrSetup = 50, // T1 + M1_DioHigh = 290, // T2 + M1_WrSetup = 45, // T3 + M1_WrHold = 20, // T4 + M1_DoutSetup = 35, // T5 + M1_DoutHold = 5, // T6 + M1_AddrHold = 15, // T9 + + // ATA Mode 2 Timing + M2_DioCycle = 330, // T0 + M2_AddrSetup = 30, // T1 + M2_DioHigh = 290, // T2 + M2_WrSetup = 30, // T3 + M2_WrHold = 15, // T4 + M2_DoutSetup = 20, // T5 + M2_DoutHold = 5, // T6 + M2_AddrHold = 10, // T9 + + // ATA Mode 3 Timing + M3_DioCycle = 180, // T0 + M3_AddrSetup = 30, // T1 + M3_DioHigh = 80, // T2 + M3_DioLow = 70, // T2i + M3_WrSetup = 30, // T3 + M3_WrHold = 10, // T4 + M3_DoutSetup = 20, // T5 + M3_DoutHold = 5, // T6 + M3_AddrHold = 10, // T9 + + // ATA Mode 4 Timing + M4_DioCycle = 120, // T0 + M4_AddrSetup = 25, // T1 + M4_DioHigh = 70, // T2 + M4_DioLow = 25, // T2i + M4_WrSetup = 20, // T3 + M4_WrHold = 10, // T4 + M4_DoutSetup = 20, // T5 + M4_DoutHold = 5, // T6 + M4_AddrHold = 10; // T9 + + + + ///////////////////////////////////////////////////// + // ATA Mode 0 Timing // + ///////////////////////////////////////////////////// + + // Output Delay Path + if(mode==0) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) + (0,0, + M0_DoutHold, (M0_DioHigh - M0_DoutSetup), + M0_DoutHold, (M0_DioHigh - M0_DoutSetup) ); + + // Write Data Setup/Hold Check + $setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 ); + + // DioX Active time Check + $width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh ); + $width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh ); + + // DioX Min Cycle Width Check + $period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle ); + $period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle ); + + // Address Setup Hold Checks + $setup(ata_da, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup); + $setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup); + $setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup); + $setup(ata_da, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup); + $setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup); + $setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup); + + $hold(ata_da, negedge ata_dior &&& ata_rst_m0, M0_AddrHold); + $hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold); + $hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold); + $hold(ata_da, negedge ata_diow &&& ata_rst_m0, M0_AddrHold); + $hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold); + $hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold); + + + ///////////////////////////////////////////////////// + // ATA Mode 1 Timing // + ///////////////////////////////////////////////////// + + // Output Delay Path + if(mode==1) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) + (0,0, + M1_DoutHold, (M1_DioHigh - M1_DoutSetup), + M1_DoutHold, (M1_DioHigh - M1_DoutSetup) ); + + // Write Data Setup/Hold Check + $setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 ); + + // DioX Active time Check + $width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh ); + $width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh ); + + // DioX Min Cycle Width Check + $period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle ); + $period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle ); + + // Address Setup Hold Checks + $setup(ata_da, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup); + $setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup); + $setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup); + $setup(ata_da, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup); + $setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup); + $setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup); + + $hold(ata_da, negedge ata_dior &&& ata_rst_m1, M1_AddrHold); + $hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold); + $hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold); + $hold(ata_da, negedge ata_diow &&& ata_rst_m1, M1_AddrHold); + $hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold); + $hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold); + + + ///////////////////////////////////////////////////// + // ATA Mode 2 Timing // + ///////////////////////////////////////////////////// + + // Output Delay Path + if(mode==2) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) + (0,0, + M2_DoutHold, (M2_DioHigh - M2_DoutSetup), + M2_DoutHold, (M2_DioHigh - M2_DoutSetup) ); + + // Write Data Setup/Hold Check + $setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 ); + + // DioX Active time Check + $width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh ); + $width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh ); + + // DioX Min Cycle Width Check + $period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle ); + $period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle ); + + // Address Setup Hold Checks + $setup(ata_da, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup); + $setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup); + $setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup); + $setup(ata_da, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup); + $setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup); + $setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup); + + $hold(ata_da, negedge ata_dior &&& ata_rst_m2, M2_AddrHold); + $hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold); + $hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold); + $hold(ata_da, negedge ata_diow &&& ata_rst_m2, M2_AddrHold); + $hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold); + $hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold); + + ///////////////////////////////////////////////////// + // ATA Mode 3 Timing // + ///////////////////////////////////////////////////// + + // Output Delay Path + if(mode==3) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) + (0,0, + M3_DoutHold, (M3_DioHigh - M3_DoutSetup), + M3_DoutHold, (M3_DioHigh - M3_DoutSetup) ); + + // Write Data Setup/Hold Check + $setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 ); + + // DioX Active time Check + $width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh ); + $width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh ); + + $width(negedge ata_dior &&& ata_rst_m3, M3_DioLow ); + $width(negedge ata_diow &&& ata_rst_m3, M3_DioLow ); + + // DioX Min Cycle Width Check + $period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle ); + $period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle ); + + // Address Setup Hold Checks + $setup(ata_da, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup); + $setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup); + $setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup); + $setup(ata_da, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup); + $setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup); + $setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup); + + $hold(ata_da, negedge ata_dior &&& ata_rst_m3, M3_AddrHold); + $hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold); + $hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold); + $hold(ata_da, negedge ata_diow &&& ata_rst_m3, M3_AddrHold); + $hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold); + $hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold); + + + ///////////////////////////////////////////////////// + // ATA Mode 4 Timing // + ///////////////////////////////////////////////////// + + // Output Delay Path + if(mode==4) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0) + (0,0, + M4_DoutHold, (M4_DioHigh - M4_DoutSetup), + M4_DoutHold, (M4_DioHigh - M4_DoutSetup) ); + + // Write Data Setup/Hold Check + $setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 ); + + // DioX Active time Check + $width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh ); + $width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh ); + + $width(negedge ata_dior &&& ata_rst_m4, M4_DioLow ); + $width(negedge ata_diow &&& ata_rst_m4, M4_DioLow ); + + // DioX Min Cycle Width Check + $period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle ); + $period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle ); + + // Address Setup Hold Checks + $setup(ata_da, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup); + $setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup); + $setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup); + $setup(ata_da, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup); + $setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup); + $setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup); + + $hold(ata_da, negedge ata_dior &&& ata_rst_m4, M4_AddrHold); + $hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold); + $hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold); + $hold(ata_da, negedge ata_diow &&& ata_rst_m4, M4_AddrHold); + $hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold); + $hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold); + + + +endspecify + + +endmodule + + Index: ata/trunk/bench/verilog/test_bench_top.v =================================================================== --- ata/trunk/bench/verilog/test_bench_top.v (nonexistent) +++ ata/trunk/bench/verilog/test_bench_top.v (revision 33) @@ -0,0 +1,270 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Top Level Test Bench //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: test_bench_top.v,v 1.2 2002-02-16 10:41:16 rherveille Exp $ +// +// $Date: 2002-02-16 10:41:16 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/16 10:01:05 rudi +// +// - Added Test Bench +// - Added Synthesis scripts for Design Compiler +// - Fixed minor bug in atahost_top +// +// +// +// +// + +`timescale 1ns / 10ps + +module test; + +reg clk; +reg rst; + +wire int; +wire [31:0] wb_addr_i; +wire [31:0] wb_data_i; +wire [31:0] wb_data_o; +wire [3:0] wb_sel_i; +wire wb_we_i; +wire wb_stb_i; +wire wb_cyc_i; +wire wb_ack_o; +wire wb_err_o; + +wire ata_rst_; +wire [15:0] ata_dout; +wire [15:0] ata_din; +wire [15:0] ata_data; +wire ata_doe; +wire [2:0] ata_da; +wire ata_cs0, ata_cs1; +wire ata_dior, ata_diow; +wire ata_iordy; +wire ata_intrq; +reg ata_intrq_r; + + +// Test Bench Variables +integer wd_cnt; +integer error_cnt; +integer verbose; + +// Misc Variables + +///////////////////////////////////////////////////////////////////// +// +// Defines +// + +`define CTRL 32'h0000_0000 +`define STAT 32'h0000_0004 +`define PCTR 32'h0000_0008 +`define ATA_DEV 32'h0000_0040 + +///////////////////////////////////////////////////////////////////// +// +// Simulation Initialization and Start up Section +// + +initial + begin + $display("\n\n"); + $display("******************************************************"); + $display("* WISHBONE ATA 1 Controller Simulation started ... *"); + $display("******************************************************"); + $display("\n"); +`ifdef WAVES + $shm_open("waves"); + $shm_probe("AS",test,"AS"); + $display("INFO: Signal dump enabled ...\n\n"); +`endif + wd_cnt = 0; + error_cnt = 0; + clk = 0; + rst = 0; + verbose = 1; + ata_intrq_r=0; + + repeat(10) @(posedge clk); + rst = 1; + repeat(10) @(posedge clk); + + // HERE IS WHERE THE TEST CASES GO ... + +if(1) // Full Regression Run + begin + io_test1; + io_test2; + int_test; + rst_test; + + end +else + begin + + // + // TEST DEVELOPMENT AREA + // +$display("\n\n"); +$display("*****************************************************"); +$display("*** DEVELOPMENT Test ***"); +$display("*****************************************************\n"); + + + + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + + end + repeat(100) @(posedge clk); + $finish; + end + +///////////////////////////////////////////////////////////////////// +// +// System Clock (100Mhz) +// + +always #5 clk = ~clk; + +///////////////////////////////////////////////////////////////////// +// +// Watchdog Counter +// Terminate simulation if nothing happens ... +// + +always @(wb_cyc_i or wb_ack_o) + wd_cnt <= #5 0; + +always @(posedge clk) + wd_cnt <= #1 wd_cnt + 1; + +always @(wd_cnt) + if(wd_cnt>5000) + begin + $display("\n\n*************************************\n"); + $display("ERROR: Watch Dog Counter Expired\n"); + $display("*************************************\n\n\n"); + $finish; + end + +///////////////////////////////////////////////////////////////////// +// +// DUT & Models +// + +// Create an external Tri-State Bus to the ATA Device +assign ata_din = ata_data; +assign ata_data = ata_doe ? ata_dout : 16'hzzzz; + +// DUT: ATA Host +atahost_top u0( //-- WISHBONE SYSCON signals + .wb_clk_i( clk ), + .arst_i( rst ), + .wb_rst_i( ~rst ), + + //-- WISHBONE SLAVE signals + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( wb_ack_o ), + .wb_err_o( wb_err_o ), + .wb_adr_i( wb_addr_i[6:2] ), + .wb_dat_i( wb_data_i ), + .wb_dat_o( wb_data_o ), + .wb_sel_i( wb_sel_i ), + .wb_we_i( wb_we_i ), + .wb_inta_o( int ), + + //-- ATA signals + .resetn_pad_o( ata_rst_ ), + .dd_pad_i( ata_din ), + .dd_pad_o( ata_dout ), + .dd_padoe_o( ata_doe ), + .da_pad_o( ata_da ), + .cs0n_pad_o( ata_cs0 ), + .cs1n_pad_o( ata_cs1 ), + .diorn_pad_o( ata_dior_ ), + .diown_pad_o( ata_diow_ ), + .iordy_pad_i( ata_iordy ), + .intrq_pad_i( ata_intrq_r ) + ); + +// ATA Device Model +ata_device a0( .ata_rst_( ata_rst_ ), + .ata_data( ata_data ), + .ata_da( ata_da ), + .ata_cs0( ata_cs0 ), + .ata_cs1( ata_cs1 ), + .ata_dior_( ata_dior_ ), + .ata_diow_( ata_diow_ ), + .ata_iordy( ata_iordy ), + .ata_intrq( ata_intrq ) ); + +// WISHBONE Master Model +wb_mast m0( .clk( clk ), + .rst( rst ), + .adr( wb_addr_i ), + .din( wb_data_o ), + .dout( wb_data_i ), + .cyc( wb_cyc_i ), + .stb( wb_stb_i ), + .sel( wb_sel_i ), + .we( wb_we_i ), + .ack( wb_ack_o ), + .err( wb_err_o ), + .rty( 1'b0 ) ); + +// External Tests +`include "tests.v" + +endmodule + + Index: ata/trunk/bench/verilog/wb_mast_model.v =================================================================== --- ata/trunk/bench/verilog/wb_mast_model.v (nonexistent) +++ ata/trunk/bench/verilog/wb_mast_model.v (revision 33) @@ -0,0 +1,631 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Master Model //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_mast_model.v,v 1.1 2001-08-16 10:01:05 rudi Exp $ +// +// $Date: 2001-08-16 10:01:05 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// + +/* + +task mem_fill; + +- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values. + + +task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data); + +- Performs a single WISHBONE write + + +task wb_wr4( 32 bit address, 4 bit byte select, integer delay, + 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); + +- Performs 4 consecutive WISHBONE writes +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay, + integer count); + +- Simular to wb_wr4, except it pwrforms "count" number of write cycles. + The data is taken from the internal wr_bub[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rmw( 32 bit address, 4 bit byte select, integer delay, + integer rcount, integer wcount); + +- This task performs "rcount" read cycles, followed by wcount write cycles. +- read data is placed in to the internal rd_buf[] memory, write data is + taken from the internal wr_buf[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data); + +- Performs a single WISHBONE write + + +task wb_rd4( 32 bit address, 4 bit byte select, integer delay, + 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); + +- Performs 4 consecutive WISHBONE reads +- Strobe is deasserted between reads for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay, + integer count); + +- Simular to wb_rd4, except it pwrforms "count" number of read cycles. + The data is read in to the internal rd_buf[] memory. +- Strobe is deasserted between reads for 'delay' number of cycles + (This simulates wait state insertion ...) + + +*/ + + +`include "wb_model_defines.v" + +module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +output [31:0] adr; +input [31:0] din; +output [31:0] dout; +output cyc, stb; +output [3:0] sel; +output we; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter mem_size = 4096; + +reg [31:0] adr; +reg [31:0] dout; +reg cyc, stb; +reg [3:0] sel; +reg we; + +reg [31:0] rd_mem[mem_size:0]; +reg [31:0] wr_mem[mem_size:0]; +integer rd_cnt; +integer wr_cnt; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + adr = 32'hxxxx_xxxx; + dout = 32'hxxxx_xxxx; + cyc = 0; + stb = 0; + sel = 4'hx; + we = 1'hx; + rd_cnt = 0; + wr_cnt = 0; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + + + +task mem_fill; + +integer n; +begin +rd_cnt = 0; +wr_cnt = 0; +for(n=0;n(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +The parameter "mem_addr_bus_width" indicates the size of the memory by +specifiying the number of address lines to the memory. + +task fill_mem(mode); +- This task initializes the internal memory. + If mode is 0, the memory is initialized to { ~address[15:0], address[15:0] }; + If mode is 1, the memory is initialized to random values. + + +The internal register "delay" specifies how fast ack is generated by the slave. +A value of 0 indicated immediatly, a value of 1 1 cycle delay etc. +It can be accesset by: +.delay = 5 bit value + +*/ + +`include "wb_model_defines.v" + +module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +input [31:0] adr, din; +output [31:0] dout; +input cyc, stb; +input [3:0] sel; +input we; +output ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter mem_size = 13; +parameter sz = (1<>> Running Read Only test 1 ... (%0t)", $time); + for(n=0;n<16;n=n+1) + begin + m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); + if(data[15:0] != (n+8) ) + begin + $display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)", + (n+8), data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 1 ... (%0t)", $time); + + for(n=0;n<16;n=n+1) + begin + m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] ); + if(a0.mem[n+8] != ~n[15:0] ) + begin + $display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)", + ~n[15:0], a0.mem[n+8], $time); + error_cnt = error_cnt + 1; + end + end + + for(n=0;n<16;n=n+1) + begin + m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); + if(data[15:0] != ~n[15:0] ) + begin + $display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)", + ~n[15:0], data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 2 ... (%0t)", $time); + + for(n=0;n<16;n=n+1) + begin + m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] ); + m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); + if(data[15:0] != n[15:0] ) + begin + $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", + n[15:0], data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 3 ... (%0t)", $time); + + for(n=0;n<16;n=n+4) + begin + m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del, + {16'h0, ~n[13:0], 2'h3}, + {16'h0, ~n[13:0], 2'h2}, + {16'h0, ~n[13:0], 2'h1}, + {16'h0, ~n[13:0], 2'h0} ); + + m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 ); + + if( (data[15:0] != {~n[13:0], 2'h3}) | + (data1[15:0] != {~n[13:0], 2'h2}) | + (data2[15:0] != {~n[13:0], 2'h1}) | + (data3[15:0] != {~n[13:0], 2'h0}) ) + begin + $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", + n[15:0], data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time); + + a0.init_mem; + + for(n=0;n<16;n=n+1) + begin + m0.wr_mem[n] = n[15:0]; + m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1); + data = m0.rd_mem[n]; + + data2[15:0] = n[15:0] + 8; + + data1 = a0.mem[n+8]; + data3 = n[15:0]; + + if( (data[15:0] != data2[15:0] ) | + (data1[15:0] != data3[15:0]) ) + begin + $display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)", + data2[15:0], data[15:0], $time); + $display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)", + data1[15:0], data3[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + end +end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + +task io_test2; + +reg [31:0] data; +reg [31:0] data1; +reg [31:0] data2; +reg [31:0] data3; +integer n; +integer id; +integer del; +integer del_max; +integer pio_mode; +integer iordy_del; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** IO Test 2 ***"); +$display("*** Testing PIO Modes, iordy assertion and ***"); +$display("*** iordy delays. ***"); +$display("*****************************************************\n"); + +id = 0; +del = 1; +verbose = 0; +iordy_del = 0; +pio_mode=4; + +for(pio_mode=0;pio_mode<5;pio_mode=pio_mode+1) +for(id=0;id<2;id=id+1) +begin + if(!verbose) + $display("*** MODE SELECT: PIO mode: %0d iordy enable: %0d", pio_mode, id); + +for(iordy_del=0;iordy_del < (id ? 600 : 1); iordy_del=iordy_del+1) + begin + + if(verbose) + $display("*** MODE SELECT: PIO mode: %0d, 'iordy' enable: %0d iordy del: %0d\n", + pio_mode, id, iordy_del ); + + a0.mode = pio_mode; + a0.iordy_enable = id; + a0.iordy_delay = iordy_del; // Delay in nS + a0.init_mem; + + data1 = 32'h0000_0001; + m0.wb_wr1( `CTRL, 4'hf, data1); + m0.wb_rd1( `CTRL, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + data1 = 32'h1000_0000; + m0.wb_rd1( `STAT, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: STAT Register read Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + case(pio_mode) + 0: data1 = {8'h18, 8'h02, 8'h1c, 8'h04}; // Teoc, T4, T2, T1 + 1: data1 = {8'h05, 8'h01, 8'h1c, 8'h02}; // Teoc, T4, T2, T1 + 2: data1 = {8'h01, 8'h01, 8'h1c, 8'h00}; // Teoc, T4, T2, T1 + 3: data1 = {8'h07, 8'h00, 8'h07, 8'h00}; // Teoc, T4, T2, T1 + 4: data1 = {8'h02, 8'h00, 8'h06, 8'h00}; // Teoc, T4, T2, T1 + endcase + m0.wb_wr1( `PCTR, 4'hf, data1); + m0.wb_rd1( `PCTR, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: PCTR Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + if(id==1) data1 = 32'h0000_0082; + else data1 = 32'h0000_0080; + m0.wb_wr1( `CTRL, 4'hf, data1); + m0.wb_rd1( `CTRL, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + repeat(10) @(posedge clk); + + // Read only Test of ATA registers + if(verbose) $display(">>> Running Read Only test 1 ... (%0t)", $time); + for(n=0;n<16;n=n+1) + begin + m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); + if(data[15:0] != (n+8) ) + begin + $display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)", + (n+8), data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 1 ... (%0t)", $time); + + for(n=0;n<16;n=n+1) + begin + m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] ); + if(a0.mem[n+8] != ~n[15:0] ) + begin + $display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)", + ~n[15:0], a0.mem[n+8], $time); + error_cnt = error_cnt + 1; + end + end + + for(n=0;n<16;n=n+1) + begin + m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); + if(data[15:0] != ~n[15:0] ) + begin + $display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)", + ~n[15:0], data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 2 ... (%0t)", $time); + + for(n=0;n<16;n=n+1) + begin + m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] ); + m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data ); + if(data[15:0] != n[15:0] ) + begin + $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", + n[15:0], data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 3 ... (%0t)", $time); + + for(n=0;n<16;n=n+4) + begin + m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del, + {16'h0, ~n[13:0], 2'h3}, + {16'h0, ~n[13:0], 2'h2}, + {16'h0, ~n[13:0], 2'h1}, + {16'h0, ~n[13:0], 2'h0} ); + + m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 ); + + if( (data[15:0] != {~n[13:0], 2'h3}) | + (data1[15:0] != {~n[13:0], 2'h2}) | + (data2[15:0] != {~n[13:0], 2'h1}) | + (data3[15:0] != {~n[13:0], 2'h0}) ) + begin + $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)", + n[15:0], data[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + + // Write Then Read Test of ATA registers + if(verbose) $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time); + + a0.init_mem; + + for(n=0;n<16;n=n+1) + begin + m0.wr_mem[n] = n[15:0]; + m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1); + data = m0.rd_mem[n]; + + data2[15:0] = n[15:0] + 8; + + data1 = a0.mem[n+8]; + data3 = n[15:0]; + + if( (data[15:0] != data2[15:0] ) | + (data1[15:0] != data3[15:0]) ) + begin + $display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)", + data2[15:0], data[15:0], $time); + $display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)", + data1[15:0], data3[15:0], $time); + error_cnt = error_cnt + 1; + end + end + if(verbose) $display(""); + + end +end + + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + + +task rst_test; +reg [31:0] data; +reg [31:0] data1; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** RST Test ***"); +$display("*** ***"); +$display("*****************************************************\n"); + + + a0.iordy_enable = 0; + a0.iordy_delay = 0; // Delay in nS + a0.init_mem; + + data1 = 32'h0000_0080; + m0.wb_wr1( `CTRL, 4'hf, data1); + m0.wb_rd1( `CTRL, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + m0.wb_rd1( `STAT, 4'hf, data ); + m0.wb_rd1( `PCTR, 4'hf, data ); + + if(ata_rst_ !== 1'b1) + begin + $display("ERROR: ATA Reset not deasserted ... (%0t)", $time); + error_cnt = error_cnt + 1; + end + repeat(500) @(posedge clk); + + data1[0] = 1; + m0.wb_wr1( `CTRL, 4'hf, data1); + m0.wb_rd1( `CTRL, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + repeat(100) + begin + if(ata_rst_ !== 1'b0) + begin + $display("ERROR: ATA Reset not asserted ... (%0t)", $time); + error_cnt = error_cnt + 1; + end + + @(posedge clk); + end + + data1[0] = 0; + m0.wb_wr1( `CTRL, 4'hf, data1); + m0.wb_rd1( `CTRL, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + if(ata_rst_ !== 1'b1) + begin + $display("ERROR: ATA Reset not deasserted ... (%0t)", $time); + error_cnt = error_cnt + 1; + end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + + +task int_test; +reg [31:0] data; +reg [31:0] data1; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** INT Test ***"); +$display("*** ***"); +$display("*****************************************************\n"); + + a0.iordy_enable = 0; + a0.iordy_delay = 0; + a0.init_mem; + + data1 = 32'h0000_0080; + m0.wb_wr1( `CTRL, 4'hf, data1); + m0.wb_rd1( `CTRL, 4'hf, data ); + if(data != data1 ) + begin + $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)", + data1, data, $time); + error_cnt = error_cnt + 1; + end + + // No interrupts at this point + m0.wb_rd1( `STAT, 4'hf, data ); + data1 = 32'h1000_0000; + if(data !== data1) + begin + $display("ERROR: ATA STATUS mismatch (1), Expected: %0h Got: %0h (%0t)", $time, data1, data); + error_cnt = error_cnt + 1; + end + + repeat(20) @(posedge clk); + + + // No interrupts at this point + m0.wb_rd1( `STAT, 4'hf, data ); + data1 = 32'h1000_0000; + if(data !== data1) + begin + $display("ERROR: ATA STATUS mismatch (2), Expected: %0h Got: %0h (%0t)", $time, data1, data); + error_cnt = error_cnt + 1; + end + + // Assert Interrup + ata_intrq_r = 1; + repeat(10) @(posedge clk); + ata_intrq_r = 0; + + + // Check to see if int bit is set + m0.wb_rd1( `STAT, 4'hf, data ); + data1 = 32'h1000_0001; + if(data !== data1) + begin + $display("ERROR: ATA STATUS mismatch (3), Expected: %0h Got: %0h (%0t)", data1, data, $time); + error_cnt = error_cnt + 1; + end + + repeat(10) @(posedge clk); + + // Make sure it is not cleared after another read + m0.wb_rd1( `STAT, 4'hf, data ); + data1 = 32'h1000_0001; + if(data !== data1) + begin + $display("ERROR: ATA STATUS mismatch (4), Expected: %0h Got: %0h (%0t)", data1, data, $time); + error_cnt = error_cnt + 1; + end + + // Clear interrupt + data1 = 32'h0000_0000; + m0.wb_wr1( `STAT, 4'hf, data1 ); + + + // Should be cleared now ... + m0.wb_rd1( `STAT, 4'hf, data ); + data1 = 32'h1000_0000; + if(data !== data1) + begin + $display("ERROR: ATA STATUS mismatch (5), Expected: %0h Got: %0h (%0t)", data1, data, $time); + error_cnt = error_cnt + 1; + end + + // Check again .... + m0.wb_rd1( `STAT, 4'hf, data ); + data1 = 32'h1000_0000; + if(data !== data1) + begin + $display("ERROR: ATA STATUS mismatch (6), Expected: %0h Got: %0h (%0t)", data1, data, $time); + error_cnt = error_cnt + 1; + end + + repeat(100) @(posedge clk); + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); + +end +endtask + + Index: ata/trunk/bench/verilog/wb_model_defines.v =================================================================== --- ata/trunk/bench/verilog/wb_model_defines.v (nonexistent) +++ ata/trunk/bench/verilog/wb_model_defines.v (revision 33) @@ -0,0 +1,52 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Model Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_model_defines.v,v 1.1 2001-08-16 10:01:05 rudi Exp $ +// +// $Date: 2001-08-16 10:01:05 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// + +`timescale 1ns / 10ps Index: ata/trunk/doc/preliminary_ata_core.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ata/trunk/doc/preliminary_ata_core.pdf =================================================================== --- ata/trunk/doc/preliminary_ata_core.pdf (nonexistent) +++ ata/trunk/doc/preliminary_ata_core.pdf (revision 33)

ata/trunk/doc/preliminary_ata_core.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ata/trunk/doc/src/ata_core.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ata/trunk/doc/src/ata_core.doc =================================================================== --- ata/trunk/doc/src/ata_core.doc (nonexistent) +++ ata/trunk/doc/src/ata_core.doc (revision 33)

ata/trunk/doc/src/ata_core.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ata/trunk/sim/rtl_sim/bin/Makefile =================================================================== --- ata/trunk/sim/rtl_sim/bin/Makefile (nonexistent) +++ ata/trunk/sim/rtl_sim/bin/Makefile (revision 33) @@ -0,0 +1,121 @@ + +all: sim +SHELL = /bin/sh +MS="-s" + +########################################################################## +# +# DUT Sources +# +########################################################################## +DUT_SRC_DIR=../../../rtl/verilog +_TARGETS_= $(DUT_SRC_DIR)/ocidec-1/atahost_controller.v \ + $(DUT_SRC_DIR)/ocidec-1/atahost_top.v \ + $(DUT_SRC_DIR)/ocidec-1/atahost_pio_tctrl.v \ + $(DUT_SRC_DIR)/ocidec-1/ro_cnt.v \ + $(DUT_SRC_DIR)/ocidec-1/ud_cnt.v + +########################################################################## +# +# Test Bench Sources +# +########################################################################## +_TOP_=test +TB_SRC_DIR=../../../bench/verilog +_TB_= $(TB_SRC_DIR)/test_bench_top.v \ + $(TB_SRC_DIR)/ata_device.v \ + $(TB_SRC_DIR)/wb_mast_model.v + +########################################################################## +# +# Misc Variables +# +########################################################################## + +INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ocidec-1/ -INCDIR ./$(TB_SRC_DIR)/" +LOGF=-LOGFILE .nclog +NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT + +########################################################################## +# +# Make Targets +# +########################################################################## +simw: + @$(MAKE) -s sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" + +ss: + signalscan -do waves/waves.do -waves waves/waves.trn & + +simxl: + verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \ + $(_TARGETS_) $(_TB_) + +sim: + @echo "" + @echo "----- Running NCVLOG ... ----------" + @$(MAKE) $(MS) vlog \ + TARGETS="$(_TARGETS_)" \ + TB="$(_TB_)" \ + INCDIR=$(INCDIR) \ + WAVES="$(WAVES)" + @echo "" + @echo "----- Running NCELAB ... ----------" + @$(MAKE) $(MS) elab \ + ACCESS="$(ACCESS)" TOP=$(_TOP_) + @echo "" + @echo "----- Running NCSIM ... ----------" + @$(MAKE) $(MS) ncsim TOP=$(_TOP_) + @echo "" + +hal: + @echo "" + @echo "----- Running HAL ... ----------" + @hal +incdir+$(DUT_SRC_DIR)/ocidec-1/ \ + -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ + $(_TARGETS_) + @echo "----- DONE ... ----------" + +clean: + rm -rf ./waves/*.dsn ./waves/*.trn \ + ncwork/.inc* ncwork/inc* \ + ./verilog.* .nclog hal.log + +########################################################################## +# +# NCVLOG +# +########################################################################## + +vhdl: + ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK count -V93 hdl/counter.vhd + ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK work -V93 $(TARGETS) + +vlog: + ncvlog $(NCCOMMON) $(LOGF) \ + -WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR) + +########################################################################## +# +# NCELAB +# +########################################################################## + +elab: + ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -WORK work $(ACCESS) -NOTIMINGCHECKS \ + work.$(TOP) + +########################################################################## +# +# NCSIM +# +########################################################################## + +ncsim: + ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ + -EXIT -ERRORMAX 10 work.$(TOP) + +

ata/trunk/sim/rtl_sim/bin/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ata/trunk/syn/bin/read.dc =================================================================== --- ata/trunk/syn/bin/read.dc (nonexistent) +++ ata/trunk/syn/bin/read.dc (revision 33) @@ -0,0 +1,66 @@ +############################################################################### +# +# Pre Synthesis Script +# +# This script only reads in the design and saves it in a DB file +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_pre.log" +append pre_comp_db_file ../out/$design_name "_pre.db" + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Analyzing all design files ..." >> $log_file + +foreach module $design_files { + echo "+++++++++ Reading: $module" >> $log_file + echo +++++++++ Reading: $module + set module_file_name "" + append module_file_name $module ".v" + analyze -f verilog $module_file_name >> $log_file + elaborate $module >> $log_file + } + +current_design $active_design + +echo "+++++++++ Linking Design ..." >> $log_file +link >> $log_file + +echo "+++++++++ Uniquifying Design ..." >> $log_file +uniquify >> $log_file + +echo "+++++++++ Checking Design ..." >> $log_file +check_design >> $log_file + +# ============================================== +# Save Design +echo "+++++++++ Saving Design ..." >> $log_file +write_file -hierarchy -format db -output $pre_comp_db_file + Index: ata/trunk/syn/bin/comp.dc =================================================================== --- ata/trunk/syn/bin/comp.dc (nonexistent) +++ ata/trunk/syn/bin/comp.dc (revision 33) @@ -0,0 +1,120 @@ +############################################################################### +# +# Actual Synthesis Script +# +# This script does the actual synthesis +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_cmp.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +append post_comp_db_file ../out/$design_name ".db" +append post_syn_verilog_file ../out/$design_name "_ps.v" +set junk_file /dev/null + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Reading Design ..." >> $log_file +read_file $pre_comp_db_file >> $log_file + +# ============================================== +# Operating conditions + +echo "+++++++++ Setting up Operation Conditions ..." >> $log_file +current_design $design_name +set_operating_conditions WORST >> $log_file + +# Turn off automatic wire load selection, as this +# always (WHY ???) defaults to "zero_load" +#set auto_wire_load_selection false +#set_wire_load_mode enclosed >> $log_file +#set_wire_load_mode top >> $log_file +#set_wire_load_model -name suggested_40K >> $log_file + +# ============================================== +# Setup Clocks and Resets + +echo "+++++++++ Setting up Clocks ..." >> $log_file + +set_drive 0 [find port {*clk*}] + +# !!! WISHBONE Clock !!! +set clock_period 5 +create_clock -period $clock_period wb_clk_i +set_clock_skew -uncertainty 0.1 wb_clk_i +set_clock_transition 0.5 wb_clk_i +set_dont_touch_network wb_clk_i + +# !!! Reset !!! +set_drive 0 [find port {*rst*}] +set_dont_touch_network [find port {*rst*}] + +# ============================================== +# Setup IOs + +echo "+++++++++ Setting up IOs ..." >> $log_file + +set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file +set_load 0.2 [all_outputs] + +set_input_delay -max 1 -clock wb_clk_i [all_inputs] +set_output_delay -max 1 -clock wb_clk_i [all_outputs] + +# ============================================== +# Setup Area Constrains +set_max_area 0.0 + +# ============================================== +# Force Ultra +set_ultra_optimization -f + +# ============================================== +# Compile Design + +echo "+++++++++ Starting Compile ..." >> $log_file +compile -map_effort medium -area_effort medium -ungroup_all >> $log_file +#compile -map_effort low -area_effort low >> $log_file +#compile -map_effort high -area_effort high -ungroup_all >> $log_file +#compile -map_effort high -area_effort high -auto_ungroup >> $log_file + +# ============================================== +# Write Out the optimized design + +echo "+++++++++ Saving Optimized Design ..." >> $log_file +write_file -format verilog -output $post_syn_verilog_file +write_file -hierarchy -format db -output $post_comp_db_file + +# ============================================== +# Create Some Basic Reports + +echo "+++++++++ Reporting Final Results ..." >> $log_file +report_timing -nworst 10 >> $log_file +report_area >> $log_file + + Index: ata/trunk/syn/bin/lib_spec.dc =================================================================== --- ata/trunk/syn/bin/lib_spec.dc (nonexistent) +++ ata/trunk/syn/bin/lib_spec.dc (revision 33) @@ -0,0 +1,36 @@ +############################################################################### +# +# Library Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Libraries + +set search_path [list $search_path . \ + /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ + $hdl_src_dir] + +set snps [getenv "SYNOPSYS"] + +set synthetic_library "" +append synthetic_library $snps "/libraries/syn/dw01.sldb " +append synthetic_library $snps "/libraries/syn/dw02.sldb " +append synthetic_library $snps "/libraries/syn/dw03.sldb " +append synthetic_library $snps "/libraries/syn/dw04.sldb " +append synthetic_library $snps "/libraries/syn/dw05.sldb " +append synthetic_library $snps "/libraries/syn/dw06.sldb " +append synthetic_library $snps "/libraries/syn/dw07.sldb " + +set target_library { umcl18u250t2_typ.db } +set link_library "" +append link_library $target_library " " $synthetic_library +set symbol_library { umcl18u250t2.sdb } + Index: ata/trunk/syn/bin/design_spec.dc =================================================================== --- ata/trunk/syn/bin/design_spec.dc (nonexistent) +++ ata/trunk/syn/bin/design_spec.dc (revision 33) @@ -0,0 +1,26 @@ +############################################################################### +# +# Design Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters + +set design_files {ud_cnt ro_cnt atahost_pio_tctrl atahost_controller atahost_top} + +set design_name atahost_top +set active_design atahost_top + +# Next Statement defines all clocks and resets in the design +set special_net {wb_rst_i rst_nreset_i wb_clk_i} + +set hdl_src_dir ../../rtl/verilog/ocidec-1/ + Index: ata/trunk =================================================================== --- ata/trunk (nonexistent) +++ ata/trunk (revision 33)

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