OpenCores
URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 32 to Rev 33
    ↔ Reverse comparison
  •

Rev 32 → Rev 33

/trunk/tx_engine/byte_counter.v
1,12 → 1,12
module byte_count_module(CLK, RESET, START, PARALLEL_CNT, BYTE_COUNTER);
module byte_count_module(CLK, RESET, START, BYTE_COUNTER);
 
// Ports declaration
input CLK;
input RESET;
input START;
input PARALLEL_CNT;
 
 
 
output [15:0] BYTE_COUNTER;
 
reg [15:0] BYTE_COUNTER;
20,18 → 20,12
 
// the ack is delayed which starts the counter
else if (START == 1) begin
if (PARALLEL_CNT) begin
counter = counter + 8;
end
else begin
counter = counter + 1;
end
counter = counter + 8;
end
 
BYTE_COUNTER = counter;
end
 
always @(counter) begin
BYTE_COUNTER = counter;
end
 
endmodule // End of Module
 
/trunk/tx_engine/TransmitTop.v
15,6 → 15,7
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
50,7 → 51,8
input TX_CFG_REG_VALID;
 
//output to stat register
output [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
output TX_STATS_VALID;
output [24:0] TXSTATREGPLUS; // a pulse for each reg for stats
 
//output to user logic
output TX_ACK; //Generated by a counter
109,6 → 111,7
 
parameter PAUSE_FRAME_LENGTH = 8'h02;
 
 
//need a parameter for min frame gap.
 
//Link fault signalling
122,83 → 125,131
/////////////////////////////////////////////////////////////////////////////
 
 
reg [15:0] length_register;
wire [15:0] BYTE_COUNTER;
reg PARALLEL_CNT;
 
wire [31:0] CRC_32_64;
wire [31:0] CRC_OUT;
 
reg [31:0] CRC_OUT_REG;
wire TX_ACK;
 
reg error_flag_int;
reg insert_error;
reg [63:0] tx_data_int;
reg [24:0] TXSTATREGPLUS;
 
reg TX_STATS_VALID;
 
reg FRAME_START;
 
wire reset_int;
 
reg [15:0] DELAY_ACK;
 
reg [7:0] TX_DATA_VALID_REG;
reg [7:0] TX_DATA_VALID_DEL1;
reg [7:0] TX_DATA_VALID_DEL2;
reg [7:0] TX_DATA_VALID_DEL3;
reg [7:0] TX_DATA_VALID_DEL4;
reg [7:0] TX_DATA_VALID_DEL5;
reg [7:0] TX_DATA_VALID_DEL6;
reg [7:0] TX_DATA_VALID_DEL7;
reg [7:0] TX_DATA_VALID_DEL8;
reg [7:0] TX_DATA_VALID_DEL9;
reg [7:0] TX_DATA_VALID_DEL10;
reg [7:0] TX_DATA_VALID_DEL11;
reg [7:0] TX_DATA_VALID_DEL12;
reg [7:0] TX_DATA_VALID_DEL13;
reg [7:0] TX_DATA_VALID_DEL14;
reg [7:0] TX_DATA_VALID_DEL15;
 
reg [63:0] TX_DATA_DEL1;
reg [63:0] TX_DATA_DEL2;
reg [63:0] TX_DATA_DEL3;
reg [63:0] TX_DATA_DEL4;
reg [63:0] TX_DATA_DEL5;
reg [63:0] TX_DATA_DEL6;
reg [63:0] TX_DATA_DEL7;
reg [63:0] TX_DATA_DEL8;
reg [63:0] TX_DATA_DEL9;
reg [63:0] TX_DATA_DEL10;
reg [63:0] TX_DATA_DEL11;
reg [63:0] TX_DATA_DEL12;
reg [63:0] TX_DATA_DEL13;
reg [63:0] TX_DATA_DEL14;
reg [63:0] TX_DATA_DEL15;
 
reg [7:0] OVERFLOW_VALID;
reg [63:0] OVERFLOW_DATA;
 
reg [63:0] TXD;
reg [7:0] TXC;
reg start_CRC8;
 
reg [7:0] TX_DATA_VALID_REG;
reg [63:0] TX_DATA_REG;
reg [63:0] TX_DATA_REG, TX_DATA_VALID_DELAY;
 
wire [31:0] CRC_32_64;
 
reg [15:0] DELAY_ACK;
wire [15:0] BYTE_COUNTER;
 
wire TX_ACK;
reg frame_start_del;
 
reg FRAME_START;
reg transmit_pause_frame_del, transmit_pause_frame_del2, transmit_pause_frame, append_start_pause, append_start_pause_del , transmit_pause_frame_valid, reset_err_pause, load_CRC8, transmit_pause_frame_del3;
 
reg [63:0] TXD_DEL1;
reg [63:0] TXD_DEL2;
reg [63:0] TXD_DEL3;
reg [63:0] TXD_DEL4;
reg [63:0] TXD_DEL5;
reg [63:0] TXD_DEL6;
reg [63:0] TXD_DEL7;
reg [63:0] TXD_DEL8;
reg [63:0] TXD_DEL9;
reg [63:0] TXD_DEL10;
reg [63:0] TXD_DEL11;
reg [63:0] TXD_DEL12;
reg [7:0] tx_data_int;
reg start_CRC8, START_CRC8_DEL;
reg append_end_frame;
 
reg [7:0] TXC_DEL1;
reg [7:0] TXC_DEL2;
reg [7:0] TXC_DEL3;
reg [7:0] TXC_DEL4;
reg [7:0] TXC_DEL5;
reg [7:0] TXC_DEL6;
reg [7:0] TXC_DEL7;
reg [7:0] TXC_DEL8;
reg [7:0] TXC_DEL9;
reg [7:0] TXC_DEL10;
reg [7:0] TXC_DEL11;
reg [7:0] TXC_DEL12;
 
reg [7:0] OVERFLOW_VALID;
reg [63:0] OVERFLOW_DATA;
reg insert_error;
 
reg [7:0] store_tx_data_valid;
reg [63:0] store_tx_data;
reg [31:0] store_CRC64;
reg [7:0] store_valid;
reg load_final_CRC;
 
reg [15:0] final_byte_count, byte_count_reg;
 
wire [31:0] CRC_OUT;
 
reg [9:0] append_reg;
 
 
reg [15:0] length_register;
 
reg tx_undderrun_int;
 
reg [15:0] MAX_FRAME_SIZE;
 
reg vlan_enabled_int;
reg jumbo_enabled_int;
reg tx_enabled_int;
reg fcs_enabled_int;
reg reset_tx_int;
reg read_ifg_int;
 
reg apply_pause_delay;
reg [15:0] store_pause_frame;
 
reg [63:0] TXD_PAUSE_DEL0;
reg [63:0] TXD_PAUSE_DEL1;
reg [63:0] TXD_PAUSE_DEL2;
reg [63:0] TXD_PAUSE_DEL3;
reg [63:0] TXD_PAUSE_DEL4;
reg [63:0] TXD_PAUSE_DEL5;
reg [63:0] TXD_PAUSE_DEL6;
reg [63:0] TXD_PAUSE_DEL7;
reg [63:0] TXD_PAUSE_DEL8;
 
reg [7:0] TXC_PAUSE_DEL0;
reg [7:0] TXC_PAUSE_DEL1;
reg [7:0] TXC_PAUSE_DEL2;
reg [7:0] TXC_PAUSE_DEL3;
reg [7:0] TXC_PAUSE_DEL4;
reg [7:0] TXC_PAUSE_DEL5;
reg [7:0] TXC_PAUSE_DEL6;
reg [7:0] TXC_PAUSE_DEL7;
reg [7:0] TXC_PAUSE_DEL8;
 
reg PAUSEVAL_DEL;
reg PAUSEVAL_DEL1;
reg PAUSEVAL_DEL2;
wire RESET_ERR_PAUSE;
 
reg set_pause_stats;
reg [15:0] store_transmit_pause_value;
reg [3:0] pause_frame_counter;
reg [63:0] shift_pause_data;
 
reg [7:0] shift_pause_valid;
reg [7:0] shift_pause_valid_del;
 
reg [14:0] byte_count_stat;
 
reg [24:0] txstatplus_int;
 
 
/////////////////////////////////////////////////////////////////////////////
//
// Start of code
236,48 → 287,9
 
 
 
integer i;
reg FRAME_START_DEL;
reg START_CRC8_DEL;
reg LOAD_CRC;
wire load_CRC8;
reg load_CRC8_del;
reg [3:0] APPEND_CRC_COUNT;
reg [15:0] CRC8_COUNT;
 
reg LOAD_OVERFLOW;
 
reg start_CRC8_count;
 
reg apply_pause_delay;
 
reg [63:0] store_data;
reg [7:0] store_valid;
reg [31:0] store_CRC;
reg [31:0] store_byte_count;
reg [15:0] store_pause_frame;
 
reg APPLY_CRC_SET;
 
reg [15:0] MAX_FRAME_SIZE;
 
reg [15:0] DATA_SIZE;
 
 
reg transmit_pause_frame;
reg PAUSEVAL_DEL;
reg PAUSEVAL_DEL1;
reg PAUSEVAL_DEL2;
wire RESET_ERR_PAUSE;
reg [15:0] store_transmit_pause_value;
reg [3:0] pause_frame_counter;
reg [63:0] shift_pause_data;
reg [7:0] shift_pause_valid;
wire transmit_pause_frame_valid;
reg append_start_pause;
reg append_start_pause_del;
reg transmit_pause_frame_del;
 
/////////////////////////////////////////////////////////////////////////////
//
// Ack counter
292,24 → 304,22
//need to stop the ack signal from transmitting when a PAUSE frame is transmitting
 
// Connect DUT to test bench
//This seem to be one of the culprit for the timing violation
ack_counter U_ACK_CNT(
.clock(TX_CLK),
.reset(RESET),
.ready(FRAME_START |START_CRC8_DEL | start_CRC8 | transmit_pause_frame),
.reset(reset_int | reset_tx_int),
.ready(FRAME_START | transmit_pause_frame),
.tx_start(TX_START),
.max_count(DELAY_ACK),
.tx_ack(TX_ACK)
);
 
 
//CRC for 64 bit data
//This seem to be one of the culprit for the timing violation
CRC32_D64 U_CRC64(
.DATA_IN(TX_DATA_REG), //need to swap between pause data
.CLK(TX_CLK),
.RESET(RESET | TX_ACK | append_start_pause),
.START(FRAME_START | transmit_pause_frame_valid),
.RESET(reset_int | TX_ACK | append_start_pause),
.START(frame_start_del | transmit_pause_frame_valid),
.CRC_OUT(CRC_32_64) //need to switch to output some how for a pause frame
);
 
318,7 → 328,7
CRC32_D8 U_CRC8(
.DATA_IN(tx_data_int), //8bit data
.CLK(TX_CLK),
.RESET(RESET),
.RESET(reset_int),
.START(start_CRC8), //this signal will be use to start
.LOAD(load_CRC8), //use this to load first
.CRC_IN(CRC_32_64),
326,55 → 336,18
);
 
 
 
//The start signal need to be high for the count
//This seem to be one of the culprit for the timing violation
byte_count_module U_byte_count_module(
.CLK(TX_CLK),
.RESET(RESET | TX_ACK),
.START(FRAME_START),
.PARALLEL_CNT(PARALLEL_CNT), //May need to remove as I don't require it
.RESET(reset_int | TX_ACK),
.START(frame_start_del & FRAME_START),
.BYTE_COUNTER(BYTE_COUNTER)
);
 
 
/////////////////////////////////////////////////////////////////////////////
//
//Still need to add more config stuff here!!!!!! For configuration register
//
/////////////////////////////////////////////////////////////////////////////
 
//Need to modify this to be setup by the config register
always @(posedge TX_CLK or posedge RESET)
begin
if (RESET) begin
APPLY_CRC_SET <= 0;
end
 
end
 
//Need to expand to be setup by the config register
always @(posedge TX_CLK or posedge RESET)
begin
if (RESET) begin
MAX_FRAME_SIZE <= 1514;
end
end
 
//Need to modify this to look for length in VLAN frame.
always @(posedge TX_CLK or posedge RESET)
begin
if (RESET) begin
length_register <= 0;
end
else if (BYTE_COUNTER == 8) begin
length_register <= TX_DATA_REG[47:32];
end
end
/////////////////////////////////////////////////////////////////////////////
 
 
/////////////////////////////////////////////////////////////////////////////
//
// PAUSE FRAME
//
387,9 → 360,9
PAUSEVAL_DEL2 <= PAUSEVAL_DEL1;
end
 
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
transmit_pause_frame <= 0;
end
else if (PAUSEVAL_DEL2) begin
400,28 → 373,30
end
end
 
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
set_pause_stats <= 0;
end
else if (PAUSEVAL_DEL2) begin
set_pause_stats <= 1;
end
else if (append_end_frame) begin
set_pause_stats <= 0;
end
end
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
TXD_PAUSE_DEL0 <= 0;
TXD_PAUSE_DEL1 <= 0;
TXD_PAUSE_DEL2 <= 0;
TXD_PAUSE_DEL3 <= 0;
TXD_PAUSE_DEL4 <= 0;
TXD_PAUSE_DEL5 <= 0;
TXD_PAUSE_DEL6 <= 0;
TXD_PAUSE_DEL7 <= 0;
TXD_PAUSE_DEL8 <= 0;
 
TXC_PAUSE_DEL0 <= 0;
TXC_PAUSE_DEL1 <= 0;
TXC_PAUSE_DEL2 <= 0;
TXC_PAUSE_DEL3 <= 0;
TXC_PAUSE_DEL4 <= 0;
TXC_PAUSE_DEL5 <= 0;
TXC_PAUSE_DEL6 <= 0;
TXC_PAUSE_DEL7 <= 0;
TXC_PAUSE_DEL8 <= 0;
 
store_transmit_pause_value <= 0;
end
432,19 → 407,14
 
TXC_PAUSE_DEL1 <= 8'hff;
TXC_PAUSE_DEL2 <= 8'hff;
TXC_PAUSE_DEL3 <= 8'hff;
TXC_PAUSE_DEL4 <= 8'hff;
TXC_PAUSE_DEL5 <= 8'hff;
TXC_PAUSE_DEL6 <= 8'hff;
TXC_PAUSE_DEL7 <= 8'hff;
TXC_PAUSE_DEL8 <= 8'h0f;
end
end
 
 
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
pause_frame_counter <= 0;
end
else if (transmit_pause_frame & !FRAME_START) begin
453,10 → 423,11
end
 
 
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
shift_pause_data <= 0;
shift_pause_valid_del <= 0;
shift_pause_valid <= 0;
end
else if (transmit_pause_frame & !FRAME_START) begin
480,10 → 451,13
else begin
shift_pause_valid <= 0;
end
shift_pause_valid_del <= shift_pause_valid;
end
else begin
shift_pause_data <= 0;
shift_pause_valid <= 0;
shift_pause_valid_del <= shift_pause_valid;
end
end
 
490,42 → 464,215
 
 
 
always @(posedge reset_int or posedge TX_CLK)
begin
if (reset_int) begin
FRAME_START <= 0;
end
else if (TX_ACK) begin
FRAME_START <= 1;
end
else if ((TX_DATA_VALID_REG != 8'hff) & (BYTE_COUNTER != 0)) begin
FRAME_START <= 0;
end
end
 
/////////////////////////////////////////////////////////////////////////////
 
 
 
assign reset_int = RESET;
 
//Signal that data is being processed and finshed.
always @(RESET or TX_ACK or TX_DATA_VALID_REG)
begin
if (RESET) begin
FRAME_START <= 0;
 
//TXSTATREGPLUS[24:0]
//24 pause_frame transmitted - count when pause flag is set
//23 to 20 bytes valid
//19 vlan frame - asserted if previous frame was a VLAN - just check if VLAN been set
//18 to 5 last frame length count in bytes stick to 16383 when jumbo frame is greater than value - just load the byte count
//4 if last frame has control type code 88-08 in the length type field - pause frame - check if pause flag is set
//3 underrun frame - check if underrun is set
//2 multicast frame - 01-80-C2-00-00-01 use for pause frame
//1 broadcast frame - al ones
//0 sucessful frame - check if error occurred -use insert error flag
 
 
//TX_STATS_VALID - need to be driving after a frame transmission - use load_overflow signal
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
txstatplus_int <= 0;
end
else if (TX_ACK) begin
FRAME_START <= 1;
else if (load_final_CRC) begin
if (insert_error) begin
txstatplus_int[3] <= 1;
end
if (set_pause_stats) begin
txstatplus_int[24] <= 1;
txstatplus_int[4] <= 1;
txstatplus_int[2] <= 1;
txstatplus_int[1] <= 1;
txstatplus_int[18:5] <= 512;
end
if (vlan_enabled_int) begin
txstatplus_int[19] <= 1;
end
else begin
if (final_byte_count[15] == 1) begin
txstatplus_int[18:5] <= 16383;
end
else begin
txstatplus_int[18:5] <= byte_count_stat;
end
end
end
else if (TX_DATA_VALID_REG != 8'hff) begin
FRAME_START <= 0;
else begin
txstatplus_int <= 0;
end
 
TXSTATREGPLUS <= txstatplus_int;
TX_STATS_VALID <= append_end_frame;
end
 
 
 
 
//input [31:0] TX_CFG_REG_VALUE;
//24:0 reserved
//25 default to 0 - min frame - 1 adjust frame delay by reading inter-frame gap delay reg - DELAY_ACK signal
//26 WAN - not used
//27 VLAN enable default to 0, 1 enabled
//28 default to 1 - transmitter enbaled, 0 - transmitter disabled - possibly used to reset
//29 default to 0 FCS enabled, 1 FCS disabled
//30 default to 0, 1 - Jumbo frame enabled
//31 deafult to 0, 1 - reset transmitter
 
//input TX_CFG_REG_VALID;
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
vlan_enabled_int <= 0;
jumbo_enabled_int <= 0;
tx_enabled_int <= 0;
fcs_enabled_int <= 1;
reset_tx_int <= 0;
read_ifg_int <= 0;
end
else if (TX_CFG_REG_VALID) begin
vlan_enabled_int <= TX_CFG_REG_VALUE[27];
jumbo_enabled_int <= TX_CFG_REG_VALUE[30];
tx_enabled_int <= TX_CFG_REG_VALUE[28]; // Stop ack from generated, hold reset
fcs_enabled_int <= TX_CFG_REG_VALUE[29];
reset_tx_int <= TX_CFG_REG_VALUE[31];
read_ifg_int <= TX_CFG_REG_VALUE[25];
end
end
 
 
//Load the delay value for the acknowledge signal
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
DELAY_ACK <= 16'h0001;
end
else if (apply_pause_delay) begin
DELAY_ACK <= store_pause_frame;
end
else if (read_ifg_int) begin
DELAY_ACK <= TX_IFG_DELAY;
end
end
 
 
//Need to expand to be setup by the config register
//1514 with out FCS added, 1518 when FCS is added
//1518 without FCS added, 1522 when FCS is added
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
MAX_FRAME_SIZE <= 1514;
end
else begin
if (vlan_enabled_int) begin
if (fcs_enabled_int) begin
MAX_FRAME_SIZE <= 1522;
end
else begin
MAX_FRAME_SIZE <= 1518;
end
end
else if (jumbo_enabled_int) begin
if (fcs_enabled_int) begin
MAX_FRAME_SIZE <= 1518;
end
else begin
MAX_FRAME_SIZE <= 1514;
end
end
else begin
if (fcs_enabled_int) begin
MAX_FRAME_SIZE <= 1518;
end
else begin
MAX_FRAME_SIZE <= 1514;
end
end
end
end
 
 
 
 
always @(posedge TX_CLK)
begin
if (reset_int | append_end_frame) begin
tx_undderrun_int <= 0;
end
else if (TX_UNDERRUN == 1) begin
tx_undderrun_int <= 1;
end
end
 
//Indicate an error
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int | append_end_frame | reset_err_pause) begin
insert_error <= 0;
end
else if (load_CRC8) begin
if (tx_undderrun_int == 1) begin
insert_error <= 1;
end
else begin
if (length_register == final_byte_count) begin
if (final_byte_count <= MAX_FRAME_SIZE) begin
insert_error <= 0;
end
else begin
insert_error <= 1;
end
end
else if (length_register < MIN_FRAME_SIZE) begin
if (final_byte_count == 64) begin
insert_error <= 0;
end
else begin
insert_error <= 1;
end
end
else begin
insert_error <= 1;
end
end
end
end
 
 
//use for delaying the ack signal when pause is required
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET | TX_ACK) begin
if (reset_int | TX_ACK) begin
apply_pause_delay <= 0;
store_pause_frame <= 0;
end
535,78 → 682,98
end
end
 
 
 
 
always @(posedge TX_CLK)
begin
if (TX_START) begin
TX_DATA_VALID_DELAY <= IDLE_FRAME_8BYTES;
end
else begin
TX_DATA_VALID_DELAY <= TX_DATA;
end
end
 
 
 
//Shift valid into the system and also ensuring min frame is achieved
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
TX_DATA_VALID_REG <= 0;
end
else if (FRAME_START) begin
if (BYTE_COUNTER < 56) begin
if (BYTE_COUNTER < 48) begin
TX_DATA_VALID_REG <= 8'b11111111;
end
else if (BYTE_COUNTER == 56) begin
TX_DATA_VALID_REG <= 8'b00001111 | TX_DATA_VALID;
else if (BYTE_COUNTER == 48) begin
if (TX_START) begin
TX_DATA_VALID_REG <= 8'b00001111;
end
else begin
TX_DATA_VALID_REG <= 8'b00001111 | TX_DATA_VALID;
end
end
else begin
TX_DATA_VALID_REG <= TX_DATA_VALID;
if (TX_START) begin
TX_DATA_VALID_REG <= 0;
end
else begin
TX_DATA_VALID_REG <= TX_DATA_VALID;
end
end
end
else if (transmit_pause_frame_valid) begin
TX_DATA_VALID_REG <= shift_pause_valid;
else if (transmit_pause_frame_del) begin
shift_pause_valid_del <= shift_pause_valid;
TX_DATA_VALID_REG <= shift_pause_valid_del;
end
else begin
TX_DATA_VALID_REG <= 0;
end
 
end
 
 
//Shifting data to the system. Also ensuring min frame is achieved
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
if (reset_int) begin
TX_DATA_REG <= IDLE_FRAME_8BYTES;
end
else if (FRAME_START) begin
if (BYTE_COUNTER < 56) begin
case (TX_DATA_VALID)
case (TX_DATA_VALID_REG)
8'b00000000 : begin
TX_DATA_REG <= 0;
TX_DATA_REG <= TX_DATA_VALID_DELAY;
end
8'b00000001 : begin
TX_DATA_REG <= {56'h00000000000000, TX_DATA[7:0]};
TX_DATA_REG <= {56'h00000000000000, TX_DATA_VALID_DELAY[7:0]};
end
8'b00000011 : begin
TX_DATA_REG <= {48'h000000000000, TX_DATA[15:0]};
TX_DATA_REG <= {48'h000000000000, TX_DATA_VALID_DELAY[15:0]};
end
8'b00000111 : begin
TX_DATA_REG <= {40'h0000000000, TX_DATA[23:0]};
TX_DATA_REG <= {40'h0000000000, TX_DATA_VALID_DELAY[23:0]};
end
8'b00001111 : begin
TX_DATA_REG <= {32'h00000000, TX_DATA[31:0]};
TX_DATA_REG <= {32'h00000000, TX_DATA_VALID_DELAY[31:0]};
end
8'b00011111 : begin
TX_DATA_REG <= {24'h000000, TX_DATA[39:0]};
TX_DATA_REG <= {24'h000000, TX_DATA_VALID_DELAY[39:0]};
end
8'b00111111 : begin
TX_DATA_REG <= {16'h0000, TX_DATA[47:0]};
TX_DATA_REG <= {16'h0000, TX_DATA_VALID_DELAY[47:0]};
end
8'b01111111 : begin
TX_DATA_REG <= {8'h00, TX_DATA[55:0]};
TX_DATA_REG <= {8'h00, TX_DATA_VALID_DELAY[55:0]};
end
8'b11111111 : begin
TX_DATA_REG <= TX_DATA;
TX_DATA_REG <= TX_DATA_VALID_DELAY;
end
endcase
end
else if (BYTE_COUNTER == 56) begin
TX_DATA_REG <= 0;
end
else begin
TX_DATA_REG <= TX_DATA;
TX_DATA_REG <= TX_DATA_VALID_DELAY;
end
end
else if (transmit_pause_frame_valid) begin
613,7 → 780,12
TX_DATA_REG <= shift_pause_data;
end
else begin
TX_DATA_REG <= IDLE_FRAME_8BYTES;
if (TX_ACK | append_start_pause) begin
TX_DATA_REG <= START_SEQ;
end
else begin
TX_DATA_REG <= IDLE_FRAME_8BYTES;
end
end
 
end
620,414 → 792,607
 
 
 
always @(posedge TX_CLK)
begin
PARALLEL_CNT <= 1;
end
 
 
//Use for shifting data to CRC and loading start value for CRC
always @(posedge TX_CLK)
begin
FRAME_START_DEL <= FRAME_START;
transmit_pause_frame_del <= transmit_pause_frame;
append_start_pause <= (!transmit_pause_frame_del & transmit_pause_frame);
append_start_pause_del <= append_start_pause;
end
 
assign transmit_pause_frame_valid = (transmit_pause_frame_del & transmit_pause_frame);
 
assign RESET_ERR_PAUSE = (transmit_pause_frame_del & !transmit_pause_frame);
assign load_CRC8 = (FRAME_START_DEL & !FRAME_START) | (transmit_pause_frame_del & !transmit_pause_frame);
 
 
 
 
 
//store 64 bit data CRC result, data_valid, data
always @(posedge TX_CLK or posedge RESET)
//Use for shifting data to CRC and loading start value for CRC
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
store_data <= 0;
store_valid <= 0;
store_CRC <= 0;
tx_data_int <= 0;
store_byte_count <= 0;
if (reset_int) begin
frame_start_del <= 0;
transmit_pause_frame_del <= 0;
transmit_pause_frame_del2 <= 0;
transmit_pause_frame_del3 <= 0;
append_start_pause <= 0;
append_start_pause_del <= 0;
transmit_pause_frame_valid <= 0;
reset_err_pause <= 0;
load_CRC8 <= 0;
end
else if (load_CRC8) begin
store_data <= TX_DATA_REG;
store_valid <= TX_DATA_VALID_REG;
store_CRC <= CRC_32_64;
store_byte_count <= BYTE_COUNTER;
end
else begin
store_valid[6:0] <= store_valid[7:1];
tx_data_int <= store_data[7:0];
store_data[55:0] <= store_data[63:8];
frame_start_del <= FRAME_START;
transmit_pause_frame_del <= transmit_pause_frame;
transmit_pause_frame_del2 <= transmit_pause_frame_del;
transmit_pause_frame_del3 <= transmit_pause_frame_del2;
append_start_pause <= (!transmit_pause_frame_del & transmit_pause_frame);
append_start_pause_del <= append_start_pause;
transmit_pause_frame_valid <= (transmit_pause_frame_del & transmit_pause_frame);
reset_err_pause <= (transmit_pause_frame_del & !transmit_pause_frame);
load_CRC8 <= (frame_start_del & !FRAME_START) | (transmit_pause_frame_del3 & !transmit_pause_frame_del2);
end
end
 
 
 
 
 
//Start CRC8 and load CRC8
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
start_CRC8 <= 0;
START_CRC8_DEL <= 0;
error_flag_int <= 0;
if (reset_int) begin
TX_DATA_VALID_DEL1 <= 0;
TX_DATA_VALID_DEL2 <= 0;
TX_DATA_VALID_DEL3 <= 0;
TX_DATA_VALID_DEL4 <= 0;
TX_DATA_VALID_DEL5 <= 0;
TX_DATA_VALID_DEL6 <= 0;
TX_DATA_VALID_DEL7 <= 0;
TX_DATA_VALID_DEL8 <= 0;
TX_DATA_VALID_DEL9 <= 0;
TX_DATA_VALID_DEL10 <= 0;
TX_DATA_VALID_DEL11 <= 0;
TX_DATA_VALID_DEL12 <= 0;
TX_DATA_VALID_DEL13 <= 0;
TX_DATA_VALID_DEL14 <= 0;
TX_DATA_VALID_DEL15 <= 0;
OVERFLOW_VALID <= 0;
end
else begin
start_CRC8 <= store_valid[0];
START_CRC8_DEL <= start_CRC8;
if (load_CRC8 == 1 & TX_DATA_VALID_REG == 8'h00) begin
error_flag_int <= load_CRC8;
TX_DATA_VALID_DEL1 <= TX_DATA_VALID_REG;
TX_DATA_VALID_DEL2 <= TX_DATA_VALID_DEL1;
TX_DATA_VALID_DEL3 <= TX_DATA_VALID_DEL2;
TX_DATA_VALID_DEL4 <= TX_DATA_VALID_DEL3;
TX_DATA_VALID_DEL5 <= TX_DATA_VALID_DEL4;
TX_DATA_VALID_DEL6 <= TX_DATA_VALID_DEL5;
TX_DATA_VALID_DEL7 <= TX_DATA_VALID_DEL6;
TX_DATA_VALID_DEL8 <= TX_DATA_VALID_DEL7;
TX_DATA_VALID_DEL9 <= TX_DATA_VALID_DEL8;
TX_DATA_VALID_DEL10 <= TX_DATA_VALID_DEL9;
TX_DATA_VALID_DEL11 <= TX_DATA_VALID_DEL10;
TX_DATA_VALID_DEL12 <= TX_DATA_VALID_DEL11;
TX_DATA_VALID_DEL13 <= TX_DATA_VALID_DEL12;
TX_DATA_VALID_DEL14 <= TX_DATA_VALID_DEL13;
 
if (load_final_CRC) begin
case (TX_DATA_VALID_DEL13)
8'b00000000 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b00001111;
end
else begin
TX_DATA_VALID_DEL14 <= 8'b00001111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00000001 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b00011111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00000011 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b00111111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00000111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b01111111;
end
OVERFLOW_VALID <= 8'b00000000;
end
8'b00001111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
end
 
OVERFLOW_VALID <= 8'b00000000;
end
8'b00011111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000001;
end
else begin
OVERFLOW_VALID <= 8'b00000000;
end
end
8'b00111111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000011;
end
else begin
OVERFLOW_VALID <= 8'b00000000;
end
end
8'b01111111 : begin
if (fcs_enabled_int) begin
TX_DATA_VALID_DEL14 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000111;
end
else begin
OVERFLOW_VALID <= 8'b00000000;
end
end
endcase
end
else begin
error_flag_int <= START_CRC8_DEL & !start_CRC8;
 
else if (append_end_frame) begin
TX_DATA_VALID_DEL14 <= OVERFLOW_VALID;
end
TX_DATA_VALID_DEL15 <= TX_DATA_VALID_DEL14;
TXC <= TX_DATA_VALID_DEL15;
end
end
 
//Use for determining the number of bytes in the data
always @(posedge TX_CLK or posedge RESET)
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
CRC8_COUNT <= 0;
if (reset_int) begin
TX_DATA_DEL1 <= 0;
TX_DATA_DEL2 <= 0;
TX_DATA_DEL3 <= 0;
TX_DATA_DEL4 <= 0;
TX_DATA_DEL5 <= 0;
TX_DATA_DEL6 <= 0;
TX_DATA_DEL7 <= 0;
TX_DATA_DEL8 <= 0;
TX_DATA_DEL9 <= 0;
TX_DATA_DEL10 <= 0;
TX_DATA_DEL11 <= 0;
TX_DATA_DEL12 <= 0;
TX_DATA_DEL13 <= 0;
TX_DATA_DEL14 <= 0;
TX_DATA_DEL15 <= 0;
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
else if (load_CRC8) begin
CRC8_COUNT <= BYTE_COUNTER;
end
else if (start_CRC8) begin
CRC8_COUNT <= CRC8_COUNT + 1;
end
end
 
//Flag use for appending CRC and terminate
always @(APPEND_CRC_COUNT)
begin
if (APPEND_CRC_COUNT == 9) begin
LOAD_CRC <= 1;
end
else begin
LOAD_CRC <= 0;
end
end
 
//Flag use for appending CRC and terminate
always @(APPEND_CRC_COUNT)
begin
if (APPEND_CRC_COUNT == 10) begin
LOAD_OVERFLOW <= 1;
end
else begin
LOAD_OVERFLOW <= 0;
end
end
 
//Start the append counter
always @(posedge TX_CLK or posedge RESET)
begin
if (RESET) begin
start_CRC8_count <= 0;
end
else if (load_CRC8) begin
start_CRC8_count <= 1;
end
else if (APPEND_CRC_COUNT == 10) begin
start_CRC8_count <= 0;
end
end
 
//Counter use to determine when to append CRC
always @(posedge TX_CLK or posedge RESET)
begin
if (RESET | load_CRC8) begin
APPEND_CRC_COUNT <= 0;
end
else if (start_CRC8_count) begin
APPEND_CRC_COUNT <= APPEND_CRC_COUNT +1;
end
end
 
 
//Append CRC and Terminate - still need to create non-crc version. Require a flag to stop CRC from generating.
always @(posedge TX_CLK or posedge RESET)
begin
if (RESET) begin
TXD_DEL1 <= 0;
TXD_DEL2 <= 0;
TXD_DEL3 <= 0;
TXD_DEL4 <= 0;
TXD_DEL5 <= 0;
TXD_DEL6 <= 0;
TXD_DEL7 <= 0;
TXD_DEL8 <= 0;
TXD_DEL9 <= 0;
TXD_DEL10 <= 0;
TXD_DEL11 <= 0;
TXD_DEL12 <= 0;
TXC_DEL1 <= 0;
TXC_DEL2 <= 0;
TXC_DEL3 <= 0;
TXC_DEL4 <= 0;
TXC_DEL5 <= 0;
TXC_DEL6 <= 0;
TXC_DEL7 <= 0;
TXC_DEL8 <= 0;
TXC_DEL9 <= 0;
TXC_DEL10 <= 0;
TXC_DEL11 <= 0;
TXC_DEL12 <= 0;
end
else begin
//Append start seq.
if (TX_ACK) begin
TXD_DEL1 <= START_SEQ;
end
else if (append_start_pause) begin
TXD_DEL1 <= START_SEQ;
end
else begin
TXD_DEL1 <= TX_DATA_REG;
end
TX_DATA_DEL1 <= TX_DATA_REG;
TX_DATA_DEL2 <= TX_DATA_DEL1;
TX_DATA_DEL3 <= TX_DATA_DEL2;
TX_DATA_DEL4 <= TX_DATA_DEL3;
TX_DATA_DEL5 <= TX_DATA_DEL4;
TX_DATA_DEL6 <= TX_DATA_DEL5;
TX_DATA_DEL7 <= TX_DATA_DEL6;
TX_DATA_DEL8 <= TX_DATA_DEL7;
TX_DATA_DEL9 <= TX_DATA_DEL8;
TX_DATA_DEL10 <= TX_DATA_DEL9;
TX_DATA_DEL11 <= TX_DATA_DEL10;
TX_DATA_DEL12 <= TX_DATA_DEL11;
TX_DATA_DEL13 <= TX_DATA_DEL12;
TX_DATA_DEL14 <= TX_DATA_DEL13;
TXD_DEL2 <= TXD_DEL1;
TXD_DEL3 <= TXD_DEL2;
TXD_DEL4 <= TXD_DEL3;
TXD_DEL5 <= TXD_DEL4;
TXD_DEL6 <= TXD_DEL5;
TXD_DEL7 <= TXD_DEL6;
TXD_DEL8 <= TXD_DEL7;
TXD_DEL9 <= TXD_DEL8;
TXD_DEL10 <= TXD_DEL9;
TXD_DEL11 <= TXD_DEL10;
TXC_DEL1 <= TX_DATA_VALID_REG;
TXC_DEL2 <= TXC_DEL1;
TXC_DEL3 <= TXC_DEL2;
TXC_DEL4 <= TXC_DEL3;
TXC_DEL5 <= TXC_DEL4;
TXC_DEL6 <= TXC_DEL5;
TXC_DEL7 <= TXC_DEL6;
TXC_DEL8 <= TXC_DEL7;
TXC_DEL9 <= TXC_DEL8;
TXC_DEL10 <= TXC_DEL9;
TXC_DEL11 <= TXC_DEL10;
if (LOAD_CRC) begin
case (TXC_DEL10)
if (load_final_CRC) begin
case (TX_DATA_VALID_DEL13)
8'b00000000 : begin
TXD_DEL11[31:0] <= CRC_OUT[31:0];
if (insert_error) begin
TXD_DEL11[39:32] <= ERROR_FRAME;
TXD_DEL11[47:40] <= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[31:0] <= CRC_OUT[31:0];
if (insert_error) begin
TX_DATA_DEL14[39:32] <= ERROR_FRAME;
TX_DATA_DEL14[47:40] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[39:32] <= TERMINATE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
end
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
else begin
TXD_DEL11[39:32] <= TERMINATE_FRAME;
TXD_DEL11[47:40] <= IDLE_FRAME;
if (insert_error) begin
TX_DATA_DEL14[7:0] <= ERROR_FRAME;
TX_DATA_DEL14[15:8] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[7:0] <= TERMINATE_FRAME;
TX_DATA_DEL14[15:8] <= IDLE_FRAME;
end
 
TX_DATA_DEL14[23:16] <= IDLE_FRAME;
TX_DATA_DEL14[31:24] <= IDLE_FRAME;
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
TXD_DEL11[55:48] <= IDLE_FRAME;
TXD_DEL11[63:56] <= IDLE_FRAME;
TXC_DEL11 <= 8'b00001111;
OVERFLOW_VALID <= 8'b00000000;
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
8'b00000001 : begin
TXD_DEL11[7:0] <= TXD_DEL10[7:0];
TXD_DEL11[39:8] <= CRC_OUT[31:0];
if (insert_error) begin
TXD_DEL11[47:40] <= ERROR_FRAME;
TXD_DEL11[55:48] <= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0];
TX_DATA_DEL14[39:8] <= CRC_OUT[31:0];
if (insert_error) begin
TX_DATA_DEL14[47:40] <= ERROR_FRAME;
TX_DATA_DEL14[55:48] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[47:40] <= TERMINATE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
end
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
TX_DATA_DEL14 <= TX_DATA_DEL13;
 
end
else begin
TXD_DEL11[47:40] <= TERMINATE_FRAME;
TXD_DEL11[55:48] <= IDLE_FRAME;
end
TXD_DEL11[47:40] <= TERMINATE_FRAME;
TXD_DEL11[55:48] <= IDLE_FRAME;
TXD_DEL11[63:56] <= IDLE_FRAME;
TXD_DEL11 <= TXD_DEL10;
TXC_DEL11 <= 8'b00011111;
OVERFLOW_VALID <= 8'b00000000;
TX_DATA_DEL14[7:0] <= TX_DATA_DEL13[7:0];
 
if (insert_error) begin
TX_DATA_DEL14[15:8] <= ERROR_FRAME;
TX_DATA_DEL14[23:16] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[15:8] <= TERMINATE_FRAME;
TX_DATA_DEL14[23:16] <= IDLE_FRAME;
end
TX_DATA_DEL14[31:24] <= IDLE_FRAME;
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
TX_DATA_DEL14 <= TX_DATA_DEL13;
end
 
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
8'b00000011 : begin
TXD_DEL11[15:0] <= TXD_DEL10[15:0];
TXD_DEL11[47:16] <= CRC_OUT[31:0];
if (insert_error) begin
TXD_DEL11[55:48] <= ERROR_FRAME;
TXD_DEL11[63:56] <= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0];
TX_DATA_DEL14[47:16] <= CRC_OUT[31:0];
if (insert_error) begin
TX_DATA_DEL14[55:48] <= ERROR_FRAME;
TX_DATA_DEL14[63:56] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[55:48] <= TERMINATE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
else begin
TXD_DEL11[55:48] <= TERMINATE_FRAME;
TXD_DEL11[63:56] <= IDLE_FRAME;
end
TXC_DEL11 <= 8'b00111111;
OVERFLOW_VALID <= 8'b00000000;
TX_DATA_DEL14[15:0] <= TX_DATA_DEL13[15:0];
if (insert_error) begin
TX_DATA_DEL14[23:16] <= ERROR_FRAME;
TX_DATA_DEL14[31:24] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[23:16] <= TERMINATE_FRAME;
TX_DATA_DEL14[31:24] <= IDLE_FRAME;
end
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
 
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
end
8'b00000111 : begin
TXD_DEL11[23:0] <= TXD_DEL10[23:0];
TXD_DEL11[55:24] <= CRC_OUT[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TXD_DEL11[63:56] <= ERROR_FRAME;
OVERFLOW_DATA[7:0] <= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0];
TX_DATA_DEL14[55:24] <= CRC_OUT[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14[63:56] <= ERROR_FRAME;
OVERFLOW_DATA[7:0] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[63:56] <= TERMINATE_FRAME;
end
end
else begin
TXD_DEL11[63:56] <= TERMINATE_FRAME;
end
TXC_DEL11 <= 8'b01111111;
OVERFLOW_VALID <= 8'b00000000;
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
TX_DATA_DEL14[23:0] <= TX_DATA_DEL13[23:0];
TX_DATA_DEL14[55:24] <= CRC_OUT[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14[31:24] <= ERROR_FRAME;
TX_DATA_DEL14[39:32] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14[31:24] <= TERMINATE_FRAME;
TX_DATA_DEL14[39:32] <= IDLE_FRAME;
end
TX_DATA_DEL14[47:40] <= IDLE_FRAME;
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
8'b00001111 : begin
TXD_DEL11[31:0] <= TXD_DEL10[31:0];
TXD_DEL11[63:32]<= CRC_OUT[31:0];
TXC_DEL11<= 8'b11111111;
OVERFLOW_VALID <= 8'b00000000;
if (insert_error) begin
OVERFLOW_DATA [7:0] <= ERROR_FRAME;
OVERFLOW_DATA[15:8] <= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0];
TX_DATA_DEL14[63:32]<= CRC_OUT[31:0];
 
if (insert_error) begin
OVERFLOW_DATA [7:0] <= ERROR_FRAME;
OVERFLOW_DATA[15:8] <= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [7:0]<= TERMINATE_FRAME;
OVERFLOW_DATA [15:8]<= IDLE_FRAME;
end
OVERFLOW_DATA [23:16]<= IDLE_FRAME;
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
OVERFLOW_DATA [7:0]<= TERMINATE_FRAME;
OVERFLOW_DATA [15:8]<= IDLE_FRAME;
end
OVERFLOW_DATA [23:16]<= IDLE_FRAME;
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
TX_DATA_DEL14[31:0] <= TX_DATA_DEL13[31:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14 [39:32] <= ERROR_FRAME;
TX_DATA_DEL14[47:40] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [39:32]<= TERMINATE_FRAME;
TX_DATA_DEL14 [47:40]<= IDLE_FRAME;
end
TX_DATA_DEL14[55:48] <= IDLE_FRAME;
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
8'b00011111 : begin
TXD_DEL11[39:0] <= TXD_DEL10[39:0];
TXD_DEL11[63:40] <= CRC_OUT[23:0];
TXC_DEL11 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000001;
OVERFLOW_DATA [7:0]<= CRC_OUT[31:24];
if (insert_error) begin
OVERFLOW_DATA [15:8]<= ERROR_FRAME;
OVERFLOW_DATA [23:16]<= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0];
TX_DATA_DEL14[63:40] <= CRC_OUT[23:0];
OVERFLOW_DATA [7:0]<= CRC_OUT[31:24];
if (insert_error) begin
OVERFLOW_DATA [15:8]<= ERROR_FRAME;
OVERFLOW_DATA [23:16]<= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [15:8]<= TERMINATE_FRAME;
OVERFLOW_DATA [23:16]<= IDLE_FRAME;
end
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
OVERFLOW_DATA [15:8]<= TERMINATE_FRAME;
OVERFLOW_DATA [23:16]<= IDLE_FRAME;
end
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
TX_DATA_DEL14[39:0] <= TX_DATA_DEL13[39:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14 [47:40] <= ERROR_FRAME;
TX_DATA_DEL14[55:48] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [47:40]<= TERMINATE_FRAME;
TX_DATA_DEL14 [55:48]<= IDLE_FRAME;
end
TX_DATA_DEL14[63:56] <= IDLE_FRAME;
end
end
8'b00111111 : begin
TXD_DEL11[47:0] <= TXD_DEL10[47:0];
TXD_DEL11[63:48] <= CRC_OUT[15:0];
TXC_DEL11 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000011;
OVERFLOW_DATA [15:0]<= CRC_OUT[31:16];
if (insert_error) begin
OVERFLOW_DATA [23:16]<= ERROR_FRAME;
OVERFLOW_DATA [31:24]<= TERMINATE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0];
TX_DATA_DEL14[63:48] <= CRC_OUT[15:0];
OVERFLOW_DATA [15:0]<= CRC_OUT[31:16];
if (insert_error) begin
OVERFLOW_DATA [23:16]<= ERROR_FRAME;
OVERFLOW_DATA [31:24]<= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [23:16]<= TERMINATE_FRAME;
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
end
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
OVERFLOW_DATA [23:16]<= TERMINATE_FRAME;
OVERFLOW_DATA [31:24]<= IDLE_FRAME;
end
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
 
TX_DATA_DEL14[47:0] <= TX_DATA_DEL13[47:0];
if (insert_error) begin
TX_DATA_DEL14 [55:48] <= ERROR_FRAME;
TX_DATA_DEL14[63:56] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [55:48]<= TERMINATE_FRAME;
TX_DATA_DEL14 [63:56]<= IDLE_FRAME;
end
end
end
8'b01111111 : begin
TXD_DEL11[55:0] <= TXD_DEL10[55:0];
TXD_DEL11[63:56] <= CRC_OUT[7:0];
TXC_DEL11 <= 8'b11111111;
OVERFLOW_VALID <= 8'b00000111;
OVERFLOW_DATA [23:0]<= CRC_OUT[31:8];
if (insert_error) begin
OVERFLOW_DATA [31:24]<= ERROR_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
end
if (fcs_enabled_int) begin
TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0];
TX_DATA_DEL14[63:56] <= CRC_OUT[7:0];
OVERFLOW_DATA [23:0]<= CRC_OUT[31:8];
if (insert_error) begin
OVERFLOW_DATA [31:24]<= ERROR_FRAME;
OVERFLOW_DATA [39:32]<= TERMINATE_FRAME;
end
else begin
OVERFLOW_DATA [31:24]<= TERMINATE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
end
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
end
else begin
OVERFLOW_DATA [31:24]<= TERMINATE_FRAME;
OVERFLOW_DATA [39:32]<= IDLE_FRAME;
end
OVERFLOW_DATA [47:40]<= IDLE_FRAME;
OVERFLOW_DATA [55:48]<= IDLE_FRAME;
OVERFLOW_DATA [63:56]<= IDLE_FRAME;
TX_DATA_DEL14[55:0] <= TX_DATA_DEL13[55:0];
OVERFLOW_DATA <= IDLE_FRAME_8BYTES;
if (insert_error) begin
TX_DATA_DEL14 [63:56] <= ERROR_FRAME;
OVERFLOW_DATA[7:0] <= TERMINATE_FRAME;
end
else begin
TX_DATA_DEL14 [63:56]<= TERMINATE_FRAME;
OVERFLOW_DATA [7:0]<= IDLE_FRAME;
end
end
end
 
endcase
end
else if (LOAD_OVERFLOW) begin
TXC_DEL11 <= OVERFLOW_VALID;
TXD_DEL11 <= OVERFLOW_DATA;
else if (append_end_frame) begin
TX_DATA_DEL14 <= OVERFLOW_DATA;
end
TXD_DEL12 <= TXD_DEL11;
TXC <= TXC_DEL12;
TXD <= TXD_DEL12;
 
TX_DATA_DEL15 <= TX_DATA_DEL14;
 
TXD <= TX_DATA_DEL15;
end
end
 
 
 
//Checking the data size from the byte count hence the -12 (remove address bytes)
always @(posedge TX_CLK or posedge RESET)
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET) begin
DATA_SIZE <= 0;
if (reset_int) begin
store_tx_data_valid <= 0;
store_tx_data <= 0;
store_CRC64 <= 0;
tx_data_int <= 0;
end
else if (error_flag_int) begin
DATA_SIZE <= CRC8_COUNT-12;
else if (load_CRC8) begin
store_tx_data_valid <= TX_DATA_VALID_DEL2;
store_tx_data <= TX_DATA_DEL2;
store_CRC64 <= CRC_32_64;
end
else begin
store_tx_data_valid[6:0] <= store_tx_data_valid[7:1];
tx_data_int <= store_tx_data[7:0];
store_tx_data[55:0] <= store_tx_data[63:8];
end
end
 
//Start CRC8 and load CRC8
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
start_CRC8 <= 0;
START_CRC8_DEL <= 0;
end
else begin
start_CRC8 <= store_tx_data_valid[0];
START_CRC8_DEL <= start_CRC8;
end
end
 
//Indicate an error
always @(posedge TX_CLK or posedge RESET)
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (RESET | LOAD_OVERFLOW | RESET_ERR_PAUSE) begin
insert_error <= 0;
if (reset_int) begin
byte_count_reg <= 0;
end
else begin
byte_count_reg <= BYTE_COUNTER;
end
end
 
//Use for determining the number of bytes in the data
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
final_byte_count <= 0;
end
else if (load_CRC8) begin
if (length_register < MIN_FRAME_SIZE) begin
if (CRC8_COUNT == 60) begin
insert_error <= 0;
end
else begin
insert_error <= 1;
end
if (BYTE_COUNTER == 64) begin
final_byte_count <= 60;
end
else begin
final_byte_count <= byte_count_reg;
end
end
else if (start_CRC8) begin
final_byte_count <= final_byte_count + 1;
end
 
if (transmit_pause_frame) begin
byte_count_stat = 512;
end
else begin
byte_count_stat = final_byte_count;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
append_reg <= 0;
load_final_CRC <= 0;
append_end_frame <= 0;
end
else begin
append_reg[0] <= load_CRC8;
append_reg[9:1] <= append_reg[8:0];
load_final_CRC <= append_reg[9];
append_end_frame <= load_final_CRC;
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
vlan_enabled_int <= 0;
end
end
 
// VLAN field - 8100 at second 64 bit data at 32:47 and V1 V2 is at 48:63
// length field at third 64 bit data at 0:15
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
length_register <= 0;
end
if (vlan_enabled_int) begin
if (BYTE_COUNTER == 16) begin
length_register <= TX_DATA_REG[15:0];
end
end
else begin
if (BYTE_COUNTER == 8) begin
length_register <= TX_DATA_REG[47:32];
end
else if (length_register == DATA_SIZE) begin
if (CRC8_COUNT <= MAX_FRAME_SIZE) begin
insert_error <= 0;
end
else begin
insert_error <= 1;
end
end
else begin
insert_error <= 1;
end
end
end
 
 
always @(posedge TX_CLK or posedge reset_int)
begin
if (reset_int) begin
set_pause_stats <= 0;
end
else if (PAUSEVAL_DEL2) begin
set_pause_stats <= 1;
end
else if (append_end_frame) begin
set_pause_stats <= 0;
end
end
 
 
/trunk/tx_engine/CRC32_D64.v
12,17 → 12,23
 
reg start_int;
reg startCRC;
reg [63:0] data_del;
wire [63:0] data_del;
 
always @(posedge CLK)
begin
start_int <= START;
data_del <= DATA_IN;
end
 
always @(start_int or START)
assign data_del = {DATA_IN[0],DATA_IN[1],DATA_IN[2],DATA_IN[3],DATA_IN[4],DATA_IN[5],DATA_IN[6],DATA_IN[7],
DATA_IN[8],DATA_IN[9],DATA_IN[10],DATA_IN[11],DATA_IN[12],DATA_IN[13],DATA_IN[14],DATA_IN[15],
DATA_IN[16],DATA_IN[17],DATA_IN[18],DATA_IN[19],DATA_IN[20],DATA_IN[21],DATA_IN[22],DATA_IN[23],
DATA_IN[24],DATA_IN[25],DATA_IN[26],DATA_IN[27],DATA_IN[28],DATA_IN[29],DATA_IN[30],DATA_IN[31],
DATA_IN[32],DATA_IN[33],DATA_IN[34],DATA_IN[35],DATA_IN[36],DATA_IN[37],DATA_IN[38],DATA_IN[39],
DATA_IN[40],DATA_IN[41],DATA_IN[42],DATA_IN[43],DATA_IN[44],DATA_IN[45],DATA_IN[46],DATA_IN[47],
DATA_IN[48],DATA_IN[49],DATA_IN[50],DATA_IN[51],DATA_IN[52],DATA_IN[53],DATA_IN[54],DATA_IN[55],
DATA_IN[56],DATA_IN[57],DATA_IN[58],DATA_IN[59],DATA_IN[60],DATA_IN[61],DATA_IN[62],DATA_IN[63]};
 
//assign data_del = 64'h1000000000000000;
 
always @(START)
begin
startCRC <= START; //start_int | START;
startCRC <= START;
end
 
always @(posedge CLK or posedge RESET)
33,9 → 39,7
end
else if (startCRC == 1) begin
CRC_OUT <= nextCRC32_D64(DATA_IN, CRC_OUT);
 
 
CRC_OUT <= nextCRC32_D64(data_del, CRC_OUT);
end
end
/trunk/tx_engine/TransmitTop_tb.v
27,6 → 27,7
reg TX_CFG_REG_VALID;
 
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
55,18 → 56,18
TX_DATA_VALID <= 8'hFF;
D_START <= 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#400 //TX_DATA_VALID <= 8'h00;
//FC_TX_PAUSEVALID <= 1;
//FC_TX_PAUSEDATA <= 30;
FC_TRANS_PAUSEDATA <= 30;
FC_TRANS_PAUSEVAL <= 1;
// TX_DATA_VALID <= 8'h7f;
// FC_TRANS_PAUSEDATA <= 30;
// FC_TRANS_PAUSEVAL <= 1;
TX_DATA_VALID <= 8'h7f;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
//FC_TX_PAUSEVALID <= 0;
//FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
// FC_TRANS_PAUSEDATA <= 0;
// FC_TRANS_PAUSEVAL <= 0;
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
141,6 → 142,7
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.