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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
45,110 → 45,110
// Wire & Register definition
//------------------------------
 
// RAM interface
wire [`RAM_MSB:0] ram_addr;
wire ram_cen;
wire [15:0] ram_din;
wire [1:0] ram_wen;
wire [15:0] ram_dout;
// Data Memory interface
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
 
// ROM interface
wire [`ROM_MSB:0] rom_addr;
wire rom_cen;
wire [15:0] rom_din_dbg;
wire [1:0] rom_wen_dbg;
wire [15:0] rom_dout;
// Program Memory interface
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
 
// Peripherals interface
wire [7:0] per_addr;
wire [15:0] per_din;
wire [15:0] per_dout;
wire [1:0] per_wen;
wire per_en;
wire [7:0] per_addr;
wire [15:0] per_din;
wire [15:0] per_dout;
wire [1:0] per_wen;
wire per_en;
 
// Digital I/O
wire irq_port1;
wire irq_port2;
wire [15:0] per_dout_dio;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [7:0] p4_dout;
wire [7:0] p4_dout_en;
wire [7:0] p4_sel;
wire [7:0] p5_dout;
wire [7:0] p5_dout_en;
wire [7:0] p5_sel;
wire [7:0] p6_dout;
wire [7:0] p6_dout_en;
wire [7:0] p6_sel;
reg [7:0] p1_din;
reg [7:0] p2_din;
reg [7:0] p3_din;
reg [7:0] p4_din;
reg [7:0] p5_din;
reg [7:0] p6_din;
wire irq_port1;
wire irq_port2;
wire [15:0] per_dout_dio;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [7:0] p4_dout;
wire [7:0] p4_dout_en;
wire [7:0] p4_sel;
wire [7:0] p5_dout;
wire [7:0] p5_dout_en;
wire [7:0] p5_sel;
wire [7:0] p6_dout;
wire [7:0] p6_dout_en;
wire [7:0] p6_sel;
reg [7:0] p1_din;
reg [7:0] p2_din;
reg [7:0] p3_din;
reg [7:0] p4_din;
reg [7:0] p5_din;
reg [7:0] p6_din;
 
// Peripheral templates
wire [15:0] per_dout_temp_8b;
wire [15:0] per_dout_temp_16b;
wire [15:0] per_dout_temp_8b;
wire [15:0] per_dout_temp_16b;
 
// Timer A
wire irq_ta0;
wire irq_ta1;
wire [15:0] per_dout_timerA;
reg inclk;
reg taclk;
reg ta_cci0a;
reg ta_cci0b;
reg ta_cci1a;
reg ta_cci1b;
reg ta_cci2a;
reg ta_cci2b;
wire ta_out0;
wire ta_out0_en;
wire ta_out1;
wire ta_out1_en;
wire ta_out2;
wire ta_out2_en;
wire irq_ta0;
wire irq_ta1;
wire [15:0] per_dout_timerA;
reg inclk;
reg taclk;
reg ta_cci0a;
reg ta_cci0b;
reg ta_cci1a;
reg ta_cci1b;
reg ta_cci2a;
reg ta_cci2b;
wire ta_out0;
wire ta_out0_en;
wire ta_out1;
wire ta_out1_en;
wire ta_out2;
wire ta_out2_en;
// Clock / Reset & Interrupts
reg dco_clk;
reg lfxt_clk;
wire mclk;
wire aclk_en;
wire smclk_en;
reg reset_n;
wire puc;
reg nmi;
reg [13:0] irq;
wire [13:0] irq_acc;
wire [13:0] irq_in;
reg dco_clk;
reg lfxt_clk;
wire mclk;
wire aclk_en;
wire smclk_en;
reg reset_n;
wire puc;
reg nmi;
reg [13:0] irq;
wire [13:0] irq_acc;
wire [13:0] irq_in;
 
// Debug interface
wire dbg_freeze;
wire dbg_uart_txd;
reg dbg_uart_rxd;
reg [15:0] dbg_uart_buf;
wire dbg_freeze;
wire dbg_uart_txd;
reg dbg_uart_rxd;
reg [15:0] dbg_uart_buf;
 
// Core testbench debuging signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
// Testbench variables
integer error;
reg stimulus_done;
integer error;
reg stimulus_done;
 
 
//
170,7 → 170,7
//------------------------------
initial
begin
$readmemh("./rom.mem", rom_0.mem);
$readmemh("./pmem.mem", pmem_0.mem);
end
 
//
222,38 → 222,38
 
//
// ROM
// Program Memory
//----------------------------------
 
ram #(`ROM_MSB) rom_0 (
ram #(`PMEM_MSB) pmem_0 (
 
// OUTPUTs
.ram_dout (rom_dout), // ROM data output
.ram_dout (pmem_dout), // Program Memory data output
 
// INPUTs
.ram_addr (rom_addr), // ROM address
.ram_cen (rom_cen), // ROM chip enable (low active)
.ram_clk (mclk), // ROM clock
.ram_din (rom_din_dbg), // ROM data input
.ram_wen (rom_wen_dbg) // ROM write enable (low active)
.ram_addr (pmem_addr), // Program Memory address
.ram_cen (pmem_cen), // Program Memory chip enable (low active)
.ram_clk (mclk), // Program Memory clock
.ram_din (pmem_din), // Program Memory data input
.ram_wen (pmem_wen) // Program Memory write enable (low active)
);
 
 
//
// RAM
// Data Memory
//----------------------------------
 
ram #(`RAM_MSB) ram_0 (
ram #(`DMEM_MSB) dmem_0 (
 
// OUTPUTs
.ram_dout (ram_dout), // RAM data output
.ram_dout (dmem_dout), // Data Memory data output
 
// INPUTs
.ram_addr (ram_addr), // RAM address
.ram_cen (ram_cen), // RAM chip enable (low active)
.ram_clk (mclk), // RAM clock
.ram_din (ram_din), // RAM data input
.ram_wen (ram_wen) // RAM write enable (low active)
.ram_addr (dmem_addr), // Data Memory address
.ram_cen (dmem_cen), // Data Memory chip enable (low active)
.ram_clk (mclk), // Data Memory clock
.ram_din (dmem_din), // Data Memory data input
.ram_wen (dmem_wen) // Data Memory write enable (low active)
);
 
 
267,6 → 267,10
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
273,27 → 277,23
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc (puc), // Main system reset
.ram_addr (ram_addr), // RAM address
.ram_cen (ram_cen), // RAM chip enable (low active)
.ram_din (ram_din), // RAM data input
.ram_wen (ram_wen), // RAM write enable (low active)
.rom_addr (rom_addr), // ROM address
.rom_cen (rom_cen), // ROM chip enable (low active)
.rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE--
.rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF--
.smclk_en (smclk_en), // SMCLK enable
 
// INPUTs
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_in), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.ram_dout (ram_dout), // RAM data output
.reset_n (reset_n), // Reset Pin (low active)
.rom_dout (rom_dout) // ROM data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n) // Reset Pin (low active)
);
 
//
/openmsp430/trunk/core/bench/verilog/registers.v
61,89 → 61,89
// RAM cells
//======================
 
wire [15:0] mem200 = ram_0.mem[0];
wire [15:0] mem202 = ram_0.mem[1];
wire [15:0] mem204 = ram_0.mem[2];
wire [15:0] mem206 = ram_0.mem[3];
wire [15:0] mem208 = ram_0.mem[4];
wire [15:0] mem20A = ram_0.mem[5];
wire [15:0] mem20C = ram_0.mem[6];
wire [15:0] mem20E = ram_0.mem[7];
wire [15:0] mem210 = ram_0.mem[8];
wire [15:0] mem212 = ram_0.mem[9];
wire [15:0] mem214 = ram_0.mem[10];
wire [15:0] mem216 = ram_0.mem[11];
wire [15:0] mem218 = ram_0.mem[12];
wire [15:0] mem21A = ram_0.mem[13];
wire [15:0] mem21C = ram_0.mem[14];
wire [15:0] mem21E = ram_0.mem[15];
wire [15:0] mem220 = ram_0.mem[16];
wire [15:0] mem222 = ram_0.mem[17];
wire [15:0] mem224 = ram_0.mem[18];
wire [15:0] mem226 = ram_0.mem[19];
wire [15:0] mem228 = ram_0.mem[20];
wire [15:0] mem22A = ram_0.mem[21];
wire [15:0] mem22C = ram_0.mem[22];
wire [15:0] mem22E = ram_0.mem[23];
wire [15:0] mem230 = ram_0.mem[24];
wire [15:0] mem232 = ram_0.mem[25];
wire [15:0] mem234 = ram_0.mem[26];
wire [15:0] mem236 = ram_0.mem[27];
wire [15:0] mem238 = ram_0.mem[28];
wire [15:0] mem23A = ram_0.mem[29];
wire [15:0] mem23C = ram_0.mem[30];
wire [15:0] mem23E = ram_0.mem[31];
wire [15:0] mem240 = ram_0.mem[32];
wire [15:0] mem242 = ram_0.mem[33];
wire [15:0] mem244 = ram_0.mem[34];
wire [15:0] mem246 = ram_0.mem[35];
wire [15:0] mem248 = ram_0.mem[36];
wire [15:0] mem24A = ram_0.mem[37];
wire [15:0] mem24C = ram_0.mem[38];
wire [15:0] mem24E = ram_0.mem[39];
wire [15:0] mem250 = ram_0.mem[40];
wire [15:0] mem252 = ram_0.mem[41];
wire [15:0] mem254 = ram_0.mem[42];
wire [15:0] mem256 = ram_0.mem[43];
wire [15:0] mem258 = ram_0.mem[44];
wire [15:0] mem25A = ram_0.mem[45];
wire [15:0] mem25C = ram_0.mem[46];
wire [15:0] mem25E = ram_0.mem[47];
wire [15:0] mem260 = ram_0.mem[48];
wire [15:0] mem262 = ram_0.mem[49];
wire [15:0] mem264 = ram_0.mem[50];
wire [15:0] mem266 = ram_0.mem[51];
wire [15:0] mem268 = ram_0.mem[52];
wire [15:0] mem26A = ram_0.mem[53];
wire [15:0] mem26C = ram_0.mem[54];
wire [15:0] mem26E = ram_0.mem[55];
wire [15:0] mem270 = ram_0.mem[56];
wire [15:0] mem272 = ram_0.mem[57];
wire [15:0] mem274 = ram_0.mem[58];
wire [15:0] mem276 = ram_0.mem[59];
wire [15:0] mem278 = ram_0.mem[60];
wire [15:0] mem27A = ram_0.mem[61];
wire [15:0] mem27C = ram_0.mem[62];
wire [15:0] mem27E = ram_0.mem[63];
wire [15:0] mem280 = ram_0.mem[64];
wire [15:0] mem200 = dmem_0.mem[0];
wire [15:0] mem202 = dmem_0.mem[1];
wire [15:0] mem204 = dmem_0.mem[2];
wire [15:0] mem206 = dmem_0.mem[3];
wire [15:0] mem208 = dmem_0.mem[4];
wire [15:0] mem20A = dmem_0.mem[5];
wire [15:0] mem20C = dmem_0.mem[6];
wire [15:0] mem20E = dmem_0.mem[7];
wire [15:0] mem210 = dmem_0.mem[8];
wire [15:0] mem212 = dmem_0.mem[9];
wire [15:0] mem214 = dmem_0.mem[10];
wire [15:0] mem216 = dmem_0.mem[11];
wire [15:0] mem218 = dmem_0.mem[12];
wire [15:0] mem21A = dmem_0.mem[13];
wire [15:0] mem21C = dmem_0.mem[14];
wire [15:0] mem21E = dmem_0.mem[15];
wire [15:0] mem220 = dmem_0.mem[16];
wire [15:0] mem222 = dmem_0.mem[17];
wire [15:0] mem224 = dmem_0.mem[18];
wire [15:0] mem226 = dmem_0.mem[19];
wire [15:0] mem228 = dmem_0.mem[20];
wire [15:0] mem22A = dmem_0.mem[21];
wire [15:0] mem22C = dmem_0.mem[22];
wire [15:0] mem22E = dmem_0.mem[23];
wire [15:0] mem230 = dmem_0.mem[24];
wire [15:0] mem232 = dmem_0.mem[25];
wire [15:0] mem234 = dmem_0.mem[26];
wire [15:0] mem236 = dmem_0.mem[27];
wire [15:0] mem238 = dmem_0.mem[28];
wire [15:0] mem23A = dmem_0.mem[29];
wire [15:0] mem23C = dmem_0.mem[30];
wire [15:0] mem23E = dmem_0.mem[31];
wire [15:0] mem240 = dmem_0.mem[32];
wire [15:0] mem242 = dmem_0.mem[33];
wire [15:0] mem244 = dmem_0.mem[34];
wire [15:0] mem246 = dmem_0.mem[35];
wire [15:0] mem248 = dmem_0.mem[36];
wire [15:0] mem24A = dmem_0.mem[37];
wire [15:0] mem24C = dmem_0.mem[38];
wire [15:0] mem24E = dmem_0.mem[39];
wire [15:0] mem250 = dmem_0.mem[40];
wire [15:0] mem252 = dmem_0.mem[41];
wire [15:0] mem254 = dmem_0.mem[42];
wire [15:0] mem256 = dmem_0.mem[43];
wire [15:0] mem258 = dmem_0.mem[44];
wire [15:0] mem25A = dmem_0.mem[45];
wire [15:0] mem25C = dmem_0.mem[46];
wire [15:0] mem25E = dmem_0.mem[47];
wire [15:0] mem260 = dmem_0.mem[48];
wire [15:0] mem262 = dmem_0.mem[49];
wire [15:0] mem264 = dmem_0.mem[50];
wire [15:0] mem266 = dmem_0.mem[51];
wire [15:0] mem268 = dmem_0.mem[52];
wire [15:0] mem26A = dmem_0.mem[53];
wire [15:0] mem26C = dmem_0.mem[54];
wire [15:0] mem26E = dmem_0.mem[55];
wire [15:0] mem270 = dmem_0.mem[56];
wire [15:0] mem272 = dmem_0.mem[57];
wire [15:0] mem274 = dmem_0.mem[58];
wire [15:0] mem276 = dmem_0.mem[59];
wire [15:0] mem278 = dmem_0.mem[60];
wire [15:0] mem27A = dmem_0.mem[61];
wire [15:0] mem27C = dmem_0.mem[62];
wire [15:0] mem27E = dmem_0.mem[63];
wire [15:0] mem280 = dmem_0.mem[64];
 
 
// Interrupt vectors
//======================
 
wire [15:0] irq_vect_15 = rom_0.mem[(1<<(`ROM_MSB+1))-1]; // RESET Vector
wire [15:0] irq_vect_14 = rom_0.mem[(1<<(`ROM_MSB+1))-2]; // NMI
wire [15:0] irq_vect_13 = rom_0.mem[(1<<(`ROM_MSB+1))-3]; // IRQ 13
wire [15:0] irq_vect_12 = rom_0.mem[(1<<(`ROM_MSB+1))-4]; // IRQ 12
wire [15:0] irq_vect_11 = rom_0.mem[(1<<(`ROM_MSB+1))-5]; // IRQ 11
wire [15:0] irq_vect_10 = rom_0.mem[(1<<(`ROM_MSB+1))-6]; // IRQ 10
wire [15:0] irq_vect_09 = rom_0.mem[(1<<(`ROM_MSB+1))-7]; // IRQ 9
wire [15:0] irq_vect_08 = rom_0.mem[(1<<(`ROM_MSB+1))-8]; // IRQ 8
wire [15:0] irq_vect_07 = rom_0.mem[(1<<(`ROM_MSB+1))-9]; // IRQ 7
wire [15:0] irq_vect_06 = rom_0.mem[(1<<(`ROM_MSB+1))-10]; // IRQ 6
wire [15:0] irq_vect_05 = rom_0.mem[(1<<(`ROM_MSB+1))-11]; // IRQ 5
wire [15:0] irq_vect_04 = rom_0.mem[(1<<(`ROM_MSB+1))-12]; // IRQ 4
wire [15:0] irq_vect_03 = rom_0.mem[(1<<(`ROM_MSB+1))-13]; // IRQ 3
wire [15:0] irq_vect_02 = rom_0.mem[(1<<(`ROM_MSB+1))-14]; // IRQ 2
wire [15:0] irq_vect_01 = rom_0.mem[(1<<(`ROM_MSB+1))-15]; // IRQ 1
wire [15:0] irq_vect_00 = rom_0.mem[(1<<(`ROM_MSB+1))-16]; // IRQ 0
wire [15:0] irq_vect_15 = pmem_0.mem[(1<<(`PMEM_MSB+1))-1]; // RESET Vector
wire [15:0] irq_vect_14 = pmem_0.mem[(1<<(`PMEM_MSB+1))-2]; // NMI
wire [15:0] irq_vect_13 = pmem_0.mem[(1<<(`PMEM_MSB+1))-3]; // IRQ 13
wire [15:0] irq_vect_12 = pmem_0.mem[(1<<(`PMEM_MSB+1))-4]; // IRQ 12
wire [15:0] irq_vect_11 = pmem_0.mem[(1<<(`PMEM_MSB+1))-5]; // IRQ 11
wire [15:0] irq_vect_10 = pmem_0.mem[(1<<(`PMEM_MSB+1))-6]; // IRQ 10
wire [15:0] irq_vect_09 = pmem_0.mem[(1<<(`PMEM_MSB+1))-7]; // IRQ 9
wire [15:0] irq_vect_08 = pmem_0.mem[(1<<(`PMEM_MSB+1))-8]; // IRQ 8
wire [15:0] irq_vect_07 = pmem_0.mem[(1<<(`PMEM_MSB+1))-9]; // IRQ 7
wire [15:0] irq_vect_06 = pmem_0.mem[(1<<(`PMEM_MSB+1))-10]; // IRQ 6
wire [15:0] irq_vect_05 = pmem_0.mem[(1<<(`PMEM_MSB+1))-11]; // IRQ 5
wire [15:0] irq_vect_04 = pmem_0.mem[(1<<(`PMEM_MSB+1))-12]; // IRQ 4
wire [15:0] irq_vect_03 = pmem_0.mem[(1<<(`PMEM_MSB+1))-13]; // IRQ 3
wire [15:0] irq_vect_02 = pmem_0.mem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
wire [15:0] irq_vect_01 = pmem_0.mem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
wire [15:0] irq_vect_00 = pmem_0.mem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
/openmsp430/trunk/core/rtl/verilog/frontend.v
68,7 → 68,7
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
fe_rom_wait, // Frontend wait for ROM
fe_pmem_wait, // Frontend wait for Instruction fetch
gie, // General interrupt enable
irq, // Maskable interrupts
mclk, // Main system clock
110,7 → 110,7
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
input fe_rom_wait; // Frontend wait for ROM
input fe_pmem_wait; // Frontend wait for Instruction fetch
input gie; // General interrupt enable
input [13:0] irq; // Maskable interrupts
input mclk; // Main system clock
259,14 → 259,14
else pc <= pc_nxt;
 
// Check if ROM has been busy in order to retry ROM access
reg rom_busy;
reg pmem_busy;
always @(posedge mclk or posedge puc)
if (puc) rom_busy <= 16'h0000;
else rom_busy <= fe_rom_wait;
if (puc) pmem_busy <= 16'h0000;
else pmem_busy <= fe_pmem_wait;
// Memory interface
wire [15:0] mab = pc_nxt;
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | rom_busy | (dbg_halt_st & ~dbg_halt_cmd);
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
 
 
//
754,3 → 754,5
 
 
endmodule // frontend
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/alu.v
245,4 → 245,4
 
endmodule // alu
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
181,9 → 181,4
endmodule // template_periph_8b
 
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/periph/gpio.v
771,8 → 771,4
 
endmodule // gpio
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/periph/timerA.v
686,9 → 686,4
 
endmodule // timerA
 
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v
174,8 → 174,4
 
endmodule // template_periph_16b
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/register_file.v
342,6 → 342,4
 
endmodule // register_file
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/dbg_uart.v
265,9 → 265,4
endmodule // dbg_uart
 
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
266,10 → 266,4
endmodule // dbg_hwbrk
 
 
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/sfr.v
200,3 → 200,5
 
 
endmodule // sfr
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/dbg.v
265,9 → 265,9
// CPU_ID Register
//-----------------
 
wire [3:0] cpu_id_rom = `ROM_AWIDTH;
wire [3:0] cpu_id_ram = `RAM_AWIDTH;
wire [31:0] cpu_id = {`DBG_ID, cpu_id_rom, cpu_id_ram};
wire [3:0] cpu_id_pmem = `PMEM_AWIDTH;
wire [3:0] cpu_id_dmem = `DMEM_AWIDTH;
wire [31:0] cpu_id = {`DBG_ID, cpu_id_pmem, cpu_id_dmem};
 
 
// CPU_CTL Register
789,8 → 789,4
 
endmodule // dbg
 
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/clock_module.v
244,3 → 244,4
 
endmodule // clock_module
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/watchdog.v
214,7 → 214,4
 
endmodule // watchdog
 
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/execution_unit.v
364,3 → 364,4
 
endmodule // execution_unit
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/mem_backbone.v
42,21 → 42,21
 
// OUTPUTs
dbg_mem_din, // Debug unit Memory data input
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
eu_mdb_in, // Execution Unit Memory data bus input
fe_mdb_in, // Frontend Memory data bus input
fe_rom_wait, // Frontend wait for ROM
fe_pmem_wait, // Frontend wait for Instruction fetch
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_din, // RAM data input
ram_wen, // RAM write enable (low active)
rom_addr, // ROM address
rom_cen, // ROM chip enable (low active)
rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE--
rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF--
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
 
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
64,6 → 64,7
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dmem_dout, // Data Memory data output
eu_mab, // Execution Unit Memory address bus
eu_mb_en, // Execution Unit Memory bus enable
eu_mb_wr, // Execution Unit Memory bus write transfer
72,48 → 73,47
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
per_dout, // Peripheral data output
puc, // Main system reset
ram_dout, // RAM data output
rom_dout // ROM data output
pmem_dout, // Program Memory data output
puc // Main system reset
);
 
// OUTPUTs
//=========
output [15:0] dbg_mem_din; // Debug unit Memory data input
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
output [15:0] fe_mdb_in; // Frontend Memory data bus input
output fe_rom_wait; // Frontend wait for ROM
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`RAM_MSB:0] ram_addr; // RAM address
output ram_cen; // RAM chip enable (low active)
output [15:0] ram_din; // RAM data input
output [1:0] ram_wen; // RAM write enable (low active)
output [`ROM_MSB:0] rom_addr; // ROM address
output rom_cen; // ROM chip enable (low active)
output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE--
output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF--
output [15:0] dbg_mem_din; // Debug unit Memory data input
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
output [15:0] fe_mdb_in; // Frontend Memory data bus input
output fe_pmem_wait; // Frontend wait for Instruction fetch
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
 
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_addr; // Debug address for rd/wr access
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_mem_en; // Debug unit memory enable
input [1:0] dbg_mem_wr; // Debug unit memory write
input [14:0] eu_mab; // Execution Unit Memory address bus
input eu_mb_en; // Execution Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
input [14:0] fe_mab; // Frontend Memory address bus
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] per_dout; // Peripheral data output
input puc; // Main system reset
input [15:0] ram_dout; // RAM data output
input [15:0] rom_dout; // ROM data output
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_addr; // Debug address for rd/wr access
input [15:0] dbg_mem_dout; // Debug unit data output
input dbg_mem_en; // Debug unit memory enable
input [1:0] dbg_mem_wr; // Debug unit memory write
input [15:0] dmem_dout; // Data Memory data output
input [14:0] eu_mab; // Execution Unit Memory address bus
input eu_mb_en; // Execution Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution Unit Memory bus write transfer
input [15:0] eu_mdb_out; // Execution Unit Memory data bus output
input [14:0] fe_mab; // Frontend Memory address bus
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input puc; // Main system reset
 
 
//=============================================================================
124,48 → 124,48
//------------------
 
// Execution unit access
wire eu_ram_cen = ~(eu_mb_en & (eu_mab>=(`RAM_BASE>>1)) &
(eu_mab<((`RAM_BASE+`RAM_SIZE)>>1)));
wire [15:0] eu_ram_addr = eu_mab-(`RAM_BASE>>1);
wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1);
 
// Debug interface access
wire dbg_ram_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`RAM_BASE>>1)) &
(dbg_mem_addr[15:1]<((`RAM_BASE+`RAM_SIZE)>>1)));
wire [15:0] dbg_ram_addr = dbg_mem_addr[15:1]-(`RAM_BASE>>1);
wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1);
 
// RAM Interface
wire [`RAM_MSB:0] ram_addr = ~dbg_ram_cen ? dbg_ram_addr[`RAM_MSB:0] : eu_ram_addr[`RAM_MSB:0];
wire ram_cen = dbg_ram_cen & eu_ram_cen;
wire [1:0] ram_wen = ~(dbg_mem_wr | eu_mb_wr);
wire [15:0] ram_din = ~dbg_ram_cen ? dbg_mem_dout : eu_mdb_out;
wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
wire [1:0] dmem_wen = ~(dbg_mem_wr | eu_mb_wr);
wire [15:0] dmem_din = ~dbg_dmem_cen ? dbg_mem_dout : eu_mdb_out;
 
 
// ROM Interface
//------------------
parameter ROM_OFFSET = (16'hFFFF-`ROM_SIZE+1);
parameter PMEM_OFFSET = (16'hFFFF-`PMEM_SIZE+1);
 
// Execution unit access (only read access are accepted)
wire eu_rom_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(ROM_OFFSET>>1)));
wire [15:0] eu_rom_addr = eu_mab-(ROM_OFFSET>>1);
wire eu_pmem_cen = ~(eu_mb_en & ~|eu_mb_wr & (eu_mab>=(PMEM_OFFSET>>1)));
wire [15:0] eu_pmem_addr = eu_mab-(PMEM_OFFSET>>1);
 
// Front-end access
wire fe_rom_cen = ~(fe_mb_en & (fe_mab>=(ROM_OFFSET>>1)));
wire [15:0] fe_rom_addr = fe_mab-(ROM_OFFSET>>1);
wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
 
// Debug interface access
wire dbg_rom_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(ROM_OFFSET>>1)));
wire [15:0] dbg_rom_addr = dbg_mem_addr[15:1]-(ROM_OFFSET>>1);
wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1);
 
// ROM Interface (Execution unit has priority)
wire [`ROM_MSB:0] rom_addr = ~dbg_rom_cen ? dbg_rom_addr[`ROM_MSB:0] :
~eu_rom_cen ? eu_rom_addr[`ROM_MSB:0] : fe_rom_addr[`ROM_MSB:0];
wire rom_cen = fe_rom_cen & eu_rom_cen & dbg_rom_cen;
wire [1:0] rom_wen_dbg = ~dbg_mem_wr;
wire [15:0] rom_din_dbg = dbg_mem_dout;
wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
wire pmem_cen = fe_pmem_cen & eu_pmem_cen & dbg_pmem_cen;
wire [1:0] pmem_wen = ~dbg_mem_wr;
wire [15:0] pmem_din = dbg_mem_dout;
 
wire fe_rom_wait = (~fe_rom_cen & ~eu_rom_cen);
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
 
 
// Peripherals
189,27 → 189,27
// Whenever the frontend doesn't access the ROM, backup the data
 
// Detect whenever the data should be backuped and restored
reg fe_rom_cen_dly;
reg fe_pmem_cen_dly;
always @(posedge mclk or posedge puc)
if (puc) fe_rom_cen_dly <= 1'b0;
else fe_rom_cen_dly <= fe_rom_cen;
if (puc) fe_pmem_cen_dly <= 1'b0;
else fe_pmem_cen_dly <= fe_pmem_cen;
 
wire fe_rom_save = ( fe_rom_cen & ~fe_rom_cen_dly) & ~dbg_halt_st;
wire fe_rom_restore = (~fe_rom_cen & fe_rom_cen_dly) | dbg_halt_st;
wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
reg [15:0] rom_dout_bckup;
reg [15:0] pmem_dout_bckup;
always @(posedge mclk or posedge puc)
if (puc) rom_dout_bckup <= 16'h0000;
else if (fe_rom_save) rom_dout_bckup <= rom_dout;
if (puc) pmem_dout_bckup <= 16'h0000;
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
 
// Mux between the ROM data and the backup
reg rom_dout_bckup_sel;
reg pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc)
if (puc) rom_dout_bckup_sel <= 1'b0;
else if (fe_rom_save) rom_dout_bckup_sel <= 1'b1;
else if (fe_rom_restore) rom_dout_bckup_sel <= 1'b0;
if (puc) pmem_dout_bckup_sel <= 1'b0;
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
assign fe_mdb_in = rom_dout_bckup_sel ? rom_dout_bckup : rom_dout;
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
 
 
// Execution-Unit data Mux
219,11 → 219,11
reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc)
if (puc) eu_mdb_in_sel <= 2'b00;
else eu_mdb_in_sel <= {~eu_rom_cen, per_en};
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
 
// Mux
assign eu_mdb_in = eu_mdb_in_sel[1] ? rom_dout :
eu_mdb_in_sel[0] ? per_dout_val : ram_dout;
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
 
// Debug interface data Mux
//---------------------------------
232,15 → 232,13
reg [1:0] dbg_mem_din_sel;
always @(posedge mclk or posedge puc)
if (puc) dbg_mem_din_sel <= 2'b00;
else dbg_mem_din_sel <= {~dbg_rom_cen, dbg_per_en};
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
 
// Mux
assign dbg_mem_din = dbg_mem_din_sel[1] ? rom_dout :
dbg_mem_din_sel[0] ? per_dout_val : ram_dout;
assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
 
endmodule // mem_backbone
 
 
 
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
1,6 → 1,3
`ifdef OPENMSP430_DEFINES
`else
`define OPENMSP430_DEFINES
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
38,26 → 35,32
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`include "openMSP430_undefines.v"
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// ROM Size:
// 9 -> 1kB
// 10 -> 2kB
// 11 -> 4kB
// 12 -> 8kB
// 13 -> 16kB
`define ROM_AWIDTH 10
// Program Memory Size:
// 9 -> 1 kB
// 10 -> 2 kB
// 11 -> 4 kB
// 12 -> 8 kB
// 13 -> 16 kB
// 14 -> 32 kB
`define PMEM_AWIDTH 10
 
// RAM Size:
// Data Memory Size:
// 6 -> 128 B
// 7 -> 256 B
// 8 -> 512 B
// 9 -> 1 kB
// 10 -> 2 kB
`define RAM_AWIDTH 6
// 11 -> 4 kB
// 12 -> 8 kB
// 13 -> 16 kB
// 14 -> 32 kB
`define DMEM_AWIDTH 6
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
68,7 → 71,7
 
// Debug interface selection
// `define DBG_UART -> Enable UART (8N1) debug interface
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED YET
// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
//
`define DBG_UART
//`define DBG_JTAG
95,16 → 98,16
//==========================================================================//
//==========================================================================//
 
// ROM and RAM sizes
`define ROM_SIZE (2 << `ROM_AWIDTH)
`define RAM_SIZE (2 << `RAM_AWIDTH)
// Program and Data Memory sizes
`define PMEM_SIZE (2 << `PMEM_AWIDTH)
`define DMEM_SIZE (2 << `DMEM_AWIDTH)
 
// RAM Base Adresses
`define RAM_BASE 16'h0200 // RAM base address
// Data Memory Base Adresses
`define DMEM_BASE 16'h0200
 
// ROM & RAM most significant address bit (for 16 bit words)
`define ROM_MSB `ROM_AWIDTH-1
`define RAM_MSB `RAM_AWIDTH-1
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB `PMEM_AWIDTH-1
`define DMEM_MSB `DMEM_AWIDTH-1
 
 
// Instructions type
285,12 → 288,9
`endif
`else
`ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED YET
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
`else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
 
 
`endif
/openmsp430/trunk/core/rtl/verilog/openMSP430.v
41,72 → 41,72
module openMSP430 (
 
// OUTPUTs
aclk_en, // ACLK enable
dbg_freeze, // Freeze peripherals
dbg_uart_txd, // Debug interface: UART TXD
irq_acc, // Interrupt request accepted (one-hot signal)
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
puc, // Main system reset
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_din, // RAM data input
ram_wen, // RAM write enable (low active)
rom_addr, // ROM address
rom_cen, // ROM chip enable (low active)
rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE--
rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF--
smclk_en, // SMCLK enable
aclk_en, // ACLK enable
dbg_freeze, // Freeze peripherals
dbg_uart_txd, // Debug interface: UART TXD
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
irq_acc, // Interrupt request accepted (one-hot signal)
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
puc, // Main system reset
smclk_en, // SMCLK enable
 
// INPUTs
dbg_uart_rxd, // Debug interface: UART RXD
dco_clk, // Fast oscillator (fast clock)
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
ram_dout, // RAM data output
reset_n, // Reset Pin (low active)
rom_dout // ROM data output
dbg_uart_rxd, // Debug interface: UART RXD
dco_clk, // Fast oscillator (fast clock)
dmem_dout, // Data Memory data output
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
reset_n // Reset Pin (low active)
);
 
// OUTPUTs
//=========
output aclk_en; // ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_uart_txd; // Debug interface: UART TXD
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output mclk; // Main system clock
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output puc; // Main system reset
output [`RAM_MSB:0] ram_addr; // RAM address
output ram_cen; // RAM chip enable (low active)
output [15:0] ram_din; // RAM data input
output [1:0] ram_wen; // RAM write enable (low active)
output [`ROM_MSB:0] rom_addr; // ROM address
output rom_cen; // ROM chip enable (low active)
output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE--
output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF--
output smclk_en; // SMCLK enable
output aclk_en; // ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_uart_txd; // Debug interface: UART TXD
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output mclk; // Main system clock
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
output puc; // Main system reset
output smclk_en; // SMCLK enable
 
 
// INPUTs
//=========
input dbg_uart_rxd; // Debug interface: UART RXD
input dco_clk; // Fast oscillator (fast clock)
input [13:0] irq; // Maskable interrupts
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input nmi; // Non-maskable interrupt (asynchronous)
input [15:0] per_dout; // Peripheral data output
input [15:0] ram_dout; // RAM data output
input reset_n; // Reset Pin (active low)
input [15:0] rom_dout; // ROM data output
input dbg_uart_rxd; // Debug interface: UART RXD
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [13:0] irq; // Maskable interrupts
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input nmi; // Non-maskable interrupt (asynchronous)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input reset_n; // Reset Pin (active low)
 
 
 
214,7 → 214,7
.cpuoff (cpuoff), // Turns off the CPU
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
.fe_rom_wait (fe_rom_wait), // Frontend wait for ROM
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.gie (gie), // General interrupt enable
.irq (irq), // Maskable interrupts
.mclk (mclk), // Main system clock
280,21 → 280,21
 
// OUTPUTs
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.fe_rom_wait (fe_rom_wait), // Frontend wait for ROM
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.ram_addr (ram_addr), // RAM address
.ram_cen (ram_cen), // RAM chip enable (low active)
.ram_din (ram_din), // RAM data input
.ram_wen (ram_wen), // RAM write enable (low active)
.rom_addr (rom_addr), // ROM address
.rom_cen (rom_cen), // ROM chip enable (low active)
.rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE--
.rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF--
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
// INPUTs
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
302,6 → 302,7
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dmem_dout (dmem_dout), // Data Memory data output
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
310,9 → 311,8
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.per_dout (per_dout_or), // Peripheral data output
.puc (puc), // Main system reset
.ram_dout (ram_dout), // RAM data output
.rom_dout (rom_dout) // ROM data output
.pmem_dout (pmem_dout), // Program Memory data output
.puc (puc) // Main system reset
);
 
 
437,3 → 437,4
endmodule // openMSP430
 
`include "openMSP430_undefines.v"
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
0,0 → 1,493
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_undefines.v
//
// *Module Description:
// openMSP430 Verilog `undef file
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// Program Memory Size:
`ifdef PMEM_AWIDTH
`undef PMEM_AWIDTH
`endif
 
// Data Memory Size:
`ifdef DMEM_AWIDTH
`undef DMEM_AWIDTH
`endif
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`ifdef DBG_EN
`undef DBG_EN
`endif
 
// Debug interface selection
`ifdef DBG_UART
`undef DBG_UART
`endif
`ifdef DBG_JTAG
`undef DBG_JTAG
`endif
 
// Number of hardware breakpoints
`ifdef DBG_HWBRK_0
`undef DBG_HWBRK_0
`endif
`ifdef DBG_HWBRK_1
`undef DBG_HWBRK_1
`endif
`ifdef DBG_HWBRK_2
`undef DBG_HWBRK_2
`endif
`ifdef DBG_HWBRK_3
`undef DBG_HWBRK_3
`endif
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Program and Data Memory sizes
`ifdef PMEM_SIZE
`undef PMEM_SIZE
`endif
`ifdef DMEM_SIZE
`undef DMEM_SIZE
`endif
 
// Data Memory Base Adresses
`ifdef DMEM_BASE
`undef DMEM_BASE
`endif
 
// Program & Data Memory most significant address bit (for 16 bit words)
`ifdef PMEM_MSB
`undef PMEM_MSB
`endif
`ifdef DMEM_MSB
`undef DMEM_MSB
`endif
 
 
// Instructions type
`ifdef INST_SO
`undef INST_SO
`endif
`ifdef INST_JMP
`undef INST_JMP
`endif
`ifdef INST_TO
`undef INST_TO
`endif
 
// Single-operand arithmetic
`ifdef RRC
`undef RRC
`endif
`ifdef SWPB
`undef SWPB
`endif
`ifdef RRA
`undef RRA
`endif
`ifdef SXT
`undef SXT
`endif
`ifdef PUSH
`undef PUSH
`endif
`ifdef CALL
`undef CALL
`endif
`ifdef RETI
`undef RETI
`endif
`ifdef IRQ
`undef IRQ
`endif
 
// Conditional jump
`ifdef JNE
`undef JNE
`endif
`ifdef JEQ
`undef JEQ
`endif
`ifdef JNC
`undef JNC
`endif
`ifdef JC
`undef JC
`endif
`ifdef JN
`undef JN
`endif
`ifdef JGE
`undef JGE
`endif
`ifdef JL
`undef JL
`endif
`ifdef JMP
`undef JMP
`endif
 
// Two-operand arithmetic
`ifdef MOV
`undef MOV
`endif
`ifdef ADD
`undef ADD
`endif
`ifdef ADDC
`undef ADDC
`endif
`ifdef SUBC
`undef SUBC
`endif
`ifdef SUB
`undef SUB
`endif
`ifdef CMP
`undef CMP
`endif
`ifdef DADD
`undef DADD
`endif
`ifdef BIT
`undef BIT
`endif
`ifdef BIC
`undef BIC
`endif
`ifdef BIS
`undef BIS
`endif
`ifdef XOR
`undef XOR
`endif
`ifdef AND
`undef AND
`endif
 
// Addressing modes
`ifdef DIR
`undef DIR
`endif
`ifdef IDX
`undef IDX
`endif
`ifdef INDIR
`undef INDIR
`endif
`ifdef INDIR_I
`undef INDIR_I
`endif
`ifdef SYMB
`undef SYMB
`endif
`ifdef IMM
`undef IMM
`endif
`ifdef ABS
`undef ABS
`endif
`ifdef CONST
`undef CONST
`endif
 
// Execution state machine
`ifdef E_IRQ_0
`undef E_IRQ_0
`endif
`ifdef E_IRQ_1
`undef E_IRQ_1
`endif
`ifdef E_IRQ_2
`undef E_IRQ_2
`endif
`ifdef E_IRQ_3
`undef E_IRQ_3
`endif
`ifdef E_IRQ_4
`undef E_IRQ_4
`endif
`ifdef E_SRC_AD
`undef E_SRC_AD
`endif
`ifdef E_SRC_RD
`undef E_SRC_RD
`endif
`ifdef E_SRC_WR
`undef E_SRC_WR
`endif
`ifdef E_DST_AD
`undef E_DST_AD
`endif
`ifdef E_DST_RD
`undef E_DST_RD
`endif
`ifdef E_DST_WR
`undef E_DST_WR
`endif
`ifdef E_EXEC
`undef E_EXEC
`endif
`ifdef E_JUMP
`undef E_JUMP
`endif
`ifdef E_IDLE
`undef E_IDLE
`endif
 
// ALU control signals
`ifdef ALU_SRC_INV
`undef ALU_SRC_INV
`endif
`ifdef ALU_INC
`undef ALU_INC
`endif
`ifdef ALU_INC_C
`undef ALU_INC_C
`endif
`ifdef ALU_ADD
`undef ALU_ADD
`endif
`ifdef ALU_AND
`undef ALU_AND
`endif
`ifdef ALU_OR
`undef ALU_OR
`endif
`ifdef ALU_XOR
`undef ALU_XOR
`endif
`ifdef ALU_DADD
`undef ALU_DADD
`endif
`ifdef ALU_STAT_7
`undef ALU_STAT_7
`endif
`ifdef ALU_STAT_F
`undef ALU_STAT_F
`endif
`ifdef ALU_SHIFT
`undef ALU_SHIFT
`endif
`ifdef EXEC_NO_WR
`undef EXEC_NO_WR
`endif
 
// Debug interface
`ifdef DBG_UART_WR
`undef DBG_UART_WR
`endif
`ifdef DBG_UART_BW
`undef DBG_UART_BW
`endif
`ifdef DBG_UART_ADDR
`undef DBG_UART_ADDR
`endif
 
// Debug interface CPU_CTL register
`ifdef HALT
`undef HALT
`endif
`ifdef RUN
`undef RUN
`endif
`ifdef ISTEP
`undef ISTEP
`endif
`ifdef SW_BRK_EN
`undef SW_BRK_EN
`endif
`ifdef FRZ_BRK_EN
`undef FRZ_BRK_EN
`endif
`ifdef RST_BRK_EN
`undef RST_BRK_EN
`endif
`ifdef CPU_RST
`undef CPU_RST
`endif
 
// Debug interface CPU_STAT register
`ifdef HALT_RUN
`undef HALT_RUN
`endif
`ifdef PUC_PND
`undef PUC_PND
`endif
`ifdef SWBRK_PND
`undef SWBRK_PND
`endif
`ifdef HWBRK0_PND
`undef HWBRK0_PND
`endif
`ifdef HWBRK1_PND
`undef HWBRK1_PND
`endif
 
// Debug interface BRKx_CTL register
`ifdef BRK_MODE_RD
`undef BRK_MODE_RD
`endif
`ifdef BRK_MODE_WR
`undef BRK_MODE_WR
`endif
`ifdef BRK_MODE
`undef BRK_MODE
`endif
`ifdef BRK_EN
`undef BRK_EN
`endif
`ifdef BRK_I_EN
`undef BRK_I_EN
`endif
`ifdef BRK_RANGE
`undef BRK_RANGE
`endif
 
// Basic clock module: BCSCTL1 Control Register
`ifdef DIVAx
`undef DIVAx
`endif
 
// Basic clock module: BCSCTL2 Control Register
`ifdef SELS
`undef SELS
`endif
`ifdef DIVSx
`undef DIVSx
`endif
 
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
 
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`ifdef DBG_SWBRK_OP
`undef DBG_SWBRK_OP
`endif
 
// Debug interface ID
`ifdef DBG_ID
`undef DBG_ID
`endif
 
// Debug UART interface auto data synchronization
`ifdef DBG_UART_AUTO_SYNC
`undef DBG_UART_AUTO_SYNC
`endif
 
// Debug UART interface data rate
`ifdef DBG_UART_BAUD
`undef DBG_UART_BAUD
`endif
`ifdef DBG_DCO_FREQ
`undef DBG_DCO_FREQ
`endif
`ifdef DBG_UART_CNT
`undef DBG_UART_CNT
`endif
openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: openmsp430/trunk/core/sim/rtl_sim/run =================================================================== --- openmsp430/trunk/core/sim/rtl_sim/run (revision 32) +++ openmsp430/trunk/core/sim/rtl_sim/run (revision 33)
openmsp430/trunk/core/sim/rtl_sim/run Property changes : Modified: svn:ignore ## -1,5 +1,5 ## *.log -rom.* +pmem.* stimulus.v *.vcd simv Index: openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v =================================================================== --- openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v (revision 32) +++ openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v (revision 33) @@ -39,8 +39,8 @@ `define LONG_TIMEOUT -reg [3:0] dbg_id_rom; -reg [3:0] dbg_id_ram; +reg [3:0] dbg_id_pmem; +reg [3:0] dbg_id_dmem; reg [31:0] dbg_id; initial @@ -56,9 +56,9 @@ // TEST CPU REGISTERS //-------------------------------------------------------- - dbg_id_rom = `ROM_AWIDTH; - dbg_id_ram = `RAM_AWIDTH; - dbg_id = {`DBG_ID, dbg_id_rom, dbg_id_ram}; + dbg_id_pmem = `PMEM_AWIDTH; + dbg_id_dmem = `DMEM_AWIDTH; + dbg_id = {`DBG_ID, dbg_id_pmem, dbg_id_dmem}; dbg_uart_wr(CPU_ID_LO , 16'hffff); dbg_uart_rd(CPU_ID_LO);
/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
77,7 → 77,7
# Cleanup #
###############################################################################
echo "Cleanup..."
rm -rf rom.*
rm -rf pmem.*
rm -rf stimulus.v
 
 
89,31 → 89,31
echo " ======================================================="
 
# Create links
ln -s $asmfile rom.s43
ln -s $asmfile pmem.s43
ln -s $verfile stimulus.v
 
# Make local copy of the openMSP403 configuration file and remove comments
cp $incfile ./rom.inc
sed -i "/^\/\// s,.*,," rom.inc
cp $incfile ./pmem.inc
sed -i "/^\/\// s,.*,," pmem.inc
 
# Get ROM size
romsize=`grep ROM_AWIDTH rom.inc | grep -v ROM_MSB | grep -v ROM_SIZE`
romsize=${romsize##* }
romsize=$((2<<$romsize))
# Get Program Memory size
pmemsize=`grep PMEM_AWIDTH pmem.inc | grep -v PMEM_MSB | grep -v PMEM_SIZE`
pmemsize=${pmemsize##* }
pmemsize=$((2<<$pmemsize))
 
# Get RAM size
ramsize=`grep RAM_AWIDTH rom.inc | grep -v RAM_MSB | grep -v RAM_SIZE`
ramsize=${ramsize##* }
ramsize=$((2<<$ramsize))
# Get Data Memory size
dmemsize=`grep DMEM_AWIDTH pmem.inc | grep -v DMEM_MSB | grep -v DMEM_SIZE`
dmemsize=${dmemsize##* }
dmemsize=$((2<<$dmemsize))
 
# Compile assembler code
echo "Compile, link & generate IHEX file (ROM: $romsize B, RAM: $ramsize B)..."
../bin/asm2ihex.sh rom rom.s43 $deffile $romsize $ramsize
echo "Compile, link & generate IHEX file (Program Memory: $pmemsize B, Data Memory: $dmemsize B)..."
../bin/asm2ihex.sh pmem pmem.s43 $deffile $pmemsize $dmemsize
 
# Generate ROM memory file
# Generate Program memory file
echo "Convert IHEX file to Verilog MEMH format..."
../bin/ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size $romsize
../bin/ihex2mem.tcl -ihex pmem.ihex -out pmem.mem -mem_size $pmemsize
 
# Start verilog simulation
echo "Start Verilog simulation..."
../bin/rtlsim.sh stimulus.v rom.mem $submitfile
../bin/rtlsim.sh stimulus.v pmem.mem $submitfile
/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
40,8 → 40,8
EXPECTED_ARGS=3
if [ $# -ne $EXPECTED_ARGS ]; then
echo "ERROR : wrong number of arguments"
echo "USAGE : rtlsim.sh <verilog stimulus file> <rom file> <submit file>"
echo "Example : rtlsim.sh ./stimulus.v rom.mem ../src/submit.f"
echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
exit 1
fi
 
/openmsp430/trunk/core/sim/rtl_sim/bin/template.def
3,8 → 3,8
OUTPUT_ARCH(msp:110)
MEMORY
{
text (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
data (rwx) : ORIGIN = 0x0200, LENGTH = RAM_SIZE
text (rx) : ORIGIN = PMEM_BASE, LENGTH = PMEM_SIZE
data (rwx) : ORIGIN = 0x0200, LENGTH = DMEM_SIZE
vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x20
bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K
infomem(rx) : ORIGIN = 0x1000, LENGTH = 256
/openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
40,8 → 40,8
EXPECTED_ARGS=5
if [ $# -ne $EXPECTED_ARGS ]; then
echo "ERROR : wrong number of arguments"
echo "USAGE : asm2ihex.sh <test name> <test assembler file> <definition file> <rom size> <ram size>"
echo "Example : asm2ihex.sh c-jump_jge ../src/c-jump_jge.s43 ../bin/template.def 2048 128"
echo "USAGE : asm2ihex.sh <test name> <test assembler file> <definition file> <prog mem size> <data mem size>"
echo "Example : asm2ihex.sh c-jump_jge ../src/c-jump_jge.s43 ../bin/template.def 2048 128"
exit 1
fi
 
64,14 → 64,14
# Generate the linker definition file #
###############################################################################
 
RAM_SIZE=$5
ROM_SIZE=$4
ROM_BASE=$((0x10000-$ROM_SIZE))
DMEM_SIZE=$5
PMEM_SIZE=$4
PMEM_BASE=$((0x10000-$PMEM_SIZE))
 
cp $3 ./rom.def
sed -i "s/ROM_BASE/$ROM_BASE/g" rom.def
sed -i "s/ROM_SIZE/$ROM_SIZE/g" rom.def
sed -i "s/RAM_SIZE/$RAM_SIZE/g" rom.def
cp $3 ./pmem.def
sed -i "s/PMEM_BASE/$PMEM_BASE/g" pmem.def
sed -i "s/PMEM_SIZE/$PMEM_SIZE/g" pmem.def
sed -i "s/DMEM_SIZE/$DMEM_SIZE/g" pmem.def
 
 
###############################################################################
79,5 → 79,5
###############################################################################
msp430-as -alsm $2 -o $1.o > $1.l43
msp430-objdump -xdsStr $1.o >> $1.l43
msp430-ld -T ./rom.def $1.o -o $1.elf
msp430-ld -T ./pmem.def $1.o -o $1.elf
msp430-objcopy -O ihex $1.elf $1.ihex

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