OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

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    from Rev 32 to Rev 33
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  •

Rev 32 → Rev 33

/trunk/bench/verilog/system.v
860,6 → 860,8
$display("PCI target images' tests finished!") ;
 
transaction_ordering ;
 
target_completion_expiration ;
$display(" ") ;
$display("PCI transaction ordering tests finished!") ;
end
15687,11 → 15689,15
reg [31:0] temp_val1 ;
reg [31:0] temp_val2 ;
reg ok ;
reg ok_wb ;
reg ok_pci ;
 
reg [31:0] pci_image_base ;
integer i ;
integer clocks_after_completion ;
reg error_monitor_done ;
reg test_mem ;
 
reg error_monitor_done ;
begin:main
pci_ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
pci_ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
15703,7 → 15709,13
lat_tim_cls_offset = 12'hC ;
pci_device_ctrl_offset = 12'h4 ;
 
pci_image_base = Target_Base_Addr_R[1] ;
`ifdef HOST
test_mem = 1'b1 ;
pci_image_base = Target_Base_Addr_R[1] & 32'hFFFF_FFFE ;
`else
test_mem = !`PCI_BA1_MEM_IO ;
pci_image_base = Target_Base_Addr_R[1] ;
`endif
 
// enable master & target operation
test_name = "BRIDGE CONFIGURATION FOR DELAYED COMPLETION EXPIRATION TEST" ;
15716,7 → 15728,7
end
 
// prepare image control register
config_write( pci_ctrl_offset, 32'h0000_0001, 4'hF, ok) ;
config_write( pci_ctrl_offset, 32'h0000_0002, 4'hF, ok) ;
if ( ok !== 1 )
begin
$display("Target completion expiration testing failed! Failed to write P_IMG_CTRL1 register! Time %t ", $time) ;
15751,8 → 15763,7
disable main ;
end
 
// carefull - first value here is 7, because bit 31 of ICR is software reset!
config_write( icr_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
config_write( icr_offset, 32'h0000_0000, 4'hF, ok ) ;
if ( ok !== 1 )
begin
$display("Target completion expiration testing failed! Failed to write IC register! Time %t ", $time) ;
15772,9 → 15783,603
pci_image_base[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
 
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
test_name = "FLUSH OF DELAYED READ NOT COMPLETED IN 2^^16 CYCLES FROM PCI TARGET UNIT" ;
test_name = "FLUSH OF DELAYED READ UNCOMPLETED IN 2^^16 CYCLES FROM PCI TARGET UNIT" ;
master1_check_received_data = 0 ;
 
ok_pci = 1 ;
// start a delayed read request
fork
begin
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base, 32'h1234_5678,
1, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Retry_On);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
do_pause( 1 ) ;
end
begin:error_monitor1
@(error_event_int) ;
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
ok_pci = 0 ;
end
begin
if ( test_mem )
wb_transaction_progress_monitor( pci_image_base, 1'b0, 4, 1'b1, ok_wb ) ;
else
wb_transaction_progress_monitor( pci_image_base, 1'b0, 1, 1'b1, ok_wb ) ;
 
if ( ok_wb !== 1 )
begin
test_fail("Bridge failed to process Target Memory read correctly") ;
disable main ;
end
if ( ok_pci )
disable error_monitor1 ;
end
join
 
clocks_after_completion = 0 ;
// now do another - different transaction
fork
begin
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base + 4, 32'h1234_5678,
1, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Retry_On);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
 
while ( clocks_after_completion < 32'h0000_FFF0 )
begin
@(posedge pci_clock) ;
clocks_after_completion = clocks_after_completion + 1 ;
end
 
do_pause('hFF) ;
 
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base + 4, 32'h1234_5678,
1, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Retry_On);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 1, `Test_Target_Retry_On ) ;
 
do_pause( 1 ) ;
end
begin:error_monitor2
@(error_event_int) ;
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
ok_pci = 0 ;
end
begin
wait ( clocks_after_completion === 32'h0000_FFF0 ) ;
repeat( 'hFF )
@(posedge pci_clock) ;
 
if ( test_mem )
wb_transaction_progress_monitor( pci_image_base + 4, 1'b0, 4, 1'b1, ok_wb ) ;
else
wb_transaction_progress_monitor( pci_image_base + 4, 1'b0, 1, 1'b1, ok_wb ) ;
 
if ( ok_wb !== 1 )
begin
test_fail("Bridge failed to process Target Memory read correctly") ;
disable main ;
end
 
repeat(4)
@(posedge pci_clock) ;
 
fork
begin
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base + 4, 32'h1234_5678,
4, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 1, `Test_Target_Normal_Completion ) ;
 
do_pause(1) ;
end
begin
pci_transaction_progress_monitor( pci_image_base + 4, test_mem ? `BC_MEM_READ : `BC_IO_READ, test_mem ? 4 : 1, 0, 1'b1, 1'b0, 0, ok ) ;
if ( ok_pci )
disable error_monitor2 ;
end
join
end
join
 
if ( ok && ok_pci && ok_wb )
test_ok ;
 
if ( ok !== 1 )
begin
$display("Target completion expiration testing failed! Failed to write P_AM1 register! Time %t ", $time) ;
test_fail("write to PCI Address Mask register failed") ;
disable main ;
end
 
// check statuses after this situation - none should be set
test_name = "PCI DEVICE ERROR STATUS BITS' STATES AFTER COMPLETION EXPIRED IN PCI TARGET UNIT" ;
config_read( pci_device_ctrl_offset, 4'hC, temp_val1 ) ;
if ( ok !== 1 )
begin
$display("Target completion expiration testing failed! Failed to read pci device status register! Time %t ", $time) ;
test_fail("read from pci device status register failed") ;
disable main ;
end
 
if ( temp_val1[31] )
begin
$display("Target completion expiration testing failed! Detected parity error bit set for no reason! Time %t ", $time) ;
test_fail("detected parity error bit was set for no reason") ;
end
 
if ( temp_val1[30] )
begin
$display("Target completion expiration testing failed! Signaled system error bit set for no reason! Time %t ", $time) ;
test_fail("signaled system error bit was set for no reason") ;
end
 
if ( temp_val1[29] )
begin
$display("Target completion expiration testing failed! Received master abort bit set for no reason! Time %t ", $time) ;
test_fail("received master abort bit was set for no reason") ;
end
 
if ( temp_val1[28] )
begin
$display("Target completion expiration testing failed! Received Target abort bit set for no reason! Time %t ", $time) ;
test_fail("received target abort bit was set for no reason") ;
end
 
if ( temp_val1[27] )
begin
$display("Target completion expiration testing failed! Signaled Target abort bit set for no reason! Time %t ", $time) ;
test_fail("signaled target abort bit was set for no reason") ;
end
 
if ( temp_val1[24] )
begin
$display("Target completion expiration testing failed! Master Data parity error bit set for no reason! Time %t ", $time) ;
test_fail("Master Data parity error bit was set for no reason") ;
end
 
test_name = "PCI TARGET UNIT ERROR REPORTING REGISTER VALUE AFTER COMPLETION EXPIRED" ;
config_read( pci_err_cs_offset, 4'hF, temp_val1 ) ;
if ( temp_val1[8] !== 0 )
begin
$display("Target completion expiration testing failed! Error status bit in PCI error reporting register set for no reason! Time %t ", $time) ;
test_fail("Error status bit in PCI error reporting register was set for no reason") ;
end
// test target retry counter expiration
// set wb slave to retry response
wishbone_slave.cycle_response(3'b001, tb_subseq_waits, 8'd255);
test_name = "RETRY COUNTER EXPIRATION DURING WRITE THROUGH PCI TARGET UNIT" ;
ok_pci = 1 ;
 
fork
begin
if ( test_mem == 1 )
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_1,
pci_image_base, 32'hDEAD_BEAF, 4'hA,
1, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
else
PCIU_IO_WRITE( `Test_Master_1, pci_image_base, 32'hDEAD_BEAF, 4'hA, 1, `Test_Target_Normal_Completion) ;
 
do_pause(1) ;
 
// do another write with same address and different data
if ( test_mem == 1 )
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_1,
pci_image_base, 32'h8765_4321, 4'h0,
1, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
else
PCIU_IO_WRITE( `Test_Master_1, pci_image_base, 32'h8765_4321, 4'h0, 1, `Test_Target_Normal_Completion) ;
do_pause(1) ;
end
begin
for ( i = 0 ; i < `WB_RTY_CNT_MAX ; i = i + 1 )
begin
wb_transaction_progress_monitor( pci_image_base, 1'b1, 0, 1'b1, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
end
 
// set WB slave to normal completion
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
wb_transaction_progress_monitor( pci_image_base, 1'b1, 1, 1'b1, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
if ( ok_pci )
disable error_monitor3 ;
end
begin:error_monitor3
@(error_event_int) ;
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
ok_pci = 0 ;
end
join
 
if ( ok_wb && ok_pci )
begin
test_ok ;
end
 
test_name = "ERROR STATUS REGISTER VALUE CHECK AFTER RETRY COUNTER EXPIRED" ;
config_read( pci_err_cs_offset, 4'hF, temp_val1 ) ;
if ( temp_val1[8] !== 1'b1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master should signal an error when retry counter expires during a write! Time %t", $time) ;
test_fail("error wasn't reported, when retry counter expired during posted write through PCI Target unit") ;
end
 
if ( temp_val1[9] !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master should set Error Source bit when retry counter expires during a write! Time %t", $time) ;
test_fail("error source bit wasn't set, when retry counter expired during posted write through PCI Target unit") ;
end
 
if ( temp_val1[10] !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master should set Retry Expired bit when retry counter expires during a write! Time %t", $time) ;
test_fail("retry expired bit wasn't set, when retry counter expired during posted write through PCI Target unit") ;
end
 
if ( temp_val1[27:24] !== (test_mem ? `BC_MEM_WRITE : `BC_IO_WRITE) )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in bus command field in error control and status register when retry counter expired during a write! Time %t", $time) ;
test_fail("bus command field in error control and status register was wrong when retry counter expired during posted write through PCI Target unit") ;
end
if ( temp_val1[31:28] !== 4'hA )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in byte enable field in error control and status register when retry counter expired during a write! Time %t", $time) ;
test_fail("byte enable field in error control and status register was wrong when retry counter expired during posted write through PCI Target unit") ;
end
 
// clear error status register
config_write( pci_err_cs_offset, temp_val1, 4'h2, ok ) ;
test_name = "ERROR ADDRESS REGISTER VALUE CHECK AFTER RETRY COUNTER EXPIRED" ;
config_read( pci_err_cs_offset + 4, 4'hF, temp_val1 ) ;
if ( temp_val1 !== pci_image_base )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in error address register when retry counter expired during a write! Time %t", $time) ;
test_fail("value in error address register was wrong when retry counter expired during posted write through PCI Target unit") ;
end
 
test_name = "ERROR DATA REGISTER VALUE CHECK AFTER RETRY COUNTER EXPIRED" ;
config_read( pci_err_cs_offset + 8, 4'hF, temp_val1 ) ;
if ( temp_val1 !== 32'hDEAD_BEAF )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in error data register when retry counter expired during a write! Time %t", $time) ;
test_fail("value in error data register was wrong when retry counter expired during posted write through PCI Target unit") ;
end
 
test_name = "RETRY COUNTER EXPIRATION DURING READ THROUGH PCI TARGET UNIT" ;
ok_pci = 1 ;
wishbone_slave.cycle_response(3'b001, tb_subseq_waits, 8'd255);
i = 0 ;
fork
begin
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base + 4, 32'h1234_5678,
2, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Retry_Before);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 2, `Test_Target_Retry_Before ) ;
do_pause( 1 ) ;
 
end
begin
for ( i = 0 ; i < `WB_RTY_CNT_MAX ; i = i + 1 )
begin
wb_transaction_progress_monitor( pci_image_base + 4, 1'b0, 0, 1'b1, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
end
// set WB slave to normal completion
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'h0);
 
fork
begin
repeat(4)
@(posedge pci_clock) ;
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base, 32'h8765_4321,
1, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Retry_On);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h8765_4321, 4'h0, 1, `Test_Target_Retry_On ) ;
 
do_pause(1) ;
end
begin
 
wb_transaction_progress_monitor( pci_image_base, 1'b0, test_mem ? 4 : 1, 1'b1, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
end
join
 
repeat( 4 )
@(posedge pci_clock) ;
 
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base, 32'h8765_4321,
1, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base, 32'h8765_4321, 4'h0, 1, `Test_Target_Normal_Completion ) ;
do_pause(1) ;
 
if ( ok_pci )
disable error_monitor4 ;
end
begin:error_monitor4
@(error_event_int) ;
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
ok_pci = 0 ;
end
join
 
if ( ok_wb && ok_pci )
test_ok ;
 
test_name = "ERROR STATUS REGISTER VALUE CHECK AFTER RETRY COUNTER EXPIRED DURING READ" ;
config_read( pci_err_cs_offset, 4'hF, temp_val1 ) ;
if ( temp_val1[8] !== 1'b0 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master shouldn't signal an error when retry counter expires during a read! Time %t", $time) ;
test_fail("error shouldn't be reported, when retry counter expires during read through PCI Target unit") ;
end
test_name = "NO RESPONSE COUNTER EXPIRATION DURING READ THROUGH PCI TARGET UNIT" ;
ok_pci = 1 ;
wishbone_slave.cycle_response(3'b000, tb_subseq_waits, 8'd255);
fork
begin
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base + 4, 32'h1234_5678,
2, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Retry_Before);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h1234_5678, 4'h0, 2, `Test_Target_Retry_Before ) ;
do_pause( 1 ) ;
end
begin
wb_transaction_progress_monitor( pci_image_base + 4, 1'b0, 0, 1'b1, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
repeat(4)
@(posedge pci_clock) ;
fork
begin
if ( test_mem )
PCIU_MEM_READ("MEM_READ ", `Test_Master_1,
pci_image_base + 4, 32'h8765_4321,
1, 8'h7_0, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Abort_On);
else
PCIU_IO_READ( `Test_Master_1, pci_image_base + 4, 32'h8765_4321, 4'h0, 1, `Test_Target_Abort_On ) ;
 
do_pause(1) ;
end
begin
pci_transaction_progress_monitor( pci_image_base + 4, test_mem ? `BC_MEM_READ : `BC_IO_READ, 0, 0, 1'b1, 1'b0, 1'b0, ok ) ;
if ( ok !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! PCI transaction progress monitor detected invalid transaction or none at all on PCI bus! Time %t", $time) ;
test_fail("PCI transaction progress monitor detected invalid transaction or none at all on PCI bus") ;
disable main ;
end
end
join
if ( ok_pci )
disable error_monitor5 ;
end
begin:error_monitor5
@(error_event_int) ;
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
ok_pci = 0 ;
end
join
if ( ok_wb && ok_pci )
test_ok ;
 
test_name = "ERROR STATUS REGISTER VALUE CHECK AFTER NO RESPONSE COUNTER EXPIRED DURING READ" ;
config_read( pci_err_cs_offset, 4'hF, temp_val1 ) ;
if ( temp_val1[8] !== 1'b0 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master shouldn't signal an error when retry counter expires during a read! Time %t", $time) ;
test_fail("error shouldn't be reported, when retry counter expires during read through PCI Target unit") ;
end
 
test_name = "PCI DEVICE STATUS REGISTER VALUE CHECK AFTER NO RESPONSE COUNTER EXPIRED DURING READ" ;
config_read( pci_device_ctrl_offset, 4'hF, temp_val1 ) ;
if ( temp_val1[25] !== 1'b1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Signaled Target Abort bit not set when PCI Target terminated with target abort! Time %t", $time) ;
test_fail("Signaled Target Abort bit was not set when PCI Target terminated with target abort") ;
end
config_write( pci_device_ctrl_offset, temp_val1, 4'hF, ok ) ;
 
test_name = "NO RESPONSE COUNTER EXPIRATION DURING WRITE THROUGH PCI TARGET UNIT" ;
ok_pci = 1 ;
wishbone_slave.cycle_response(3'b000, tb_subseq_waits, 8'd255);
 
fork
begin
if ( test_mem == 1 )
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_1,
pci_image_base, 32'hBEAF_DEAD, 4'h0,
1, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
else
PCIU_IO_WRITE( `Test_Master_1, pci_image_base, 32'hBEAF_DEAD, 4'h0, 1, `Test_Target_Normal_Completion) ;
do_pause(1) ;
// do another write with same address and different data
if ( test_mem == 1 )
PCIU_MEM_WRITE ("MEM_WRITE ", `Test_Master_1,
pci_image_base, 32'h8765_6789, 4'h0,
3, `Test_One_Zero_Master_WS, `Test_One_Zero_Target_WS,
`Test_Devsel_Medium, `Test_Target_Normal_Completion);
else
PCIU_IO_WRITE( `Test_Master_1, pci_image_base, 32'h8765_6789, 4'h0, 1, `Test_Target_Normal_Completion) ;
 
do_pause(1) ;
$display("PCIU monitor (WB bus) will complain in following section for a few times - no WB response test!") ;
$fdisplay(pciu_mon_log_file_desc,
"******************************************** Monitor will complain in following section for a few times - testbench is intentionally causing no response *********************************************") ;
end
begin
wb_transaction_progress_monitor( pci_image_base, 1'b1, 0, 1'b1, ok_wb ) ;
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
 
wishbone_slave.cycle_response(3'b100, tb_subseq_waits, 8'd255);
if ( test_mem )
wb_transaction_progress_monitor( pci_image_base, 1'b1, 3, 1'b1, ok_wb ) ;
else
wb_transaction_progress_monitor( pci_image_base, 1'b1, 1, 1'b1, ok_wb ) ;
 
if ( ok_wb !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB transaction progress monitor detected invalid transaction or none at all on WB bus! Time %t", $time) ;
test_fail("WB transaction progress monitor detected invalid transaction or none at all on WB bus") ;
disable main ;
end
 
if ( ok_pci )
disable error_monitor6 ;
end
begin:error_monitor6
@(error_event_int) ;
test_fail("PCI behavioral master or PCI monitor detected error on PCI bus") ;
ok_pci = 0 ;
end
join
 
$display("PCIU monitor (WB bus) should NOT complain any more!") ;
$fdisplay(pciu_mon_log_file_desc,
"******************************************** Monitor should NOT complain any more ********************************************************************************************************************") ;
 
test_name = "ERROR STATUS REGISTER VALUE CHECK AFTER NO RESPONSE COUNTER EXPIRED DURING TARGET WRITE" ;
config_read( pci_err_cs_offset, 4'hF, temp_val1 ) ;
if ( temp_val1[8] !== 1'b1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master should signal an error when no response counter expires during a write! Time %t", $time) ;
test_fail("error wasn't reported, when no response counter expired during posted write through PCI Target unit") ;
end
if ( temp_val1[9] !== 0 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master should not set Error Source bit when no response counter expires during a write! Time %t", $time) ;
test_fail("error source bit was set, when no response counter expired during posted write through PCI Target unit") ;
end
if ( temp_val1[10] !== 1 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! WB Master should set Retry Expired bit when no response counter expires during a write! Time %t", $time) ;
test_fail("retry expired bit wasn't set, when no response counter expired during posted write through PCI Target unit") ;
end
if ( temp_val1[27:24] !== (test_mem ? `BC_MEM_WRITE : `BC_IO_WRITE) )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in bus command field in error control and status register when no response counter expired during a write! Time %t", $time) ;
test_fail("bus command field in error control and status register was wrong when no response counter expired during posted write through PCI Target unit") ;
end
if ( temp_val1[31:28] !== 4'h0 )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in byte enable field in error control and status register when no response counter expired during a write! Time %t", $time) ;
test_fail("byte enable field in error control and status register was wrong when no response counter expired during posted write through PCI Target unit") ;
end
// clear error status register
config_write( pci_err_cs_offset, temp_val1, 4'h2, ok ) ;
 
test_name = "ERROR ADDRESS REGISTER VALUE CHECK AFTER NO RESPONSE COUNTER EXPIRED" ;
config_read( pci_err_cs_offset + 4, 4'hF, temp_val1 ) ;
if ( temp_val1 !== pci_image_base )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in error address register when no response counter expired during a write! Time %t", $time) ;
test_fail("value in error address register was wrong when no response counter expired during posted write through PCI Target unit") ;
end
test_name = "ERROR DATA REGISTER VALUE CHECK AFTER NO RESPONSE COUNTER EXPIRED" ;
config_read( pci_err_cs_offset + 8, 4'hF, temp_val1 ) ;
if ( temp_val1 !== 32'hBEAF_DEAD )
begin
$display("WISHBONE Master Retry Counter expiration test failed! Invalid value in error data register when no response counter expired during a write! Time %t", $time) ;
test_fail("value in error data register was wrong when no response counter expired during posted write through PCI Target unit") ;
end
// disable current image - write address mask register
config_write( pci_am_offset, 32'h7FFF_FFFF, 4'hF, ok ) ;
end
endtask // target_completion_expired
 
/trunk/rtl/verilog/fifo_control.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:28 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
67,7 → 70,6
wenable_in,
reset_in,
flush_in,
almost_full_out,
full_out,
almost_empty_out,
empty_out,
93,8 → 95,8
// flush input
input flush_in ;
 
// almost full and empy status outputs
output almost_full_out, almost_empty_out;
// almost empy status output
output almost_empty_out;
 
// full and empty status outputs
output full_out, empty_out;
122,7 → 124,6
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
 
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
134,9 → 135,8
reg empty ;
reg full ;
 
// almost_empty and almost_full tag - implemented as latches
// almost_empty tag
reg almost_empty ;
reg almost_full ;
 
// write allow wire - writes are allowed when fifo is not full
wire wallow = wenable_in && ~full ;
150,9 → 150,6
// full output assignment
assign full_out = full ;
 
// almost full output assignment
assign almost_full_out = almost_full && ~full ;
 
// clear generation for FFs and registers
wire clear = reset_in || flush_in ;
 
199,8 → 196,8
begin
if (clear)
begin
// initial value is 5 - one more than initial value of read address
raddr_plus_one <= #`FF_DELAY 5 ;
// initial value is 4 - one more than initial value of read address
raddr_plus_one <= #`FF_DELAY 4 ;
end
else if (rallow)
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
210,8 → 207,8
always@(posedge rclock_in or posedge clear)
begin
if (clear)
// initial value is 4
raddr <= #`FF_DELAY 4 ;
// initial value is 3
raddr <= #`FF_DELAY 3 ;
else if (rallow)
raddr <= #`FF_DELAY raddr_plus_one ;
end
219,23 → 216,10
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 4 Grey addresses:
- rgrey_minus2 is Grey Code of address two before current address
- rgrey_minus1 is Grey Code of address one before current address
- rgrey_addr is Grey Code of current read address
- rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
// grey code register for two before read address
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
// initial value is 0
rgrey_minus2 <= #`FF_DELAY 0 ;
end
else
if (rallow)
rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
end
 
// grey code register for one before read address
always@(posedge rclock_in or posedge clear)
242,8 → 226,8
begin
if (clear)
begin
// initial value is 1
rgrey_minus1 <= #`FF_DELAY 1 ;
// initial value is 0
rgrey_minus1 <= #`FF_DELAY 0 ;
end
else
if (rallow)
255,8 → 239,8
begin
if (clear)
begin
// initial value is 3
rgrey_addr <= #`FF_DELAY 3 ;
// initial value is 1
rgrey_addr <= #`FF_DELAY 1 ;
end
else
if (rallow)
268,8 → 252,8
begin
if (clear)
begin
// initial value is 2
rgrey_next <= #`FF_DELAY 2 ;
// initial value is 3
rgrey_next <= #`FF_DELAY 3 ;
end
else
if (rallow)
287,8 → 271,8
begin
if (clear)
begin
// initial value is 1
wgrey_minus1 <= #`FF_DELAY 1 ;
// initial value is 0
wgrey_minus1 <= #`FF_DELAY 0 ;
end
else
if (wallow)
300,8 → 284,8
begin
if (clear)
begin
// initial value is 3
wgrey_addr <= #`FF_DELAY 3 ;
// initial value is 1
wgrey_addr <= #`FF_DELAY 1 ;
end
else
if (wallow)
313,8 → 297,8
begin
if (clear)
begin
// initial value is 2
wgrey_next <= #`FF_DELAY 2 ;
// initial value is 3
wgrey_next <= #`FF_DELAY 3 ;
end
else
if (wallow)
325,8 → 309,8
always@(posedge wclock_in or posedge clear)
begin
if (clear)
// initial value 4
waddr <= #`FF_DELAY 4 ;
// initial value 3
waddr <= #`FF_DELAY 3 ;
else
if (wallow)
waddr <= #`FF_DELAY waddr + 1'b1 ;
342,8 → 326,7
It remains set if nothing is read/written from/to fifo. All operations are synchronized on write clock.
--------------------------------------------------------------------------------------------------------------------------------*/
wire comb_full = wgrey_next == rgrey_addr ;
wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
wire comb_two_left = wgrey_next == rgrey_minus2 ;
wire comb_almost_full = wgrey_next == rgrey_minus1 ;
 
//combinatorial input to Registered full FlipFlop
wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
356,17 → 339,6
full <= #`FF_DELAY reg_full ;
end
 
// input for almost full flip flop
wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
 
always@(posedge clear or posedge wclock_in)
begin
if (clear)
almost_full <= #`FF_DELAY 1'b0 ;
else
almost_full <= #`FF_DELAY reg_almost_full_in ;
end
 
/*------------------------------------------------------------------------------------------------------------------------------
Registered empty control:
registered empty is set on rising edge of rclock_in when one location is occupied and read from it. It remains set until
/trunk/rtl/verilog/wb_master.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/02/19 16:32:37 mihad
// Modified testbench and fixed some bugs
//
// Revision 1.3 2002/02/01 15:25:13 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
62,51 → 65,51
`include "timescale.v"
//synopsys translate_on
 
module WB_MASTER ( wb_clock_in, // CLK_I
reset_in, // RST_I
module WB_MASTER ( wb_clock_in, // CLK_I
reset_in, // RST_I
pci_tar_read_request,
pci_tar_address,
pci_tar_cmd,
pci_tar_be,
pci_tar_burst_ok,
pci_cache_line_size,
cache_lsize_not_zero,
wb_read_done_out,
w_attempt,
pci_tar_address,
pci_tar_cmd,
pci_tar_be,
pci_tar_burst_ok,
pci_cache_line_size,
cache_lsize_not_zero,
wb_read_done_out,
w_attempt,
 
pcir_fifo_wenable_out,
pcir_fifo_data_out,
pcir_fifo_be_out,
pcir_fifo_control_out,
//pcir_fifo_renable_out, for PCI Target !!!
//pcir_fifo_data_in, for PCI Target !!!
//pcir_fifo_be_in, for PCI Target !!!
//pcir_fifo_control_in, for PCI Target !!!
//pcir_fifo_flush_out, for PCI Target !!!
//pcir_fifo_almost_empty_in, for PCI Target !!!
//pcir_fifo_empty_in, NOT used
//pcir_fifo_transaction_ready_in, NOT used
//pciw_fifo_wenable_out, for PCI Target !!!
//pciw_fifo_addr_data_out, for PCI Target !!!
//pciw_fifo_cbe_out, for PCI Target !!!
//pciw_fifo_control_out, for PCI Target !!!
pciw_fifo_renable_out,
pciw_fifo_addr_data_in,
pciw_fifo_cbe_in,
pciw_fifo_control_in,
//pciw_fifo_flush_out, NOT used
//pciw_fifo_almost_full_in, for PCI Target !!!
//pciw_fifo_full_in, for PCI Target !!!
pciw_fifo_almost_empty_in,
pciw_fifo_empty_in,
pciw_fifo_transaction_ready_in,
pcir_fifo_wenable_out,
pcir_fifo_data_out,
pcir_fifo_be_out,
pcir_fifo_control_out,
//pcir_fifo_renable_out, for PCI Target !!!
//pcir_fifo_data_in, for PCI Target !!!
//pcir_fifo_be_in, for PCI Target !!!
//pcir_fifo_control_in, for PCI Target !!!
//pcir_fifo_flush_out, for PCI Target !!!
//pcir_fifo_almost_empty_in, for PCI Target !!!
//pcir_fifo_empty_in, NOT used
//pcir_fifo_transaction_ready_in, NOT used
//pciw_fifo_wenable_out, for PCI Target !!!
//pciw_fifo_addr_data_out, for PCI Target !!!
//pciw_fifo_cbe_out, for PCI Target !!!
//pciw_fifo_control_out, for PCI Target !!!
pciw_fifo_renable_out,
pciw_fifo_addr_data_in,
pciw_fifo_cbe_in,
pciw_fifo_control_in,
//pciw_fifo_flush_out, NOT used
//pciw_fifo_almost_full_in, for PCI Target !!!
//pciw_fifo_full_in, for PCI Target !!!
pciw_fifo_almost_empty_in,
pciw_fifo_empty_in,
pciw_fifo_transaction_ready_in,
 
pci_error_sig_out,
pci_error_bc,
write_rty_cnt_exp_out,
error_source_out,
read_rty_cnt_exp_out,
pci_error_sig_out,
pci_error_bc,
write_rty_cnt_exp_out,
error_source_out,
read_rty_cnt_exp_out,
 
CYC_O,
STB_O,
124,12 → 127,12
/*----------------------------------------------------------------------------------------------------------------------
Various parameters needed for state machine and other stuff
----------------------------------------------------------------------------------------------------------------------*/
parameter S_IDLE = `WB_FSM_BITS'h0 ;
parameter S_WRITE = `WB_FSM_BITS'h1 ;
parameter S_WRITE_ERR_RTY = `WB_FSM_BITS'h2 ;
parameter S_READ = `WB_FSM_BITS'h3 ;
parameter S_READ_RTY = `WB_FSM_BITS'h4 ;
parameter S_TURN_ARROUND = `WB_FSM_BITS'h5 ;
parameter S_IDLE = `WB_FSM_BITS'h0 ;
parameter S_WRITE = `WB_FSM_BITS'h1 ;
parameter S_WRITE_ERR_RTY = `WB_FSM_BITS'h2 ;
parameter S_READ = `WB_FSM_BITS'h3 ;
parameter S_READ_RTY = `WB_FSM_BITS'h4 ;
parameter S_TURN_ARROUND = `WB_FSM_BITS'h5 ;
 
/*----------------------------------------------------------------------------------------------------------------------
System signals inputs
136,119 → 139,119
wb_clock_in - WISHBONE bus clock input
reset_in - system reset input controlled by bridge's reset logic
----------------------------------------------------------------------------------------------------------------------*/
input wb_clock_in ;
input reset_in ;
input wb_clock_in ;
input reset_in ;
 
/*----------------------------------------------------------------------------------------------------------------------
Control signals from PCI Target for READS to PCIR_FIFO
---------------------------------------------------------------------------------------------------------------------*/
input pci_tar_read_request ; // read request from PCI Target
input [31:0] pci_tar_address ; // address for requested read from PCI Target
input [3:0] pci_tar_cmd ; // command for requested read from PCI Target
input [3:0] pci_tar_be ; // byte enables for requested read from PCI Target
input pci_tar_burst_ok ;
input [7:0] pci_cache_line_size ; // CACHE line size register value for burst length
input cache_lsize_not_zero ;
output wb_read_done_out ; // read done and PCIR_FIFO has data ready
output w_attempt ;
input pci_tar_read_request ; // read request from PCI Target
input [31:0] pci_tar_address ; // address for requested read from PCI Target
input [3:0] pci_tar_cmd ; // command for requested read from PCI Target
input [3:0] pci_tar_be ; // byte enables for requested read from PCI Target
input pci_tar_burst_ok ;
input [7:0] pci_cache_line_size ; // CACHE line size register value for burst length
input cache_lsize_not_zero ;
output wb_read_done_out ; // read done and PCIR_FIFO has data ready
output w_attempt ;
 
reg wb_read_done_out ;
reg wb_read_done ;
reg wb_read_done_out ;
reg wb_read_done ;
 
/*----------------------------------------------------------------------------------------------------------------------
PCIR_FIFO control signals used for sinking data into PCIR_FIFO and status monitoring
PCIR_FIFO control signals used for sinking data into PCIR_FIFO and status monitoring
---------------------------------------------------------------------------------------------------------------------*/
output pcir_fifo_wenable_out ; // PCIR_FIFO write enable output
output [31:0] pcir_fifo_data_out ; // data output to PCIR_FIFO
output [3:0] pcir_fifo_be_out ; // byte enable output to PCIR_FIFO
output [3:0] pcir_fifo_control_out ; // control bus output to PCIR_FIFO
output pcir_fifo_wenable_out ; // PCIR_FIFO write enable output
output [31:0] pcir_fifo_data_out ; // data output to PCIR_FIFO
output [3:0] pcir_fifo_be_out ; // byte enable output to PCIR_FIFO
output [3:0] pcir_fifo_control_out ; // control bus output to PCIR_FIFO
 
reg [31:0] pcir_fifo_data_out ;
reg pcir_fifo_wenable_out ;
reg pcir_fifo_wenable ;
reg [3:0] pcir_fifo_control_out ;
reg [3:0] pcir_fifo_control ;
reg [31:0] pcir_fifo_data_out ;
reg pcir_fifo_wenable_out ;
reg pcir_fifo_wenable ;
reg [3:0] pcir_fifo_control_out ;
reg [3:0] pcir_fifo_control ;
 
/*----------------------------------------------------------------------------------------------------------------------
PCIW_FIFO control signals used for fetching data from PCIW_FIFO and status monitoring
---------------------------------------------------------------------------------------------------------------------*/
output pciw_fifo_renable_out ; // read enable for PCIW_FIFO output
input [31:0] pciw_fifo_addr_data_in ; // address and data input from PCIW_FIFO
input [3:0] pciw_fifo_cbe_in ; // command and byte_enables from PCIW_FIFO
input [3:0] pciw_fifo_control_in ; // control bus input from PCIW_FIFO
input pciw_fifo_almost_empty_in ; // almost empty status indicator from PCIW_FIFO
input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
input pciw_fifo_transaction_ready_in ; // write transaction is ready in PCIW_FIFO
output pciw_fifo_renable_out ; // read enable for PCIW_FIFO output
input [31:0] pciw_fifo_addr_data_in ; // address and data input from PCIW_FIFO
input [3:0] pciw_fifo_cbe_in ; // command and byte_enables from PCIW_FIFO
input [3:0] pciw_fifo_control_in ; // control bus input from PCIW_FIFO
input pciw_fifo_almost_empty_in ; // almost empty status indicator from PCIW_FIFO
input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
input pciw_fifo_transaction_ready_in ; // write transaction is ready in PCIW_FIFO
 
reg pciw_fifo_renable_out ;
reg pciw_fifo_renable ;
reg pciw_fifo_renable_out ;
reg pciw_fifo_renable ;
 
/*----------------------------------------------------------------------------------------------------------------------
Control INPUT / OUTPUT signals for configuration space reporting registers !!!
---------------------------------------------------------------------------------------------------------------------*/
output pci_error_sig_out ; // When error occures (on WB bus, retry counter, etc.)
output [3:0] pci_error_bc ; // bus command at which error occured !
output write_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during write transaction!
output read_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during read transaction!
// if error_source is '0' other side didn't respond
// if error_source is '1' other side RETRIED for max retry counter value
output error_source_out ; // Signaling error source - '0' other WB side signaled error OR didn't respond
// if '1' wridge counted max value in retry counter because of RTY responds
reg pci_error_sig_out ;
reg write_rty_cnt_exp_out ;
reg read_rty_cnt_exp_out ;
reg error_source_out ;
output pci_error_sig_out ; // When error occures (on WB bus, retry counter, etc.)
output [3:0] pci_error_bc ; // bus command at which error occured !
output write_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during write transaction!
output read_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during read transaction!
// if error_source is '0' other side didn't respond
// if error_source is '1' other side RETRIED for max retry counter value
output error_source_out ; // Signaling error source - '0' other WB side signaled error OR didn't respond
// if '1' wridge counted max value in retry counter because of RTY responds
reg pci_error_sig_out ;
reg write_rty_cnt_exp_out ;
reg read_rty_cnt_exp_out ;
reg error_source_out ;
 
/*----------------------------------------------------------------------------------------------------------------------
WISHBONE bus interface signals - can be connected directly to WISHBONE bus
---------------------------------------------------------------------------------------------------------------------*/
output CYC_O ; // cycle indicator output
output STB_O ; // strobe output - data is valid when strobe and cycle indicator are high
output WE_O ; // write enable output - 1 - write operation, 0 - read operation
output [3:0] SEL_O ; // Byte select outputs
output [31:0] ADR_O ; // WISHBONE address output
input [31:0] MDATA_I ; // WISHBONE slave interface input data bus
output [31:0] MDATA_O ; // WISHBONE slave interface output data bus
input ACK_I ; // Acknowledge input - qualifies valid data on data output bus or received data on data input bus
input RTY_I ; // retry input - signals from WISHBONE slave that cycle should be terminated and retried later
input ERR_I ; // Signals from WISHBONE slave that access resulted in an error
output CAB_O ; // consecutive address burst output - indicated that master will do a serial address transfer in current cycle
output CYC_O ; // cycle indicator output
output STB_O ; // strobe output - data is valid when strobe and cycle indicator are high
output WE_O ; // write enable output - 1 - write operation, 0 - read operation
output [3:0] SEL_O ; // Byte select outputs
output [31:0] ADR_O ; // WISHBONE address output
input [31:0] MDATA_I ; // WISHBONE slave interface input data bus
output [31:0] MDATA_O ; // WISHBONE slave interface output data bus
input ACK_I ; // Acknowledge input - qualifies valid data on data output bus or received data on data input bus
input RTY_I ; // retry input - signals from WISHBONE slave that cycle should be terminated and retried later
input ERR_I ; // Signals from WISHBONE slave that access resulted in an error
output CAB_O ; // consecutive address burst output - indicated that master will do a serial address transfer in current cycle
 
reg CYC_O ;
reg STB_O ;
reg WE_O ;
reg [3:0] SEL_O ;
reg [31:0] MDATA_O ;
reg CAB_O ;
reg CYC_O ;
reg STB_O ;
reg WE_O ;
reg [3:0] SEL_O ;
reg [31:0] MDATA_O ;
reg CAB_O ;
 
 
/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
LOGIC, COUNTERS, STATE MACHINE and some control register bits
=============================================================
LOGIC, COUNTERS, STATE MACHINE and some control register bits
=============================================================
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
###########################################################################################################*/
 
reg last_data_transferred ; // signal is set by STATE MACHINE after each complete transfere !
reg last_data_transferred ; // signal is set by STATE MACHINE after each complete transfere !
 
// wire for write attempt - 1 when PCI Target attempt to write and PCIW_FIFO has a write transaction ready
`ifdef REGISTER_WBM_OUTPUTS
reg w_attempt;
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
w_attempt <= #`FF_DELAY 1'b0;
else
begin
if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in)
w_attempt <= #`FF_DELAY 1'b1;
else
if (last_data_transferred)
w_attempt <= #`FF_DELAY 1'b0;
end
end
reg w_attempt;
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
w_attempt <= #`FF_DELAY 1'b0;
else
begin
if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in)
w_attempt <= #`FF_DELAY 1'b1;
else
if (last_data_transferred)
w_attempt <= #`FF_DELAY 1'b0;
end
end
`else
assign w_attempt = ( pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in ) ;
assign w_attempt = ( pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in ) ;
`endif
 
// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full !
257,266 → 260,225
wire r_attempt = ( pci_tar_read_request && !w_attempt);// pciw_fifo_empty_in ) ;
 
// Signal is used for reads on WB, when there is retry!
reg first_wb_data_access ;
reg first_wb_data_access ;
 
reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo
reg last_data_from_pciw_fifo_reg ;
reg last_data_to_pcir_fifo ; // signal tells when there will be last data for pcir_fifo
reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo
reg last_data_from_pciw_fifo_reg ;
reg last_data_to_pcir_fifo ; // signal tells when there will be last data for pcir_fifo
 
// Logic used in State Machine logic implemented out of State Machine because of less delay!
always@(pciw_fifo_control_in or pciw_fifo_almost_empty_in)
begin
if (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in) // if last data is going to be transfered
last_data_from_pciw_fifo <= 1'b1 ; // signal for last data from PCIW_FIFO
else
last_data_from_pciw_fifo <= 1'b0 ;
if (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in) // if last data is going to be transfered
last_data_from_pciw_fifo <= 1'b1 ; // signal for last data from PCIW_FIFO
else
last_data_from_pciw_fifo <= 1'b0 ;
end
 
reg read_count_load;
reg read_count_enable;
reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;
always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd)
begin
if (cache_lsize_not_zero)
if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) )
// If cache line size is larger than FIFO or BC_MEM_READ_MUL command is performed!
max_read_count = `PCIR_DEPTH - 1'b1;
else
max_read_count = pci_cache_line_size ;
else
max_read_count = 1'b1;
end
reg read_count_load;
reg read_count_enable;
reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;
always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd)
begin
if (cache_lsize_not_zero)
if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) )
// If cache line size is larger than FIFO or BC_MEM_READ_MUL command is performed!
max_read_count = `PCIR_DEPTH - 1'b1;
else
max_read_count = pci_cache_line_size ;
else
max_read_count = 1'b1;
end
 
reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;
reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;
 
// cache line bound indicator - it signals when data for one complete cacheline was read
wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;
// cache line bound indicator - it signals when data for one complete cacheline was read
wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;
 
reg read_bound ;
always@(posedge wb_clock_in or posedge reset_in)
begin
if ( reset_in )
read_bound <= #`FF_DELAY 1'b0 ;
else if (read_count_load)
read_bound <= #`FF_DELAY 1'b0 ;
else if ( read_count_enable )
read_bound <= #`FF_DELAY read_bound_comb ;
end
reg read_bound ;
always@(posedge wb_clock_in or posedge reset_in)
begin
if ( reset_in )
read_bound <= #`FF_DELAY 1'b0 ;
else if (read_count_load)
read_bound <= #`FF_DELAY 1'b0 ;
else if ( read_count_enable )
read_bound <= #`FF_DELAY read_bound_comb ;
end
 
// down counter with load
always@(posedge reset_in or posedge wb_clock_in)
begin
if (reset_in)
read_count <= #`FF_DELAY 0 ;
else
if (read_count_load)
read_count <= #`FF_DELAY max_read_count ;
else
if (read_count_enable)
read_count <= #`FF_DELAY read_count - 1'b1 ;
end
// down counter with load
always@(posedge reset_in or posedge wb_clock_in)
begin
if (reset_in)
read_count <= #`FF_DELAY 0 ;
else
if (read_count_load)
read_count <= #`FF_DELAY max_read_count ;
else
if (read_count_enable)
read_count <= #`FF_DELAY read_count - 1'b1 ;
end
 
// Logic used in State Machine logic implemented out of State Machine because of less delay!
// definition of signal telling, when there is last data written into FIFO
always@(pci_tar_cmd or pci_tar_burst_ok or read_bound)
begin
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
case ({pci_tar_cmd, pci_tar_burst_ok})
{`BC_MEM_READ, 1'b1},
{`BC_MEM_READ_LN, 1'b1} :
begin // when burst cycle
if (read_bound)
last_data_to_pcir_fifo <= 1'b1 ;
else
last_data_to_pcir_fifo <= 1'b0 ;
end
{`BC_MEM_READ_MUL, 1'b1} :
begin // when burst cycle
if (read_bound)
last_data_to_pcir_fifo <= 1'b1 ;
else
last_data_to_pcir_fifo <= 1'b0 ;
end
default :
// {`BC_IO_READ, 1'b0},
// {`BC_IO_READ, 1'b1},
// {`BC_MEM_READ, 1'b0},
// {`BC_MEM_READ_LN, 1'b0},
// {`BC_MEM_READ_MUL, 1'b0}:
begin // when single cycle
last_data_to_pcir_fifo <= 1'b1 ;
end
endcase
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
case ({pci_tar_cmd, pci_tar_burst_ok})
{`BC_MEM_READ, 1'b1},
{`BC_MEM_READ_LN, 1'b1} :
begin // when burst cycle
if (read_bound)
last_data_to_pcir_fifo <= 1'b1 ;
else
last_data_to_pcir_fifo <= 1'b0 ;
end
{`BC_MEM_READ_MUL, 1'b1} :
begin // when burst cycle
if (read_bound)
last_data_to_pcir_fifo <= 1'b1 ;
else
last_data_to_pcir_fifo <= 1'b0 ;
end
default :
// {`BC_IO_READ, 1'b0},
// {`BC_IO_READ, 1'b1},
// {`BC_MEM_READ, 1'b0},
// {`BC_MEM_READ_LN, 1'b0},
// {`BC_MEM_READ_MUL, 1'b0}:
begin // when single cycle
last_data_to_pcir_fifo <= 1'b1 ;
end
endcase
end
 
reg [3:0] wb_no_response_cnt ;
reg [3:0] wb_response_value ;
reg wait_for_wb_response ;
reg set_retry ; //
reg [3:0] wb_no_response_cnt ;
reg [3:0] wb_response_value ;
reg wait_for_wb_response ;
reg set_retry ; //
 
// internal WB no response retry generator counter!
always@(posedge reset_in or posedge wb_clock_in)
begin
if (reset_in)
wb_no_response_cnt <= #`FF_DELAY 4'h0 ;
else
wb_no_response_cnt <= #`FF_DELAY wb_response_value ;
if (reset_in)
wb_no_response_cnt <= #`FF_DELAY 4'h0 ;
else
wb_no_response_cnt <= #`FF_DELAY wb_response_value ;
end
// internal WB no response retry generator logic
always@(wait_for_wb_response or wb_no_response_cnt or ACK_I or ERR_I or RTY_I)
always@(wait_for_wb_response or wb_no_response_cnt)
begin
if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry
begin
wb_response_value <= 4'h0 ;
set_retry <= 1'b1 ;
end
else
begin
if (ACK_I || ERR_I || RTY_I) // if device responded, then ZERO must be written into counter
wb_response_value <= 4'h0 ;
else
if (wait_for_wb_response)
wb_response_value <= wb_no_response_cnt + 1'h1 ; // count clocks when no response
else
wb_response_value <= wb_no_response_cnt ;
set_retry <= 1'b0 ;
end
if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry
begin
wb_response_value <= 4'h0 ;
set_retry <= 1'b1 ;
end
else
begin
if (wait_for_wb_response)
wb_response_value <= wb_no_response_cnt + 1'h1 ; // count clocks when no response
else
wb_response_value <= 4'h0 ;
set_retry <= 1'b0 ;
end
end
 
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
reg [7:0] rty_counter ; // output from retry counter
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
reg rty_counter_max_value ; // signal tells when retry counter riches maximum value!
reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere
wire retry = RTY_I || set_retry ; // retry signal - logic OR function between RTY_I and internal WB no response retry!
reg [7:0] rty_counter ; // output from retry counter
reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value
reg rty_counter_almost_max_value ; // signal tells when retry counter riches maximum value - 1!
reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere
 
// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset
// for reseting the retry counter
always@(posedge reset_in or posedge wb_clock_in)
begin
if (reset_in)
reset_rty_cnt <= 1'b1 ; // asynchronous set when reset signal is active
else
reset_rty_cnt <= ACK_I || ERR_I || last_data_transferred ; // synchronous set after completed transfere
if (reset_in)
reset_rty_cnt <= 1'b1 ; // asynchronous set when reset signal is active
else
reset_rty_cnt <= ACK_I || ERR_I || last_data_transferred ; // synchronous set after completed transfere
end
 
// Retry counter register control
always@(posedge reset_in or posedge wb_clock_in)
begin
if (reset_in)
rty_counter <= #`FF_DELAY 8'h00 ;
else
begin
if (reset_rty_cnt)
rty_counter <= #`FF_DELAY 8'h00 ;
else if (retry)
rty_counter <= #`FF_DELAY rty_counter_in ;
end
if (reset_in)
rty_counter <= #`FF_DELAY 8'h00 ;
else
begin
if (reset_rty_cnt)
rty_counter <= #`FF_DELAY 8'h00 ;
else if (retry)
rty_counter <= #`FF_DELAY rty_counter_in ;
end
end
// Retry counter logic
always@(rty_counter)
begin
if(rty_counter == `WB_RTY_CNT_MAX) // stop counting
begin
rty_counter_in <= rty_counter ;
rty_counter_max_value <= 1'b1 ;
end
else
begin
rty_counter_in <= rty_counter + 1'b1 ; // count up
rty_counter_max_value <= 1'b0 ;
end
end
if(rty_counter == `WB_RTY_CNT_MAX - 1'b1) // stop counting
begin
rty_counter_in <= rty_counter ;
rty_counter_almost_max_value <= 1'b1 ;
end
else
begin
rty_counter_in <= rty_counter + 1'b1 ; // count up
rty_counter_almost_max_value <= 1'b0 ;
end
end
 
/*reg [7:0] cache_line ; // output from cache line down-counter
reg [7:0] cache_line_in ; // input to cache line counter
reg cache_line_into_cnt ; // control signal for loading cache line size to counter
reg cache_line_count ; // control signal for count enable
reg cache_line_reg_used ; // if pci_cache_line_size is ZERO then all PCIR_FIFO is read
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
reg [31:0] addr_cnt_in ; // input address value to address counter
reg addr_into_cnt ; // control signal for loading starting address into counter
reg addr_count ; // control signal for count enable
reg [3:0] bc_register ; // used when error occures during writes!
 
assign cache_line_wire = cache_line ;
// cache line size down-counter register control
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in) // reset counter
cache_line <= #`FF_DELAY 8'h00 ;
else
cache_line <= #`FF_DELAY cache_line_in ; // count down or hold value depending on cache line counter logic
end
// cache line size down-counter logic
always@(cache_line_into_cnt or cache_line_count or pci_cache_line_size or cache_lsize_not_zero or cache_line)
begin
if (cache_line_into_cnt) // load cache line size into counter
begin
if (cache_lsize_not_zero)
cache_line_in = pci_cache_line_size ;
else
cache_line_in = 8'h01 ;
end
else
if (cache_line_count)
begin
cache_line_in = cache_line - 1'h1 ; // count down
end
else
begin
cache_line_in = cache_line ;
end
end
*/
 
 
reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output
reg [31:0] addr_cnt_in ; // input address value to address counter
reg addr_into_cnt ; // control signal for loading starting address into counter
reg addr_count ; // control signal for count enable
reg [3:0] bc_register ; // used when error occures during writes!
 
// wb address counter register control
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in) // reset counter
begin
addr_cnt_out <= #`FF_DELAY 32'h0000_0000 ;
bc_register <= #`FF_DELAY 4'h0 ;
end
else
begin
addr_cnt_out <= #`FF_DELAY addr_cnt_in ; // count up or hold value depending on cache line counter logic
if (addr_into_cnt)
bc_register <= #`FF_DELAY pciw_fifo_cbe_in ;
end
if (reset_in) // reset counter
begin
addr_cnt_out <= #`FF_DELAY 32'h0000_0000 ;
bc_register <= #`FF_DELAY 4'h0 ;
end
else
begin
addr_cnt_out <= #`FF_DELAY addr_cnt_in ; // count up or hold value depending on cache line counter logic
if (addr_into_cnt)
bc_register <= #`FF_DELAY pciw_fifo_cbe_in ;
end
end
 
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
wire io_memory_bus_command = !pci_tar_cmd[3] && !pci_tar_cmd[2] ;
wire io_memory_bus_command = !pci_tar_cmd[3] && !pci_tar_cmd[2] ;
 
// wb address counter logic
always@(addr_into_cnt or r_attempt or addr_count or pciw_fifo_addr_data_in or pci_tar_address or addr_cnt_out or
io_memory_bus_command)
io_memory_bus_command)
begin
if (addr_into_cnt) // load starting address into counter
begin
if (r_attempt)
begin // if read request, then load read addresss from PCI Target
addr_cnt_in = {pci_tar_address[31:2], pci_tar_address[1] && io_memory_bus_command,
pci_tar_address[0] && io_memory_bus_command} ;
end
else
begin // if not read request, then load write address from PCIW_FIFO
addr_cnt_in = pciw_fifo_addr_data_in[31:0] ;
end
end
else
if (addr_count)
begin
addr_cnt_in = addr_cnt_out + 3'h4 ; // count up for 32-bit alligned address
end
else
begin
addr_cnt_in = addr_cnt_out ;
end
if (addr_into_cnt) // load starting address into counter
begin
if (r_attempt)
begin // if read request, then load read addresss from PCI Target
addr_cnt_in = {pci_tar_address[31:2], pci_tar_address[1] && io_memory_bus_command,
pci_tar_address[0] && io_memory_bus_command} ;
end
else
begin // if not read request, then load write address from PCIW_FIFO
addr_cnt_in = pciw_fifo_addr_data_in[31:0] ;
end
end
else
if (addr_count)
begin
addr_cnt_in = addr_cnt_out + 3'h4 ; // count up for 32-bit alligned address
end
else
begin
addr_cnt_in = addr_cnt_out ;
end
end
 
reg wb_stb_o ; // Internal signal for driwing STB_O on WB bus
523,72 → 485,72
reg wb_we_o ; // Internal signal for driwing WE_O on WB bus
reg wb_cyc_o ; // Internal signal for driwing CYC_O on WB bus and for enableing burst signal generation
 
reg retried ; // Signal is output value from FF and is set for one clock period after retried_d is set
reg retried_d ; // Signal is set whenever cycle is retried and is input to FF for delaying -> used in S_IDLE state
reg retried ; // Signal is output value from FF and is set for one clock period after retried_d is set
reg retried_d ; // Signal is set whenever cycle is retried and is input to FF for delaying -> used in S_IDLE state
reg retried_write;
reg rty_i_delayed; // Dignal used for determinig the source of retry!
 
reg first_data_is_burst ; // Signal is set in S_WRITE or S_READ states, when data transfere is burst!
reg first_data_is_burst_reg ;
wire burst_transfer ; // This signal is set when data transfere is burst and is reset with RESET or last data transfered
reg first_data_is_burst ; // Signal is set in S_WRITE or S_READ states, when data transfere is burst!
reg first_data_is_burst_reg ;
wire burst_transfer ; // This signal is set when data transfere is burst and is reset with RESET or last data transfered
 
// FFs output signals tell, when there is first data out from FIFO (for BURST checking)
// and for delaying retried signal
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in) // reset signals
begin
retried <= #`FF_DELAY 1'b0 ;
retried_write <= #`FF_DELAY 1'b0 ;
rty_i_delayed <= #`FF_DELAY 1'B0 ;
end
else
begin
retried <= #`FF_DELAY retried_d ; // delaying retried signal
retried_write <= #`FF_DELAY retried ;
rty_i_delayed <= #`FF_DELAY RTY_I ;
end
if (reset_in) // reset signals
begin
retried <= #`FF_DELAY 1'b0 ;
retried_write <= #`FF_DELAY 1'b0 ;
rty_i_delayed <= #`FF_DELAY 1'B0 ;
end
else
begin
retried <= #`FF_DELAY retried_d ; // delaying retried signal
retried_write <= #`FF_DELAY retried ;
rty_i_delayed <= #`FF_DELAY RTY_I ;
end
end
 
// Determinig if first data is a part of BURST or just a single transfere!
always@(addr_into_cnt or r_attempt or pci_tar_burst_ok or max_read_count or
pciw_fifo_control_in or pciw_fifo_empty_in)
pciw_fifo_control_in or pciw_fifo_empty_in)
begin
if (addr_into_cnt)
begin
if (r_attempt)
begin
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
if (pci_tar_burst_ok && (max_read_count != 8'h1))
first_data_is_burst <= 1'b1 ;
else
first_data_is_burst <= 1'b0 ;
end
else
begin
first_data_is_burst <= 1'b0 ;
end
end
else
first_data_is_burst <= pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in ;
if (addr_into_cnt)
begin
if (r_attempt)
begin
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok
if (pci_tar_burst_ok && (max_read_count != 8'h1))
first_data_is_burst <= 1'b1 ;
else
first_data_is_burst <= 1'b0 ;
end
else
begin
first_data_is_burst <= 1'b0 ;
end
end
else
first_data_is_burst <= pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in ;
end
 
// FF for seting and reseting burst_transfer signal
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
first_data_is_burst_reg <= #`FF_DELAY 1'b0 ;
else
begin
if (last_data_transferred || first_data_is_burst)
first_data_is_burst_reg <= #`FF_DELAY ~last_data_transferred ;
end
if (reset_in)
first_data_is_burst_reg <= #`FF_DELAY 1'b0 ;
else
begin
if (last_data_transferred || first_data_is_burst)
first_data_is_burst_reg <= #`FF_DELAY ~last_data_transferred ;
end
end
`ifdef REGISTER_WBM_OUTPUTS
assign burst_transfer = first_data_is_burst || first_data_is_burst_reg ;
assign burst_transfer = first_data_is_burst || first_data_is_burst_reg ;
`else
assign burst_transfer = (first_data_is_burst && ~last_data_transferred) || first_data_is_burst_reg ;
assign burst_transfer = (first_data_is_burst && ~last_data_transferred) || first_data_is_burst_reg ;
`endif
 
reg [(`WB_FSM_BITS - 1):0] c_state ; //current state register
605,432 → 567,413
 
// state machine logic
always@(c_state or
ACK_I or
RTY_I or
ERR_I or
w_attempt or
r_attempt or
retried or
rty_i_delayed or
pci_tar_read_request or
rty_counter_max_value or
last_data_to_pcir_fifo or
first_wb_data_access or
last_data_from_pciw_fifo_reg
)
ACK_I or
RTY_I or
ERR_I or
w_attempt or
r_attempt or
retried or
rty_i_delayed or
pci_tar_read_request or
rty_counter_almost_max_value or
set_retry or
last_data_to_pcir_fifo or
first_wb_data_access or
last_data_from_pciw_fifo_reg
)
begin
case (c_state)
S_IDLE:
begin
// Default values for signals not used in this state
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_count <= 1'b0 ;
read_count_enable <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
case ({w_attempt, r_attempt, retried})
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
begin // If there was retry, the same transaction must be initiated
pciw_fifo_renable <= 1'b0 ; // the same data
addr_into_cnt <= 1'b0 ; // the same address
read_count_load <= 1'b0 ; // no need for cache line when there is write
if (rty_counter_max_value) // If retry counter reached maximum value
begin
n_state <= S_WRITE_ERR_RTY ;
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
error_source_out <= rty_i_delayed;
pci_error_sig_out <= 1'b1 ;
end
else
begin
n_state <= S_WRITE ;
write_rty_cnt_exp_out <= 1'b0 ;
error_source_out <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
end
read_rty_cnt_exp_out <= 1'b0 ;
end
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
begin // If there is new transaction
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
read_count_load <= 1'b0 ; // no need for cache line when there is write
n_state <= S_WRITE ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
error_source_out <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
end
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
begin // If there was retry, the same transaction must be initiated
addr_into_cnt <= 1'b0 ; // the same address
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
if (rty_counter_max_value) // If retry counter reached maximum value
begin
n_state <= S_READ_RTY;
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
end
else
begin
n_state <= S_READ ;
read_rty_cnt_exp_out <= 1'b0 ;
end
write_rty_cnt_exp_out <= 1'b0 ;
error_source_out <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
end
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
begin // If there is new transaction
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
n_state <= S_READ ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
error_source_out <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
end
default : // stay in IDLE state
begin
pciw_fifo_renable <= 1'b0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
n_state <= S_IDLE ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
error_source_out <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
end
endcase
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
S_WRITE: // WRITE from PCIW_FIFO to WB bus
begin
// Default values for signals not used in this state
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
wb_read_done <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
case ({ACK_I, ERR_I, RTY_I})
3'b100 : // If writting of one data is acknowledged
begin
pciw_fifo_renable <= 1'b1 ; // prepare next value (address when new trans., data when burst tran.)
addr_count <= 1'b1 ; // prepare next address if there will be burst
pci_error_sig_out <= 1'b0 ; // there was no error
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ; // there was no retry
write_rty_cnt_exp_out <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
if (last_data_from_pciw_fifo_reg) // if last data was transfered
begin
n_state <= S_IDLE ;
last_data_transferred <= 1'b1 ; // signal for last data transfered
end
else
begin
n_state <= S_WRITE ;
last_data_transferred <= 1'b0 ;
end
end
3'b010 : // If writting of one data is terminated with ERROR
begin
pciw_fifo_renable <= 1'b1 ; // prepare next value (address when new trans., data when cleaning FIFO)
addr_count <= 1'b0 ; // no need for new address
retried_d <= 1'b0 ; // there was no retry
last_data_transferred <= 1'b1 ; // signal for last data transfered
pci_error_sig_out <= 1'b1 ; // segnal for error reporting
error_source_out <= 1'b0 ; // error source from other side of WB bus
write_rty_cnt_exp_out <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
if (last_data_from_pciw_fifo_reg) // if last data was transfered
n_state <= S_IDLE ; // go to S_IDLE for new transfere
else // if there wasn't last data of transfere
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
end
3'b001 : // If writting of one data is retried
begin
pciw_fifo_renable <= 1'b0 ;
addr_count <= 1'b0 ;
last_data_transferred <= 1'b0 ;
retried_d <= 1'b1 ; // there was a retry
wait_for_wb_response <= 1'b0 ;
if(rty_counter_max_value) // If retry counter reached maximum allowed value
begin
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
pci_error_sig_out <= 1'b1 ;
error_source_out <= 1'b1 ; // error ocuerd because of retry counter
end
else
begin
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
end
end
default :
begin
pciw_fifo_renable <= 1'b0 ;
addr_count <= 1'b0 ;
last_data_transferred <= 1'b0 ;
retried_d <= 1'b0 ;
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
error_source_out <= 1'b0 ; // if error ocures, error source is from other WB bus side
if(rty_counter_max_value) // when no WB response and RTY CNT reached maximum allowed value
begin
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
pci_error_sig_out <= 1'b1 ; // signal for error reporting
end
else
begin
n_state <= S_WRITE ; // stay in S_WRITE state to wait WB to response
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
pci_error_sig_out <= 1'b0 ;
end
end
endcase
wb_stb_o <= 1'b1 ;
wb_we_o <= 1'b1 ;
wb_cyc_o <= 1'b1 ;
end
S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures
begin
pciw_fifo_renable <= 1'b1 ; // put out next data (untill last data or FIFO empty)
last_data_transferred <= 1'b1 ; // after exiting this state, negedge of this signal is used
// Default values for signals not used in this state
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
// If last data is cleaned out from PCIW_FIFO
if (last_data_from_pciw_fifo_reg)
n_state <= S_IDLE ;
else
n_state <= S_WRITE_ERR_RTY ; // Clean until last data is cleaned out from FIFO
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
S_READ: // READ from WB bus to PCIR_FIFO
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
case ({ACK_I, ERR_I, RTY_I})
3'b100 : // If reading of one data is acknowledged
begin
pcir_fifo_wenable <= 1'b1 ; // enable writting data into PCIR_FIFO
addr_count <= 1'b1 ; // prepare next address if there will be burst
read_count_enable <= 1'b1 ; // decrease counter value for cache line size
retried_d <= 1'b0 ; // there was no retry
read_rty_cnt_exp_out <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
// if last data was transfered
if (last_data_to_pcir_fifo)
begin
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b1 ; // FIFO must indicate LAST data transfered
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
last_data_transferred <= 1'b1 ; // signal for last data transfered
wb_read_done <= 1'b1 ; // signal last data of read transaction for PCI Target
n_state <= S_TURN_ARROUND ;
end
else // if not last data transfered
begin
pcir_fifo_control <= 4'h0 ; // ZERO for control code
last_data_transferred <= 1'b0 ; // not last data transfered
wb_read_done <= 1'b0 ; // read is not done yet
n_state <= S_READ ;
end
end
3'b010 : // If reading of one data is terminated with ERROR
begin
pcir_fifo_wenable <= 1'b1 ; // enable for writting to FIFO data with ERROR
addr_count <= 1'b0 ; // no need for new address
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
last_data_transferred <= 1'b1 ; // signal for last data transfered
wb_read_done <= 1'b1 ; // signal last data of read transaction for PCI Target
read_count_enable <= 1'b0 ; // no need for cache line, when error occures
n_state <= S_TURN_ARROUND ;
retried_d <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ; // there was no retry
end
3'b001 : // If reading of one data is retried
begin
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_count <= 1'b0 ;
read_count_enable <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
case ({first_wb_data_access, rty_counter_max_value})
2'b10 :
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
retried_d <= 1'b1 ; // there was a retry
end
2'b11 :
begin // if retry counter reached maximum value
n_state <= S_READ_RTY ; // go here to wait for PCI Target to remove read request
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
retried_d <= 1'b1 ; // there was a retry
end
default : // if retry occures after at least 1 data was transferred without breaking cycle (CYC_O inactive)
begin // then PCI device will retry access!
n_state <= S_TURN_ARROUND ; // go to S_TURN_ARROUND state
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired
last_data_transferred <= 1'b1 ;
wb_read_done <= 1'b1 ;
retried_d <= 1'b0 ; // retry must not be retried, since there is not a first data
end
endcase
end
default :
begin
addr_count <= 1'b0 ;
read_count_enable <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
retried_d <= 1'b0 ;
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
if(rty_counter_max_value) // when no WB response and RTY CNT reached maximum allowed value
begin
n_state <= S_TURN_ARROUND ; // go here to stop read request
pcir_fifo_wenable <= 1'b1 ;
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
last_data_transferred <= 1'b1 ;
wb_read_done <= 1'b1 ;
end
else
begin
n_state <= S_READ ; // stay in S_READ state to wait WB to response
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
end
end
endcase
wb_stb_o <= 1'b1 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b1 ;
end
S_READ_RTY: // Wait for PCI Target to remove read request, when retry counter reaches maximum value!
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
// wait for PCI Target to remove read request
if (pci_tar_read_request)
begin
n_state <= S_READ_RTY ; // stay in this state until read request is removed
last_data_transferred <= 1'b0 ;
end
else // when read request is removed
begin
n_state <= S_IDLE ;
last_data_transferred <= 1'b1 ; // when read request is removed, there is "last" data
end
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
S_TURN_ARROUND: // Turn arround cycle after writting to PCIR_FIFO (for correct data when reading from PCIW_FIFO)
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
last_data_transferred <= 1'b1 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
n_state <= S_IDLE ;
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
default :
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
n_state <= S_IDLE ;
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
endcase
// Default values for signals not used in this state
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_count <= 1'b0 ;
read_count_enable <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
error_source_out <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
case ({w_attempt, r_attempt, retried})
3'b101 : // Write request for PCIW_FIFO to WB bus transaction
begin // If there was retry, the same transaction must be initiated
pciw_fifo_renable <= 1'b0 ; // the same data
addr_into_cnt <= 1'b0 ; // the same address
read_count_load <= 1'b0 ; // no need for cache line when there is write
n_state <= S_WRITE ;
end
3'b100 : // Write request for PCIW_FIFO to WB bus transaction
begin // If there is new transaction
pciw_fifo_renable <= 1'b1 ; // first location is address (in FIFO), next will be data
addr_into_cnt <= 1'b1 ; // address must be latched into address counter
read_count_load <= 1'b0 ; // no need for cache line when there is write
n_state <= S_WRITE ;
end
3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
begin // If there was retry, the same transaction must be initiated
addr_into_cnt <= 1'b0 ; // the same address
read_count_load <= 1'b0 ; // cache line counter must not be changed for retried read
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
n_state <= S_READ ;
end
3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction
begin // If there is new transaction
addr_into_cnt <= 1'b1 ; // address must be latched into counter from separate request bus
read_count_load <= 1'b1 ; // cache line size must be latched into its counter
pciw_fifo_renable <= 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO
n_state <= S_READ ;
end
default : // stay in IDLE state
begin
pciw_fifo_renable <= 1'b0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
n_state <= S_IDLE ;
end
endcase
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
S_WRITE: // WRITE from PCIW_FIFO to WB bus
begin
// Default values for signals not used in this state
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
wb_read_done <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
case ({ACK_I, ERR_I, RTY_I})
3'b100 : // If writting of one data is acknowledged
begin
pciw_fifo_renable <= 1'b1 ; // prepare next value (address when new trans., data when burst tran.)
addr_count <= 1'b1 ; // prepare next address if there will be burst
pci_error_sig_out <= 1'b0 ; // there was no error
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ; // there was no retry
write_rty_cnt_exp_out <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
if (last_data_from_pciw_fifo_reg) // if last data was transfered
begin
n_state <= S_IDLE ;
last_data_transferred <= 1'b1 ; // signal for last data transfered
end
else
begin
n_state <= S_WRITE ;
last_data_transferred <= 1'b0 ;
end
end
3'b010 : // If writting of one data is terminated with ERROR
begin
pciw_fifo_renable <= 1'b1 ; // prepare next value (address when new trans., data when cleaning FIFO)
addr_count <= 1'b0 ; // no need for new address
retried_d <= 1'b0 ; // there was no retry
last_data_transferred <= 1'b1 ; // signal for last data transfered
pci_error_sig_out <= 1'b1 ; // segnal for error reporting
error_source_out <= 1'b0 ; // error source from other side of WB bus
write_rty_cnt_exp_out <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
if (last_data_from_pciw_fifo_reg) // if last data was transfered
n_state <= S_IDLE ; // go to S_IDLE for new transfere
else // if there wasn't last data of transfere
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
end
3'b001 : // If writting of one data is retried
begin
addr_count <= 1'b0 ;
last_data_transferred <= 1'b0 ;
retried_d <= 1'b1 ; // there was a retry
wait_for_wb_response <= 1'b0 ;
if(rty_counter_almost_max_value) // If retry counter reached maximum allowed value
begin
if (last_data_from_pciw_fifo_reg) // if last data was transfered
pciw_fifo_renable <= 1'b0 ;
else // if there wasn't last data of transfere
pciw_fifo_renable <= 1'b1 ;
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
pci_error_sig_out <= 1'b1 ;
error_source_out <= 1'b1 ; // error ocuerd because of retry counter
end
else
begin
pciw_fifo_renable <= 1'b0 ;
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
end
end
default :
begin
addr_count <= 1'b0 ;
last_data_transferred <= 1'b0 ;
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
error_source_out <= 1'b0 ; // if error ocures, error source is from other WB bus side
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
begin
retried_d <= 1'b1 ;
if (last_data_from_pciw_fifo_reg) // if last data was transfered
pciw_fifo_renable <= 1'b0 ;
else // if there wasn't last data of transfere
pciw_fifo_renable <= 1'b1 ;
n_state <= S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO
write_rty_cnt_exp_out <= 1'b1 ; // signal for reporting write counter expired
pci_error_sig_out <= 1'b1 ; // signal for error reporting
end
else
begin
pciw_fifo_renable <= 1'b0 ;
retried_d <= 1'b0 ;
n_state <= S_WRITE ; // stay in S_WRITE state to wait WB to response
write_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
pci_error_sig_out <= 1'b0 ;
end
end
endcase
wb_stb_o <= 1'b1 ;
wb_we_o <= 1'b1 ;
wb_cyc_o <= 1'b1 ;
end
S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures
begin
`ifdef REGISTER_WBM_OUTPUTS
pciw_fifo_renable <= !last_data_from_pciw_fifo_reg ; // put out next data (untill last data or FIFO empty)
`else
pciw_fifo_renable <= 1'b1 ; // put out next data (untill last data or FIFO empty)
`endif
last_data_transferred <= 1'b1 ; // after exiting this state, negedge of this signal is used
// Default values for signals not used in this state
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
// If last data is cleaned out from PCIW_FIFO
if (last_data_from_pciw_fifo_reg)
n_state <= S_IDLE ;
else
n_state <= S_WRITE_ERR_RTY ; // Clean until last data is cleaned out from FIFO
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
S_READ: // READ from WB bus to PCIR_FIFO
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
case ({ACK_I, ERR_I, RTY_I})
3'b100 : // If reading of one data is acknowledged
begin
pcir_fifo_wenable <= 1'b1 ; // enable writting data into PCIR_FIFO
addr_count <= 1'b1 ; // prepare next address if there will be burst
read_count_enable <= 1'b1 ; // decrease counter value for cache line size
retried_d <= 1'b0 ; // there was no retry
read_rty_cnt_exp_out <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
// if last data was transfered
if (last_data_to_pcir_fifo)
begin
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b1 ; // FIFO must indicate LAST data transfered
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
last_data_transferred <= 1'b1 ; // signal for last data transfered
wb_read_done <= 1'b1 ; // signal last data of read transaction for PCI Target
n_state <= S_TURN_ARROUND ;
end
else // if not last data transfered
begin
pcir_fifo_control <= 4'h0 ; // ZERO for control code
last_data_transferred <= 1'b0 ; // not last data transfered
wb_read_done <= 1'b0 ; // read is not done yet
n_state <= S_READ ;
end
end
3'b010 : // If reading of one data is terminated with ERROR
begin
pcir_fifo_wenable <= 1'b1 ; // enable for writting to FIFO data with ERROR
addr_count <= 1'b0 ; // no need for new address
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
last_data_transferred <= 1'b1 ; // signal for last data transfered
wb_read_done <= 1'b1 ; // signal last data of read transaction for PCI Target
read_count_enable <= 1'b0 ; // no need for cache line, when error occures
n_state <= S_TURN_ARROUND ;
retried_d <= 1'b0 ; // there was no retry
wait_for_wb_response <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ; // there was no retry
end
3'b001 : // If reading of one data is retried
begin
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_count <= 1'b0 ;
read_count_enable <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
case ({first_wb_data_access, rty_counter_almost_max_value})
2'b10 :
begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive
n_state <= S_IDLE ; // go to S_IDLE state for retrying the transaction
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired yet
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
retried_d <= 1'b1 ; // there was a retry
end
2'b11 :
begin // if retry counter reached maximum value
n_state <= S_READ_RTY ; // go here to wait for PCI Target to remove read request
read_rty_cnt_exp_out <= 1'b1 ; // signal for reporting read counter expired
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
retried_d <= 1'b1 ; // there was a retry
end
default : // if retry occures after at least 1 data was transferred without breaking cycle (CYC_O inactive)
begin // then PCI device will retry access!
n_state <= S_TURN_ARROUND ; // go to S_TURN_ARROUND state
read_rty_cnt_exp_out <= 1'b0 ; // retry counter hasn't expired
last_data_transferred <= 1'b1 ;
wb_read_done <= 1'b1 ;
retried_d <= 1'b0 ; // retry must not be retried, since there is not a first data
end
endcase
end
default :
begin
addr_count <= 1'b0 ;
read_count_enable <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented)
if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value
begin
retried_d <= 1'b1 ;
n_state <= S_TURN_ARROUND ; // go here to stop read request
pcir_fifo_wenable <= 1'b1 ;
pcir_fifo_control[`LAST_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`DATA_ERROR_CTRL_BIT] <= 1'b1 ; // FIFO must indicate the DATA with ERROR
pcir_fifo_control[`UNUSED_CTRL_BIT] <= 1'b0 ;
pcir_fifo_control[`ADDR_CTRL_BIT] <= 1'b0 ;
last_data_transferred <= 1'b1 ;
wb_read_done <= 1'b1 ;
end
else
begin
retried_d <= 1'b0 ;
n_state <= S_READ ; // stay in S_READ state to wait WB to response
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
end
end
endcase
wb_stb_o <= 1'b1 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b1 ;
end
S_READ_RTY: // Wait for PCI Target to remove read request, when retry counter reaches maximum value!
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
// wait for PCI Target to remove read request
if (pci_tar_read_request)
begin
n_state <= S_READ_RTY ; // stay in this state until read request is removed
last_data_transferred <= 1'b0 ;
end
else // when read request is removed
begin
n_state <= S_IDLE ;
last_data_transferred <= 1'b1 ; // when read request is removed, there is "last" data
end
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
S_TURN_ARROUND: // Turn arround cycle after writting to PCIR_FIFO (for correct data when reading from PCIW_FIFO)
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
last_data_transferred <= 1'b1 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
n_state <= S_IDLE ;
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
default :
begin
// Default values for signals not used in this state
pciw_fifo_renable <= 1'b0 ;
pcir_fifo_wenable <= 1'b0 ;
pcir_fifo_control <= 4'h0 ;
addr_into_cnt <= 1'b0 ;
read_count_load <= 1'b0 ;
read_count_enable <= 1'b0 ;
addr_count <= 1'b0 ;
pci_error_sig_out <= 1'b0 ;
error_source_out <= 1'b0 ;
retried_d <= 1'b0 ;
last_data_transferred <= 1'b0 ;
wb_read_done <= 1'b0 ;
write_rty_cnt_exp_out <= 1'b0 ;
read_rty_cnt_exp_out <= 1'b0 ;
wait_for_wb_response <= 1'b0 ;
n_state <= S_IDLE ;
wb_stb_o <= 1'b0 ;
wb_we_o <= 1'b0 ;
wb_cyc_o <= 1'b0 ;
end
endcase
end
 
// Signal for retry monitor in state machine when there is read and first (or single) data access
1039,108 → 982,123
// Signal first_wb_data_access is set when no WB cycle present till end of first data access of WB cycle on WB bus
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
first_wb_data_access = 1'b1 ;
else
begin
if (~wb_cyc_o)
first_wb_data_access = 1'b1 ;
else if (ack_rty_response)
first_wb_data_access = 1'b0 ;
end
if (reset_in)
first_wb_data_access = 1'b1 ;
else
begin
if (~wb_cyc_o)
first_wb_data_access = 1'b1 ;
else if (ack_rty_response)
first_wb_data_access = 1'b0 ;
end
end
 
reg [3:0] wb_sel_o;
reg [3:0] wb_sel_o;
always@(pciw_fifo_cbe_in or pci_tar_be or wb_we_o or burst_transfer or pci_tar_read_request)
begin
case ({wb_we_o, burst_transfer, pci_tar_read_request})
3'b100,
3'b101,
3'b110,
3'b111:
wb_sel_o = ~pciw_fifo_cbe_in ;
3'b011:
wb_sel_o = 4'hf ;
default:
wb_sel_o = ~pci_tar_be ;
endcase
case ({wb_we_o, burst_transfer, pci_tar_read_request})
3'b100,
3'b101,
3'b110,
3'b111:
wb_sel_o = ~pciw_fifo_cbe_in ;
3'b011:
wb_sel_o = 4'hf ;
default:
wb_sel_o = ~pci_tar_be ;
endcase
end
 
// Signals to FIFO
assign pcir_fifo_be_out = 4'hf ; // pci_tar_be ;
assign pcir_fifo_be_out = 4'hf ; // pci_tar_be ;
 
// OUTPUT signals
assign pci_error_bc = bc_register ;
assign pci_error_bc = bc_register ;
 
assign ADR_O = addr_cnt_out ;
assign ADR_O = addr_cnt_out ;
 
`ifdef REGISTER_WBM_OUTPUTS
 
reg wb_cyc_reg ;
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
begin
CYC_O <= 1'h0 ;
STB_O <= 1'h0 ;
WE_O <= 1'h0 ;
CAB_O <= 1'h0 ;
MDATA_O <= 32'h0 ;
SEL_O <= 4'h0 ;
wb_cyc_reg <= 1'h0 ;
wb_read_done_out <= 1'b0 ;
pcir_fifo_data_out <= 32'h0 ;
pcir_fifo_wenable_out <= 1'b0 ;
pcir_fifo_control_out <= 1'b0 ;
end
else
begin
if (wb_cyc_o)
begin
CYC_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) ;
CAB_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
STB_O <= ~((ACK_I || RTY_I || ERR_I) && (last_data_transferred || retried_d)) ;
end
WE_O <= wb_we_o ;
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
MDATA_O <= pciw_fifo_addr_data_in ;
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
SEL_O <= wb_sel_o ;
wb_cyc_reg <= wb_cyc_o ;
wb_read_done_out <= wb_read_done ;
pcir_fifo_data_out <= MDATA_I ;
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
pcir_fifo_control_out <= pcir_fifo_control ;
end
end
always@(pciw_fifo_renable or last_data_from_pciw_fifo_reg or wb_cyc_o or wb_cyc_reg or wb_we_o or retried_write or
pciw_fifo_control_in or pciw_fifo_empty_in)
begin
pciw_fifo_renable_out <= (pciw_fifo_renable && ~wb_cyc_o) ||
(pciw_fifo_renable && ~last_data_from_pciw_fifo_reg) ||
(wb_cyc_o && ~wb_cyc_reg && wb_we_o && !retried_write) ;
last_data_from_pciw_fifo_reg <= pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
end
reg no_sel_o_change_due_rty;
reg wb_cyc_reg ;
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
begin
no_sel_o_change_due_rty <= 1'b0;
CYC_O <= 1'h0 ;
STB_O <= 1'h0 ;
WE_O <= 1'h0 ;
CAB_O <= 1'h0 ;
MDATA_O <= 32'h0 ;
SEL_O <= 4'h0 ;
wb_cyc_reg <= 1'h0 ;
wb_read_done_out <= 1'b0 ;
pcir_fifo_data_out <= 32'h0 ;
pcir_fifo_wenable_out <= 1'b0 ;
pcir_fifo_control_out <= 1'b0 ;
end
else
begin
if (w_attempt)
if (ACK_I || ERR_I || last_data_transferred)
no_sel_o_change_due_rty <= 1'b0;
else if (retry)
no_sel_o_change_due_rty <= 1'b1;
if (wb_cyc_o)
begin // retry = RTY_I || set_retry
CYC_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
CAB_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) && burst_transfer ;
STB_O <= ~((ACK_I || retry || ERR_I) && (last_data_transferred || retried_d)) ;
end
WE_O <= wb_we_o ;
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
MDATA_O <= pciw_fifo_addr_data_in ;
if (w_attempt)
begin
if (((wb_cyc_o && ~wb_cyc_reg && !retried_write) || ACK_I) && wb_we_o)
SEL_O <= ~pciw_fifo_cbe_in ;
end
else
begin
if ((wb_cyc_o && ~wb_cyc_reg) || ACK_I)
SEL_O <= wb_sel_o ;
end
wb_cyc_reg <= wb_cyc_o ;
wb_read_done_out <= wb_read_done ;
pcir_fifo_data_out <= MDATA_I ;
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
pcir_fifo_control_out <= pcir_fifo_control ;
end
end
always@(pciw_fifo_renable or last_data_from_pciw_fifo_reg or wb_cyc_o or wb_cyc_reg or wb_we_o or retried_write or
pciw_fifo_control_in or pciw_fifo_empty_in)
begin
pciw_fifo_renable_out <= (pciw_fifo_renable && ~wb_cyc_o) ||
(pciw_fifo_renable && ~last_data_from_pciw_fifo_reg) ||
(wb_cyc_o && ~wb_cyc_reg && wb_we_o && !retried_write) ;
last_data_from_pciw_fifo_reg <= pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
end
`else
always@(wb_cyc_o or wb_stb_o or wb_we_o or burst_transfer or pciw_fifo_addr_data_in or wb_sel_o or
wb_read_done or MDATA_I or pcir_fifo_wenable or pcir_fifo_control)
begin
CYC_O <= wb_cyc_o ;
STB_O <= wb_stb_o ;
WE_O <= wb_we_o ;
CAB_O <= wb_cyc_o & burst_transfer ;
MDATA_O <= pciw_fifo_addr_data_in ;
SEL_O <= wb_sel_o ;
wb_read_done_out <= wb_read_done ;
pcir_fifo_data_out <= MDATA_I ;
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
pcir_fifo_control_out <= pcir_fifo_control ;
end
always@(pciw_fifo_renable or last_data_from_pciw_fifo)
begin
pciw_fifo_renable_out <= pciw_fifo_renable ;
last_data_from_pciw_fifo_reg <= last_data_from_pciw_fifo ;
end
always@(wb_cyc_o or wb_stb_o or wb_we_o or burst_transfer or pciw_fifo_addr_data_in or wb_sel_o or
wb_read_done or MDATA_I or pcir_fifo_wenable or pcir_fifo_control)
begin
CYC_O <= wb_cyc_o ;
STB_O <= wb_stb_o ;
WE_O <= wb_we_o ;
CAB_O <= wb_cyc_o & burst_transfer ;
MDATA_O <= pciw_fifo_addr_data_in ;
SEL_O <= wb_sel_o ;
wb_read_done_out <= wb_read_done ;
pcir_fifo_data_out <= MDATA_I ;
pcir_fifo_wenable_out <= pcir_fifo_wenable ;
pcir_fifo_control_out <= pcir_fifo_control ;
end
always@(pciw_fifo_renable or last_data_from_pciw_fifo)
begin
pciw_fifo_renable_out <= pciw_fifo_renable ;
last_data_from_pciw_fifo_reg <= last_data_from_pciw_fifo ;
end
`endif
 
 
/trunk/rtl/verilog/delayed_sync.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:28 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
394,7 → 397,7
 
synchronizer_flop rty_exp_back_prop_sync
(
.data_in (req_rty_exp_reg),
.data_in (req_rty_exp_reg && req_rty_exp_clr),
.clk_out (comp_clk_in),
.sync_data_out (sync_comp_rty_exp_clr),
.async_reset (reset_in)
/trunk/rtl/verilog/pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/02/01 15:25:13 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:30 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
85,7 → 88,6
pcir_be_out,
pcir_control_out,
pcir_flush_in,
pcir_almost_full_out,
pcir_full_out,
pcir_almost_empty_out,
pcir_empty_out,
174,7 → 176,6
 
status signals - monitored by various resources in the core
pcir_flush_in = flush signal input for PCIR_FIFO - when asserted, fifo is flushed(emptied)
pcir_almost_full_out = almost full output from PCIR_FIFO
pcir full_out = full output from PCIR_FIFO
pcir_almost_empty_out = almost empty output from PCIR_FIFO
pcir_empty_out = empty output from PCIR_FIFO
196,7 → 197,6
input pcir_flush_in ;
 
// status outputs
output pcir_almost_full_out ;
output pcir_full_out ;
output pcir_almost_empty_out ;
output pcir_empty_out ;
457,7 → 457,6
.wenable_in(pcir_wenable_in),
.reset_in(reset_in),
.flush_in(pcir_flush_in),
.almost_full_out(pcir_almost_full_out),
.full_out(pcir_full_out),
.almost_empty_out(pcir_almost_empty_out),
.empty_out(pcir_empty),
/trunk/rtl/verilog/pci_user_constants.v
39,7 → 39,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/01 14:43:31 mihad
// *** empty log message ***
//
//
 
// Fifo implementation defines:
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
54,11 → 57,11
 
`define WBW_ADDR_LENGTH 6
`define WBR_ADDR_LENGTH 4
`define PCIW_ADDR_LENGTH 6
`define PCIW_ADDR_LENGTH 3
`define PCIR_ADDR_LENGTH 3
 
`define FPGA
`define XILINX
//`define FPGA
//`define XILINX
 
//`define WB_RAM_DONT_SHARE
//`define PCI_RAM_DONT_SHARE
73,10 → 76,10
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`define WB_ARTISAN_SDP
`define PCI_ARTISAN_SDP
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
// `define WB_ARTISAN_SDP
// `define PCI_ARTISAN_SDP
`endif
 
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
179,7 → 182,7
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
`define REGISTER_WBS_OUTPUTS
//`define REGISTER_WBS_OUTPUTS
 
/*-----------------------------------------------------------------------------------------------------------
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
201,7 → 204,7
// Turn registered WISHBONE master outputs on or off
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBM_OUTPUTS
`define REGISTER_WBM_OUTPUTS
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
/trunk/rtl/verilog/pci_target_unit.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/02/19 16:32:37 mihad
// Modified testbench and fixed some bugs
//
// Revision 1.3 2002/02/01 15:25:13 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
517,7 → 520,6
.pcir_be_out (fifos_pcir_be_out), //for PCI Target !!!
.pcir_control_out (fifos_pcir_control_out), //for PCI Target !!!
.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
.pcir_almost_full_out (),
.pcir_full_out (),
.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
854,4 → 856,4
.wbu_frame_en_in (pcit_sm_wbu_frame_en_in)
) ;
 
endmodule
endmodule

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