URL
https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
Subversion Repositories tinycpu
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- This comparison shows the changes necessary to convert path
/
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/tinycpu/trunk/testbench/core_tb.vhd
166,9 → 166,12
wait for 10 ns; |
assert(MemAddr=x"0200" and MemOut=x"0070") report "push is not correct" severity error; |
wait for 10 ns; |
MemIn <= "0101000001100001"; --mov r0, SP |
wait for 10 ns; |
assert(Debugr0 = x"02") report "SP is not correct" severity error; |
|
MemIn <= "0101000000010000"; --pop r0 |
assert(MemAddr=x"015A") report "IP increment is wrong after push" severity error; |
assert(MemAddr=x"015C") report "IP increment is wrong after push" severity error; |
wait for 10 ns; |
MemIn <= x"0020"; --the value to be popped into r0 |
assert(MemAddr=x"0200") report "Pop is not fetching from correct address" severity error; |
/tinycpu/trunk/src/core.vhd
291,7 → 291,12
state <= Execute; |
FetchEn <= '1'; |
IpAddend <= x"02"; |
SpAddend <= x"00"; |
--SpAddend <= x"00"; |
--SP can change here... really I don't *think* it can change from within Execute... so maybe that's redundant |
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me |
regIn(REGSS) <= SSCarryOut; |
regWE(REGSP) <= '1'; |
regWE(REGSS) <= '1'; |
if OpWE='0' then |
regIn(to_integer(unsigned(OpDestReg1))) <= OpDataIn(7 downto 0); |
regWE(to_integer(unsigned(OpDestReg1))) <= '1'; |
320,10 → 325,6
regWE(REGIP) <= '1'; |
regWE(REGCS) <= '1'; |
regIn(REGCS) <= CSCarryOut; |
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me |
regIn(REGSS) <= SSCarryOut; |
regWE(REGSP) <= '1'; |
regWE(REGSS) <= '1'; |
OpUseReg2 <= '0'; |
OpAddress <= "ZZZZZZZZZZZZZZZZ"; |
if UseAluTR='1' then |
375,7 → 376,8
FetchEN <= '0'; |
when "001" => --pop reg |
SPAddend <= x"FE"; --set SP to decrement |
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP); |
--TODO account for carryover properties |
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & std_logic_vector(unsigned(regOut(REGSP))-2); --decrement 2 here "early" |
OpWE <= '0'; |
OpDestReg1 <= bankreg1; |
--regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0); |
388,6 → 390,9
report "Not implemented subgroup 5-0" severity error; |
--synthesis on |
end case; |
when "001" => --mov reg, reg |
regIn(to_integer(unsigned(bankreg1))) <= regOut(to_integer(unsigned(bankreg2))); |
regWE(to_integer(unsigned(bankreg1))) <= '1'; |
when others => |
--synthesis off |
report "Not implemented group 5" severity error; |
/tinycpu/trunk/docs/design.md.txt
340,5 → 340,7
000: push reg |
001: pop reg |
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001: mov reg, reg |
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