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Rev 327 → Rev 328

/trunk/or1200/rtl/verilog/sprs.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:10 lampret
// MP3 version.
//
71,7 → 74,7
clk, rst,
 
// Internal CPU interface
flag, addrbase, addrofs, dat_i, alu_op, branch_op,
flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
epcr, eear, esr, except_start, except_started,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
spr_dat_cfgr, spr_dat_rf, spr_dat_pc,
97,7 → 100,9
//
input clk; // Clock
input rst; // Reset
input flag; // From ALU
output flag; // SR[F]
input flagforw; // From ALU
input flag_we; // From ALU
input [width-1:0] addrbase; // SPR base address
input [15:0] addrofs; // SPR offset
input [width-1:0] dat_i; // SPR write data
273,6 → 278,11
({{32-`SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
 
//
// Flag alias
//
assign flag = sr[`SR_F];
 
//
// Supervision register
//
always @(posedge clk or posedge rst)
296,6 → 306,14
`endif
sr <= #1 to_sr;
end
else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: setting SR[F] bit: %b", flagforw);
// synopsys translate_on
`endif
sr[`SR_F] <= #1 flagforw;
end
 
//
// MTSPR/MFSPR interface
/trunk/or1200/rtl/verilog/id.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
72,7 → 75,7
 
// Internal i/f
id_freeze, ex_freeze, wb_freeze, except_flushpipe, if_insn, branch_op,
rf_addra, rf_addrb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, shrot_op, comp_op, rf_addrw, rfwb_op,
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
force_dslot_fetch, id_macrc_op, ex_macrc_op
92,6 → 95,8
output [`REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output [`REGFILE_ADDR_WIDTH-1:0] rf_addra;
output [`REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output rf_rda;
output rf_rdb;
output [`ALUOP_WIDTH-1:0] alu_op;
output [`SHROTOP_WIDTH-1:0] shrot_op;
output [`RFWBOP_WIDTH-1:0] rfwb_op;
143,6 → 148,8
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
assign rf_rda = if_insn[31];
assign rf_rdb = if_insn[30];
 
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
/trunk/or1200/rtl/verilog/operandmuxes.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
68,7 → 71,7
clk, rst,
 
// Internal i/f
ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);
 
79,6 → 82,7
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
98,15 → 102,23
reg [width-1:0] operand_b;
reg [width-1:0] muxed_a;
reg [width-1:0] muxed_b;
reg saved_a;
reg saved_b;
 
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
if (rst)
if (rst) begin
operand_a <= #1 32'd0;
else if (!ex_freeze)
saved_a <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
saved_a <= #1 1'b1;
end else if (!ex_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
end else if (!ex_freeze && !id_freeze)
saved_a <= #1 1'b0;
end
 
//
113,10 → 125,16
// Operand B register
//
always @(posedge clk or posedge rst) begin
if (rst)
if (rst) begin
operand_b <= #1 32'd0;
else if (!ex_freeze)
saved_b <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
saved_b <= #1 1'b1;
end else if (!ex_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
end else if (!ex_freeze && !id_freeze)
saved_b <= #1 1'b0;
end
 
//
/trunk/or1200/rtl/verilog/defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.11 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
88,7 → 91,7
`define VCD_DUMP
 
// Verbose
//`define OR1200_VERBOSE
`define OR1200_VERBOSE
 
//
// Data cache not implemented
277,7 → 280,7
`define EXCEPT_RESET `EXCEPT_WIDTH'h1
`define EXCEPT_NONE `EXCEPT_WIDTH'h0
 
`define SR_WIDTH 9
`define SR_WIDTH 10
// SR bits (no CID)
`define SR_SUPV 0
`define SR_EXR 1
287,7 → 290,8
`define SR_DME 5
`define SR_IME 6
`define SR_LEE 7
`define SR_CF 8
`define SR_CE 8
`define SR_F 9
 
// Access types
`define ACCESS_WIDTH 2
/trunk/or1200/rtl/verilog/alu.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:45 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
66,7 → 69,7
// synopsys translate_on
`include "defines.v"
 
module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flag);
module alu(clk, rst, a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flagforw, flag_we);
 
parameter width = `OPERAND_WIDTH;
 
83,7 → 86,8
input [`SHROTOP_WIDTH-1:0] shrot_op;
input [`COMPOP_WIDTH-1:0] comp_op;
output [width-1:0] result;
output flag;
output flagforw;
output flag_we;
 
//
// Internal wires and regs
92,7 → 96,6
reg [width-1:0] shifted_rotated;
reg flagforw;
reg flag_we;
reg flag;
integer d1;
integer d2;
wire [width-1:0] comp_a;
272,20 → 275,4
end
`endif
 
//
// Flag bit
//
always @(posedge clk or posedge rst) begin
if (rst)
flag <= #1 1'b0;
else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("COMPARE: comp_a:%h comp_b:%h a_eq_b=%b a_lt_b=%b", comp_a, comp_b, a_eq_b, a_lt_b);
// synopsys translate_on
`endif
flag <= #1 flagforw;
end
end
 
endmodule
/trunk/or1200/rtl/verilog/cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
186,6 → 189,8
wire [aw-1:0] rf_addrw;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrb;
wire rf_rda;
wire rf_rdb;
wire [dw-1:0] simm;
wire [dw-1:2] branch_addrofs;
wire [`ALUOP_WIDTH-1:0] alu_op;
217,6 → 222,8
wire except_flushpipe;
wire branch_taken;
wire flag;
wire flagforw;
wire flag_we;
wire lsu_stall;
wire branch_stall;
wire epcr_we;
363,6 → 370,8
.branch_op(branch_op),
.rf_addra(rf_addra),
.rf_addrb(rf_addrb),
.rf_rda(rf_rda),
.rf_rdb(rf_rdb),
.alu_op(alu_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
414,8 → 423,10
.we(rfwb_op[0]),
.except_flushpipe(except_flushpipe),
.addra(rf_addra),
.rda(rf_rda),
.dataa(rf_dataa),
.addrb(rf_addrb),
.rdb(rf_rdb),
.datab(rf_datab),
.spr_cs(spr_cs[`SPR_GROUP_SYS]),
.spr_write(spr_we),
430,6 → 441,7
operandmuxes operandmuxes(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.rf_dataa(rf_dataa),
.rf_datab(rf_datab),
457,7 → 469,8
.shrot_op(shrot_op),
.comp_op(comp_op),
.result(alu_dataout),
.flag(flag)
.flagforw(flagforw),
.flag_we(flag_we)
);
 
//
485,6 → 498,8
.addrofs(spr_addrimm),
.dat_i(operand_b),
.alu_op(alu_op),
.flagforw(flagforw),
.flag_we(flag_we),
.flag(flag),
.to_wbmux(sprs_dataout),
 
/trunk/or1200/rtl/verilog/rf.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
77,7 → 80,7
addrw, dataw, we, except_flushpipe,
 
// Read i/f
id_freeze, addra, addrb, dataa, datab,
id_freeze, addra, addrb, dataa, datab, rda, rdb,
 
// Debug
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
112,6 → 115,8
input [aw-1:0] addrb;
output [dw-1:0] dataa;
output [dw-1:0] datab;
input rda;
input rdb;
 
//
// SPR access for debugging purposes
134,6 → 139,8
wire [dw-1:0] rf_dataw;
wire rf_we;
wire spr_valid;
wire rf_ena;
wire rf_enb;
 
//
// SPR access is valid when spr_cs is asserted and
177,6 → 184,18
assign rf_we = ((spr_valid & spr_write) | we) & ~except_flushpipe;
 
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = rda & ~id_freeze;
 
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze;
 
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
209,7 → 228,7
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
.ce_a(rf_ena),
// .we_a(1'b0),
.oe_a(1'b1),
.addr_a(rf_addra),
234,7 → 253,7
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(1'b1),
.ce_a(rf_enb),
// .we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),

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