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Rev 327 → Rev 328
/phr/trunk/codigo/cpld/test1/tb.vhd
0,0 → 1,103
-------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 23:47:36 06/04/2014 |
-- Design Name: |
-- Module Name: /home/luis/opencores/phr/trunk/codigo/cpld/test1/tb.vhd |
-- Project Name: test1 |
-- Target Device: |
-- Tool versions: |
-- Description: |
-- |
-- VHDL Test Bench Created by ISE for module: test1 |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY tb IS |
END tb; |
|
ARCHITECTURE behavior OF tb IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT test1 |
PORT( |
clock : IN std_logic; |
sw : IN std_logic_vector(7 downto 0); |
btn : IN std_logic_vector(4 downto 0); |
seg : OUT std_logic_vector(7 downto 0); |
an : OUT std_logic_vector(3 downto 0); |
led : OUT std_logic_vector(7 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal clock : std_logic := '0'; |
signal sw : std_logic_vector(7 downto 0) := (others => '0'); |
signal btn : std_logic_vector(4 downto 0) := (others => '0'); |
|
--Outputs |
signal seg : std_logic_vector(7 downto 0); |
signal an : std_logic_vector(3 downto 0); |
signal led : std_logic_vector(7 downto 0); |
|
-- Clock period definitions |
constant clock_period : time := 1370 us; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: test1 PORT MAP ( |
clock => clock, |
sw => sw, |
btn => btn, |
seg => seg, |
an => an, |
led => led |
); |
|
-- Clock process definitions |
clock_process :process |
begin |
clock <= '0'; |
wait for clock_period/2; |
clock <= '1'; |
wait for clock_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
-- hold reset state for 100 ns. |
wait for 10 ms; |
|
btn(0) <= '1'; |
wait for 1 ms; |
btn(0) <= '0'; |
|
-- insert stimulus here |
wait; |
end process; |
|
END; |