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    from Rev 33 to Rev 34
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Rev 33 → Rev 34

/trunk/generic_memories/rtl/verilog/generic_dpram.v
66,6 → 66,13
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
// Memories are now compatible, i.e. drop-in replacements.
// Added synthesizeable generic FPGA description.
// Created "generic_memories" cvs entry.
//
// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
// *** empty log message ***
//
82,7 → 89,7
 
`include "timescale.v"
 
`define VENDOR_FPGA
//`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
 
301,12 → 308,12
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
assign do = (oe & rce) ? do_reg : {dw{1'bz}};
 
// read operation
always @(posedge rclk)
if (rce)
do_reg <= #1 mem[raddr];
do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
 
// write operation
always @(posedge wclk)
313,6 → 320,19
if (wce && we)
mem[waddr] <= #1 di;
 
 
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task ram_print;
input [aw-1:0] start;
input [aw-1:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %h",rnum,mem[rnum]);
end
endtask
 
`endif // !VENDOR_VIRAGE
`endif // !VENDOR_AVANT
`endif // !VENDOR_ARTISAN
477,4 → 497,4
// synopsys translate_on
 
endmodule
`endif // VENDOR_XILINX
`endif // VENDOR_XILINX

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