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- This comparison shows the changes necessary to convert path
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- from Rev 33 to Rev 34
- ↔ Reverse comparison
Rev 33 → Rev 34
/trunk/generic_memories/rtl/verilog/generic_dpram.v
66,6 → 66,13
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille |
// Major cleanup. |
// Files are now compliant to Altera & Xilinx memories. |
// Memories are now compatible, i.e. drop-in replacements. |
// Added synthesizeable generic FPGA description. |
// Created "generic_memories" cvs entry. |
// |
// Revision 1.1.1.2 2001/08/21 13:09:27 damjan |
// *** empty log message *** |
// |
82,7 → 89,7
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`include "timescale.v" |
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`define VENDOR_FPGA |
//`define VENDOR_FPGA |
//`define VENDOR_XILINX |
//`define VENDOR_ALTERA |
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301,12 → 308,12
// |
// Data output drivers |
// |
assign do = (oe) ? do_reg : {dw{1'bz}}; |
assign do = (oe & rce) ? do_reg : {dw{1'bz}}; |
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// read operation |
always @(posedge rclk) |
if (rce) |
do_reg <= #1 mem[raddr]; |
do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr]; |
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// write operation |
always @(posedge wclk) |
313,6 → 320,19
if (wce && we) |
mem[waddr] <= #1 di; |
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// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
task ram_print; |
input [aw-1:0] start; |
input [aw-1:0] finish; |
integer rnum; |
begin |
for (rnum=start;rnum<=finish;rnum=rnum+1) |
$display("Addr %h = %h",rnum,mem[rnum]); |
end |
endtask |
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`endif // !VENDOR_VIRAGE |
`endif // !VENDOR_AVANT |
`endif // !VENDOR_ARTISAN |
477,4 → 497,4
// synopsys translate_on |
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endmodule |
`endif // VENDOR_XILINX |
`endif // VENDOR_XILINX |