URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 33 to Rev 34
- ↔ Reverse comparison
Rev 33 → Rev 34
/turbo8051/trunk/rtl/lib/wb_interface.v
114,7 → 114,6
reg wbd_we_o ; // westbone write req |
reg [23:0] wbd_adr_o ; // westnone address |
reg dma_ack_o ; // dma ack |
reg dma_done_o ; // dma ack |
reg [7:0] twbtrans ; // total westbone transaction |
reg dma_wr_o ; // dma write request |
reg dma_rd_o ; // dma read request |
/turbo8051/trunk/fpga/altera/turbo8051.qsf
0,0 → 1,124
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2009 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II |
# Version 9.0 Build 132 02/25/2009 SJ Full Version |
# Date created = 16:06:19 March 15, 2011 |
# |
# -------------------------------------------------------------------------- # |
# |
# Notes: |
# |
# 1) The default values for assignments are stored in the file: |
# turbo8051_assignment_defaults.qdf |
# If this file doesn't exist, see file: |
# assignment_defaults.qdf |
# |
# 2) Altera recommends that you do not modify this file. This |
# file is updated automatically by the Quartus II software |
# and any changes you make may be lost or overwritten. |
# |
# -------------------------------------------------------------------------- # |
|
|
set_global_assignment -name FAMILY "Cyclone II" |
set_global_assignment -name DEVICE EP2C15AF484A7 |
set_global_assignment -name TOP_LEVEL_ENTITY turbo8051 |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:06:19 MARCH 15, 2011" |
set_global_assignment -name LAST_QUARTUS_VERSION 9.0 |
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" |
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation |
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga |
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" |
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125 |
|
set_global_assignment -name SEARCH_PATH ../../rtl/lib |
set_global_assignment -name SEARCH_PATH ../../rtl/8051 |
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" |
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" |
set_global_assignment -name VERILOG_FILE ../../models/altera/altera_stargate_pll.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_wr_mem2mem.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/clk_ctl.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/dble_reg.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/double_sync_high.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/double_sync_low.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/dpath_ctrl.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/registers.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/sfifo.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/stat_counter.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/toggle_sync.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_crossbar.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_interface.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/wb_rd_mem2mem.v |
set_global_assignment -name VERILOG_FILE ../../rtl/lib/async_fifo.v |
set_global_assignment -name VERILOG_FILE ../../rtl/core/core.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/top/g_mac_top.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_tx_fsm.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_deferral.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_tx_top.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_rx_fsm.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_cfg_mgmt.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/s2f_sync.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_md_intf.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_ad_fltr.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_deferral_rx.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_rx_top.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_mii_intf.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/mac/g_mac_core.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/crc32/g_rx_crc32.v |
set_global_assignment -name VERILOG_FILE ../../rtl/gmac/crc32/g_tx_crc32.v |
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_core.v |
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_ctl.v |
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_if.v |
set_global_assignment -name VERILOG_FILE ../../rtl/spi/spi_cfg.v |
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_rxfsm.v |
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_txfsm.v |
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_core.v |
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart_cfg.v |
set_global_assignment -name VERILOG_FILE ../../rtl/clkgen/clkgen.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_top.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_alu_src_sel.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_alu.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_decoder.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_divide.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_multiply.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_memory_interface.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ram_top.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_acc.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_comp.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_sp.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_dptr.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_cy_select.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_psw.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_indi_addr.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ports.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_b_register.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_uart.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_int.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_tc.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_tc2.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_sfr.v |
set_global_assignment -name VERILOG_FILE ../../rtl/8051/oc8051_ram_256x8_two_bist.v |
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF |
/turbo8051/trunk/fpga/altera/summary/turbo8051.map.summary
0,0 → 1,14
Analysis & Synthesis Status : Successful - Wed Mar 16 11:29:22 2011 |
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version |
Revision Name : turbo8051 |
Top-level Entity Name : turbo8051 |
Family : Cyclone II |
Total logic elements : 7,566 |
Total combinational functions : 5,072 |
Dedicated logic registers : 3,261 |
Total registers : 3261 |
Total pins : 272 |
Total virtual pins : 0 |
Total memory bits : 3,072 |
Embedded Multiplier 9-bit elements : 0 |
Total PLLs : 1 |
/turbo8051/trunk/fpga/altera/summary/turbo8051.fit.summary
0,0 → 1,16
Fitter Status : Successful - Wed Mar 16 11:33:10 2011 |
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version |
Revision Name : turbo8051 |
Top-level Entity Name : turbo8051 |
Family : Cyclone II |
Device : EP2C15AF484A7 |
Timing Models : Final |
Total logic elements : 6,595 / 14,448 ( 46 % ) |
Total combinational functions : 5,077 / 14,448 ( 35 % ) |
Dedicated logic registers : 3,261 / 14,448 ( 23 % ) |
Total registers : 3261 |
Total pins : 272 / 315 ( 86 % ) |
Total virtual pins : 0 |
Total memory bits : 3,072 / 239,616 ( 1 % ) |
Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) |
Total PLLs : 1 / 4 ( 25 % ) |
/turbo8051/trunk/fpga/altera/summary/turbo8051.tan.summary
0,0 → 1,126
-------------------------------------------------------------------------------------- |
Timing Analyzer Summary |
-------------------------------------------------------------------------------------- |
|
Type : Worst-case tsu |
Slack : N/A |
Required Time : None |
Actual Time : 26.898 ns |
From : wb_xrom_ack |
To : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4] |
From Clock : -- |
To Clock : xtal_clk |
Failed Paths : 0 |
|
Type : Worst-case tco |
Slack : N/A |
Required Time : None |
Actual Time : 19.423 ns |
From : oc8051_top:u_8051_core|oc8051_sfr:oc8051_sfr1|wait_data |
To : wb_xram_adr[14] |
From Clock : xtal_clk |
To Clock : -- |
Failed Paths : 0 |
|
Type : Worst-case tpd |
Slack : N/A |
Required Time : None |
Actual Time : 16.411 ns |
From : wb_xram_rdata[5] |
To : ext_reg_rdata[13] |
From Clock : -- |
To Clock : -- |
Failed Paths : 0 |
|
Type : Worst-case th |
Slack : N/A |
Required Time : None |
Actual Time : -0.037 ns |
From : ext_reg_tid[1] |
To : wb_crossbar:u_wb_crossbar|master_mx_id[2][1] |
From Clock : -- |
To Clock : xtal_clk |
Failed Paths : 0 |
|
Type : Worst-case Minimum Pulse Width Requirement (Low) |
Slack : -0.564 ns |
Required Time : 2.564 ns |
Actual Time : 2.000 ns |
From : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0 |
To : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_reg |
From Clock : -- |
To Clock : -- |
Failed Paths : 58 |
|
Type : Worst-case Minimum Pulse Width Requirement (High) |
Slack : -0.564 ns |
Required Time : 2.564 ns |
Actual Time : 2.000 ns |
From : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0 |
To : uart_core:u_uart_core|async_fifo:u_txfifo|altsyncram:mem_rtl_0|altsyncram_m8g1:auto_generated|ram_block1a0~porta_we_reg |
From Clock : -- |
To Clock : -- |
Failed Paths : 58 |
|
Type : Clock Setup: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0' |
Slack : -21.494 ns |
Required Time : 250.00 MHz ( period = 4.000 ns ) |
Actual Time : 39.22 MHz ( period = 25.494 ns ) |
From : oc8051_top:u_8051_core|oc8051_decoder:oc8051_decoder1|altsyncram:WideOr30_rtl_2|altsyncram_ia01:auto_generated|ram_block1a0~porta_address_reg7 |
To : oc8051_top:u_8051_core|oc8051_ram_top:oc8051_ram_top1|oc8051_ram_256x8_two_bist:oc8051_idata|rd_data[4] |
From Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0 |
To Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0 |
Failed Paths : 310109 |
|
Type : Clock Setup: 'xtal_clk' |
Slack : 36.125 ns |
Required Time : 25.00 MHz ( period = 40.000 ns ) |
Actual Time : 258.06 MHz ( period = 3.875 ns ) |
From : clkgen:u_clkgen|pll_count[0] |
To : clkgen:u_clkgen|pll_count[11] |
From Clock : xtal_clk |
To Clock : xtal_clk |
Failed Paths : 0 |
|
Type : Clock Hold: 'clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0' |
Slack : 0.460 ns |
Required Time : 250.00 MHz ( period = 4.000 ns ) |
Actual Time : N/A |
From : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_n |
To : spi_core:u_spi_core|spi_ctl:u_spi_ctrl|cs_int_n |
From Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0 |
To Clock : clkgen:u_clkgen|altera_stargate_pll:u_pll|altpll:altpll_component|_clk0 |
Failed Paths : 0 |
|
Type : Clock Hold: 'xtal_clk' |
Slack : 0.460 ns |
Required Time : 25.00 MHz ( period = 40.000 ns ) |
Actual Time : N/A |
From : clkgen:u_clkgen|pll_count[6] |
To : clkgen:u_clkgen|pll_count[6] |
From Clock : xtal_clk |
To Clock : xtal_clk |
Failed Paths : 0 |
|
Type : Other violations (see messages) |
Slack : |
Required Time : |
Actual Time : |
From : |
To : |
From Clock : |
To Clock : |
Failed Paths : 1 |
|
Type : Total number of failed paths |
Slack : |
Required Time : |
Actual Time : |
From : |
To : |
From Clock : |
To Clock : |
Failed Paths : 310226 |
|
-------------------------------------------------------------------------------------- |
|
/turbo8051/trunk/fpga/altera/turbo8051.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2009 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II |
# Version 9.0 Build 132 02/25/2009 SJ Full Version |
# Date created = 16:06:19 March 15, 2011 |
# |
# -------------------------------------------------------------------------- # |
|
QUARTUS_VERSION = "9.0" |
DATE = "16:06:19 March 15, 2011" |
|
# Revisions |
|
PROJECT_REVISION = "turbo8051" |