URL
https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk
Subversion Repositories vga_lcd
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/
- from Rev 33 to Rev 34
- ↔ Reverse comparison
Rev 33 → Rev 34
/trunk/rtl/verilog/vga_wb_master.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: vga_wb_master.v,v 1.8 2002-03-04 11:01:59 rherveille Exp $ |
// $Id: vga_wb_master.v,v 1.9 2002-03-04 16:05:52 rherveille Exp $ |
// |
// $Date: 2002-03-04 11:01:59 $ |
// $Revision: 1.8 $ |
// $Date: 2002-03-04 16:05:52 $ |
// $Revision: 1.9 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/03/04 11:01:59 rherveille |
// Added 64x64pixels 4bpp hardware cursor support. |
// |
// Revision 1.7 2002/02/16 10:40:00 rherveille |
// Some minor bug-fixes. |
// Changed vga_ssel into vga_curproc (cursor processor). |
163,9 → 166,18
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wire [7:0] clut_offs; // color lookup table offset |
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reg [8:0] cursor_adr; |
reg cursor0_we, cursor1_we; |
// |
// hardware cursors |
reg [31:11] cursor_ba; // cursor pattern base address |
reg [ 8: 0] cursor_adr; // cursor pattern offset |
wire cursor0_we, cursor1_we; // cursor buffers write_request |
reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1 |
reg cur_acc; // cursor processors request memory access |
reg cur_acc_sel; // which cursor to reload |
wire cur_ack; // cursor processor memory access acknowledge |
wire cur_done; // done reading cursor pattern |
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// |
// module body |
// |
185,13 → 197,22
// wishbone access controller, video memory access request has highest priority (try to keep fifo full) |
always@(posedge clk_i) |
if (sclr) |
vmem_acc <= #1 1'b0; |
vmem_acc <= #1 1'b0; // video memory access request |
else |
vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone; |
vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone & !cur_acc; |
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assign vmem_ack = ack_i; |
always@(posedge clk_i) |
if (sclr) |
cur_acc <= #1 1'b0; // cursor processor memory access request |
else |
cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done; |
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assign vmem_ack = ack_i & vmem_acc; |
assign cur_ack = ack_i & cur_acc; |
assign sint = err_i; // Non recoverable error, interrupt host system |
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// select active memory page |
assign vmem_switch = ImDoneStrb; |
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218,6 → 239,7
.full() |
); |
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// |
// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay |
always@(posedge clk_i) |
if (sclr) |
239,9 → 261,11
else if (ctrl_cbsw) |
stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled) |
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// |
// generate clut-address |
assign clut_adr = {stat_acmp, clut_offs}; |
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// |
// generate burst counter |
wire [3:0] burst_cnt_val; |
assign burst_cnt_val = {1'b0, burst_cnt} -4'h1; |
360,9 → 384,52
else if (vmem_ack) |
vmemA <= #1 vmemA +30'h1; |
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//////////////////////////////////// |
// hardware cursor signals section |
// |
always@(posedge clk_i) |
if (ImDone) |
cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority |
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always@(posedge clk_i) |
if (sclr) |
begin |
ld_cursor0 <= #1 1'b0; |
ld_cursor1 <= #1 1'b0; |
end |
else |
begin |
ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel)); |
ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel)); |
end |
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// select cursor base address |
always@(posedge clk_i) |
if (!cur_acc) |
cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba; |
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// generate pattern offset |
wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1; |
assign cur_done = next_cursor_adr[9]; |
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always@(posedge clk_i) |
if (!cur_acc) |
cursor_adr <= #1 9'h0; |
else if (cur_ack) |
cursor_adr <= #1 next_cursor_adr; |
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// generate cursor buffers write enable signals |
assign cursor1_we = cur_ack & !cur_acc_sel; |
assign cursor0_we = cur_ack & cur_acc_sel; |
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////////////////////////////// |
// generate wishbone signals |
assign adr_o = {vmemA, 2'b00}; |
wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone; |
// |
assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00}; |
wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone || |
cur_acc & !cur_done; |
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always@(posedge clk_i or negedge nrst_i) |
if (!nrst_i) |
391,6 → 458,7
we_o <= #1 1'b0; // read only |
end |
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// |
// video-data buffer (temporary store data read from video memory) |
vga_fifo #(4, 32) data_fifo ( |
.clk(clk_i), |
407,7 → 475,7
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assign nvmem_req = data_fifo_hfull; |
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// |
// hookup color processor |
vga_colproc color_proc ( |
.clk(clk_i), |
428,31 → 496,28
.clut_q(clut_q) |
); |
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// |
// hookup data-source-selector && hardware cursor module |
`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled) |
reg scursor1_ld; |
wire cursor1_ld_strb; |
reg scursor1_en; |
reg scursor1_res; |
reg [31:0] scursor1_xy; |
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always@(posedge clk_i) |
if (sclr) |
scursor1_ld <= #1 1'b0; |
else |
scursor1_ld <= #1 cursor1_ld | (scursor1_ld & !(ddImDoneFifoQ & !dImDoneFifoQ)); |
assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ; |
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always@(posedge clk_i) |
if (sclr) |
scursor1_en <= #1 1'b0; |
else if (scursor1_ld) |
else if (cursor1_ld_strb) |
scursor1_en <= #1 cursor1_en; |
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always@(posedge clk_i) |
if (scursor1_ld) |
if (cursor1_ld_strb) |
scursor1_xy <= #1 cursor1_xy; |
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always@(posedge clk_i) |
if (scursor1_ld) |
if (cursor1_ld_strb) |
scursor1_res <= #1 cursor1_res; |
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vga_curproc hw_cursor1 ( |
486,7 → 551,6
`endif |
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`else // Hardware Cursor1 disabled, generate pass-through signals |
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assign ssel1_wreq = color_proc_wreq; |
assign ssel1_q = color_proc_q; |
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503,29 → 567,25
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`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled) |
reg scursor0_ld; |
wire cursor0_ld_strb; |
reg scursor0_en; |
reg scursor0_res; |
reg [31:0] scursor0_xy; |
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always@(posedge clk_i) |
if (sclr) |
scursor0_ld <= #1 1'b0; |
else |
scursor0_ld <= #1 cursor0_ld | (scursor0_ld & !(sddImDoneFifoQ & !sdImDoneFifoQ)); |
assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ; |
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always@(posedge clk_i) |
if (sclr) |
scursor0_en <= #1 1'b0; |
else if (scursor0_ld) |
else if (cursor0_ld_strb) |
scursor0_en <= #1 cursor0_en; |
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always@(posedge clk_i) |
if (scursor0_ld) |
if (cursor0_ld_strb) |
scursor0_xy <= #1 cursor0_xy; |
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always@(posedge clk_i) |
if (scursor0_ld) |
if (cursor0_ld_strb) |
scursor0_res <= #1 cursor0_res; |
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vga_curproc hw_cursor0 ( |
553,6 → 613,7
assign cc0_adr_o = 4'h0; |
`endif |
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// |
// hookup RGB buffer (temporary station between WISHBONE-clock-domain |
// and pixel-clock-domain) |
// The cursor_processor pipelines introduce a delay between the color |
576,4 → 637,3
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endmodule |
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/trunk/rtl/verilog/vga_wb_slave.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: vga_wb_slave.v,v 1.8 2002-03-04 11:01:59 rherveille Exp $ |
// $Id: vga_wb_slave.v,v 1.9 2002-03-04 16:05:52 rherveille Exp $ |
// |
// $Date: 2002-03-04 11:01:59 $ |
// $Revision: 1.8 $ |
// $Date: 2002-03-04 16:05:52 $ |
// $Revision: 1.9 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/03/04 11:01:59 rherveille |
// Added 64x64pixels 4bpp hardware cursor support. |
// |
// Revision 1.7 2002/02/25 06:13:44 rherveille |
// Fixed dat_o incomplete sensitivity list. |
// |
400,7 → 403,7
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// assign output |
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or |
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba) |
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba or ccr0_dat_o or ccr1_dat_o) |
casez (REG_ADR) // synopsis full_case parallel_case |
CTRL_ADR : reg_dato = ctrl; |
STAT_ADR : reg_dato = stat; |
/trunk/rtl/verilog/vga_cur_cregs.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: vga_cur_cregs.v,v 1.1 2002-03-04 11:01:59 rherveille Exp $ |
// $Id: vga_cur_cregs.v,v 1.2 2002-03-04 16:05:52 rherveille Exp $ |
// |
// $Date: 2002-03-04 11:01:59 $ |
// $Revision: 1.1 $ |
// $Date: 2002-03-04 16:05:52 $ |
// $Revision: 1.2 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,7 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/03/04 11:01:59 rherveille |
// Added 64x64pixels 4bpp hardware cursor support. |
// |
// |
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`include "timescale.v" |
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87,7 → 90,7
// |
// variable declarations |
// |
reg [31:0] cregs [2:0]; // color registers |
reg [31:0] cregs [7:0]; // color registers |
wire [31:0] temp_cdat; |
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// |
99,9 → 102,7
// generate host interface |
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// write section |
always@(posedge clk_i or negedge arst_i) |
if (~arst_i) |
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always@(posedge clk_i) |
if (hsel_i & hwe_i) |
cregs[hadr_i] <= #1 hdat_i; |
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/trunk/rtl/verilog/vga_curproc.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: vga_curproc.v,v 1.2 2002-03-04 11:01:59 rherveille Exp $ |
// $Id: vga_curproc.v,v 1.3 2002-03-04 16:05:52 rherveille Exp $ |
// |
// $Date: 2002-03-04 11:01:59 $ |
// $Revision: 1.2 $ |
// $Date: 2002-03-04 16:05:52 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/04 11:01:59 rherveille |
// Added 64x64pixels 4bpp hardware cursor support. |
// |
// Revision 1.1 2002/02/16 10:40:00 rherveille |
// Some minor bug-fixes. |
// Changed vga_ssel into vga_curproc (cursor processor). |
106,10 → 109,9
reg [15:0] xcnt, ycnt; |
wire xdone, ydone; |
wire [15:0] cursor_x, cursor_y; |
reg alpha, dalpha; |
wire cursor_alpha; |
reg [ 4:0] r, g, b, dr, dg, db; |
wire [ 7:0] cursor_r, cursor_g, cursor_b; |
wire cursor_isalpha; |
reg [15:0] cdat, dcdat; |
wire [ 7:0] cursor_r, cursor_g, cursor_b, cursor_alpha; |
reg inbox_x, inbox_y; |
wire inbox; |
reg dinbox, ddinbox, dddinbox; |
200,20 → 202,10
// decode cursor data for 32x32x16bpp mode |
always@(posedge clk) |
if (didat_wreq) |
begin |
alpha <= #1 dcbuf_ra[0] ? cbuf_q[31] : cbuf_q[15]; |
r <= #1 dcbuf_ra[0] ? cbuf_q[30:26] : cbuf_q[14:10]; |
g <= #1 dcbuf_ra[0] ? cbuf_q[25:21] : cbuf_q[ 9: 5]; |
b <= #1 dcbuf_ra[0] ? cbuf_q[20:16] : cbuf_q[ 4: 0]; |
end |
cdat <= #1 dcbuf_ra[0] ? cbuf_q[31:16] : cbuf_q[15:0]; |
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always@(posedge clk) |
begin |
dalpha <= #1 alpha; |
dr <= #1 r; |
dg <= #1 g; |
db <= #1 b; |
end |
dcdat <= #1 cdat; |
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// |
// decode cursor data for 64x64x4bpp mode |
234,12 → 226,12
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// |
// generate cursor colors |
assign cursor_alpha = cursor_res ? cc_dat_i[15] : dalpha; |
assign cursor_r = {cursor_res ? cc_dat_i[14:10] : dr, 3'h0}; |
assign cursor_g = {cursor_res ? cc_dat_i[ 9: 5] : dg, 3'h0}; |
assign cursor_b = {cursor_res ? cc_dat_i[ 4: 0] : db, 3'h0}; |
assign cursor_isalpha = cursor_res ? cc_dat_i[15] : dcdat[15]; |
assign cursor_alpha = cursor_res ? cc_dat_i[7:0] : dcdat[7:0]; |
assign cursor_r = {cursor_res ? cc_dat_i[14:10] : dcdat[14:10], 3'h0}; |
assign cursor_g = {cursor_res ? cc_dat_i[ 9: 5] : dcdat[ 9: 5], 3'h0}; |
assign cursor_b = {cursor_res ? cc_dat_i[ 4: 0] : dcdat[ 4: 0], 3'h0}; |
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// |
// delay image data |
always@(posedge clk) |
270,12 → 262,22
always@(posedge clk) |
dddcursor_en <= #1 ddcursor_en; |
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// Alpha blending: |
// rgb = (rgb1 * alhpa1) + (rgb2 * alpha2) |
// We generate an alpha mixer (alpha1 + alpha2 = 1) |
// rgb = (alpha1)(rgb1) + (1-alpha1)(rgb2) |
// We always mix to black (rgb2 = 0) |
// rgb = (alpha1)(rgb1) |
always@(posedge clk) |
if (ddidat_wreq) |
if (!dddcursor_en || !dddinbox) |
rgb <= #1 dddidat; |
else if (cursor_alpha) |
rgb <= #1 dddidat; |
else if (cursor_isalpha) |
`ifdef VGA_HWC_3D |
rgb <= #1 dddidat * cursor_alpha; |
`else |
rgb <= #1 dddidat; |
`endif |
else |
rgb <= #1 {cursor_r, cursor_g, cursor_b}; |
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