URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 34 to Rev 35
- ↔ Reverse comparison
Rev 34 → Rev 35
/storm_core/trunk/rtl/REG_FILE.vhd
4,7 → 4,7
-- # 30x32-Bit Banked 1w3r Register File # |
-- # (+ address translation unit) # |
-- # *************************************************** # |
-- # Last modified: 18.02.2012 # |
-- # Last modified: 06.05.2012 # |
-- ####################################################### |
|
library IEEE; |
150,8 → 150,8
end REG_FILE_STRUCTURE; |
|
|
---------------------------------------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------------------------------------- |
------------------------------------------------------------------------------------------------------------------------------------------------ |
------------------------------------------------------------------------------------------------------------------------------------------------ |
|
|
-- ####################################################### |
218,9 → 218,9
end case; |
|
--- Address Mapping: Virtual Register -> Real Register --- |
REAL_REG_SEL := (others => '0'); |
REAL_REG_SEL := (others => '0'); |
REAL_REG_SEL(07 downto 00) := VIRT_REG_SEL(07 downto 00); -- R0-R7 are always the same |
REAL_REG_SEL(31) := VIRT_REG_SEL(15); -- PC access = dummy access |
REAL_REG_SEL(31) := VIRT_REG_SEL(15); -- PC access = dummy access |
|
case (MODE_I) is |
|
/storm_core/trunk/rtl/BUS_UNIT.vhd
7,7 → 7,7
-- # cache of the STORM Core processor to a pipelined # |
-- # Wishbone compatible 32-bit bus system. # |
-- # ************************************************** # |
-- # Last modified: 17.03.2012 # |
-- # Last modified: 05.05.2012 # |
-- ###################################################### |
|
library IEEE; |
108,12 → 108,6
-- Architecture Constants -- |
constant WB_PIPE_EN : boolean := FALSE; |
|
-- Wishbone Cycle Types -- |
constant WB_CLASSIC_CYC : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- classic cycle |
constant WB_CON_BST_CYC : STD_LOGIC_VECTOR(2 downto 0) := "001"; -- constant address burst |
constant WB_INC_BST_CYC : STD_LOGIC_VECTOR(2 downto 0) := "010"; -- incrementing address burst |
constant WB_BST_END_CYC : STD_LOGIC_VECTOR(2 downto 0) := "111"; -- burst end |
|
-- Arbiter FSM -- |
type ARB_STATE_TYPE is (IDLE, ASSIGN_D_PAGE, UPLOAD_D_PAGE, IO_REQUEST, DOWNLOAD_I_PAGE, DOWNLOAD_D_PAGE, END_TRANSFER); |
signal ARB_STATE, ARB_STATE_NXT : ARB_STATE_TYPE; |
/storm_core/trunk/rtl/CORE.vhd
8,11 → 8,11
-- # - CORE.vhd (this file) | # |
-- # + STORM_CORE.vhd (package file) +---------------------------------------------------------------# |
-- # - REG_FILE.vhd | # |
-- # - OPERANT_UNIT.vhd | SSSS TTTTT OOO RRRR M M CCCC OOO RRRR EEEEE # |
-- # - MS_UNIT.vhd | S T O O R R MM MM C O O R R E # |
-- # - MULTIPLY_UNIT.vhd | SSS T O O RRRR M M M ### C O O RRRR EEE # |
-- # - BARREL_SHIFTER.vhd | S T O O R R M M C O O R R E # |
-- # - ALU.vhd | SSSS T OOO R R M M CCCC OOO R R EEEEE # |
-- # - OPERANT_UNIT.vhd | SSSS TTTTT OOO RRRR M M CCC OOO RRRR EEEEE # |
-- # - MS_UNIT.vhd | S T O O R R MM MM C O O R R E # |
-- # - MULTIPLY_UNIT.vhd | SSS T O O RRRR M M M ### C O O RRRR EEE # |
-- # - BARREL_SHIFTER.vhd | S T O O R R M M C O O R R E # |
-- # - ALU.vhd | SSSS T OOO R R M M CCC OOO R R EEEEE # |
-- # - FLOW_CTRL.vhd | # |
-- # - WB_UNIT.vhd +-------------------------------------------------------------- # |
-- # - MC_SYS.vhd | The STORM Core Processor was created by Stephan Nolting # |
21,7 → 21,7
-- # | -> stnolting@googlemail.com # |
-- # | -> stnolting@web.de # |
-- # *************************************************************************************************** # |
-- # Last modified: 17.03.2012 # |
-- # Last modified: 29.04.2012 # |
-- ####################################################################################################### |
|
library IEEE; |
/storm_core/trunk/rtl/CORE_PKG.vhd
5,7 → 5,7
-- # This file contains all needed components and # |
-- # system parameters for the STORM Core processor. # |
-- # +-------------------------------------------------+ # |
-- # Last modified: 29.03.2012 # |
-- # Last modified: 03.05.2012 # |
-- ####################################################### |
|
library IEEE; |
36,6 → 36,13
constant C_PC_ADR : STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Prog. Counter = R15 |
constant SYS_CP_ADR : STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- system coprocessor |
|
-- WISHBONE CYCLE TYPES ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant WB_CLASSIC_CYC : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- classic cycle |
constant WB_CON_BST_CYC : STD_LOGIC_VECTOR(2 downto 0) := "001"; -- constant address burst |
constant WB_INC_BST_CYC : STD_LOGIC_VECTOR(2 downto 0) := "010"; -- incrementing address burst |
constant WB_BST_END_CYC : STD_LOGIC_VECTOR(2 downto 0) := "111"; -- burst end |
|
-- OPERAND ADR BUS LOCATIONS -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant OP_A_ADR_0 : natural := 0; -- OP A ADR LSB |
93,7 → 100,7
constant CTRL_COND_3 : natural := 15; -- condition code bit 3 |
|
constant CTRL_MS : natural := 16; -- '0' = shift, '1' = multiply |
constant CTRL_AF : natural := 17; -- alter flags |
constant CTRL_AF : natural := 17; -- alter flags / reload cmsr |
constant CTRL_ALU_FS_0 : natural := 18; -- alu function set bit 0 |
constant CTRL_ALU_FS_1 : natural := 19; -- alu function set bit 1 |
constant CTRL_ALU_FS_2 : natural := 20; -- alu function set bit 2 |
239,7 → 246,6
-- COOL WORKING MUSIC --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- Carrie Underwood - Last Name |
-- Sugarland - Something More |
-- Taylor Swift - Today Was A Fairy Tale |
-- Montgomery Gentry - One In Every Crowd |
-- Tim McGraw - Something Like That |
263,11 → 269,19
-- Montgomery Gentry - Where I Come From |
-- Dixie Chicks - Ready To Run |
-- Eagle-Eye Cherry - Skull Tattoo |
-- Jake Owen - Barefoot Blue Jean Night |
-- Keith Urban - You Gonna Fly |
-- Miranda Lambert - Baggage Claim |
-- Diamond Rio - Meet In The Middle |
-- Lost Trailers - How 'Bout You Don't |
-- Alabama - Song of The South |
-- Chris Cagle - What Kinda Gone |
-- Jerrod Niemann - Lover, Lover |
-- Tim McGraw - Where The Green Grass Grows |
-- Kenny Chesney - I Go Back |
-- The Band Perry - Postcard From Paris |
-- Chris Cagle - Got My Country On |
-- Kenny Chesney - Summertime |
-- Montgomery Gentry - Something To Be Proud Of |
|
-- INTERNAL MNEMONICS --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
344,7 → 358,7
); |
end component; |
|
-- COMPONENT Operant Unit ----------------------------------------------------------------- |
-- COMPONENT Operand Unit ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component OPERAND_UNIT |
port ( |
/storm_core/trunk/rtl/FLOW_CTRL.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Operation Flow Control Unit # |
-- # *************************************************** # |
-- # Last modified: 28.03.2012 # |
-- # Last modified: 10.05.2012 # |
-- ####################################################### |
|
library IEEE; |
106,9 → 106,9
|
begin |
|
-- ####################################################################################################### |
-- ## INSTRUCTION FETCH ARBITER ## |
-- ####################################################################################################### |
-- ####################################################################################################### |
-- ## INSTRUCTION FETCH ARBITER ## |
-- ####################################################################################################### |
|
-- Instruction Fetch Arbiter ----------------------------------------------------------------- |
-- ---------------------------------------------------------------------------------------------- |
149,7 → 149,7
end if; |
|
--- Default values and first cycle init --- |
DIS_OF <= STOP_IF_I; |
DIS_OF <= STOP_IF_I and (not MULTI_CYCLE_REQ); |
DIS_MS <= HOLD_BUS_I(0); |
DIS_EX <= BRANCH_TAKEN or EXECUTE_INT_I; |
CTRL_REG_HALT <= HOLD_BUS_I(0); |
233,14 → 233,13
|
|
|
-- ####################################################################################################### |
-- ## OPERAND FETCH ## |
-- ####################################################################################################### |
-- ####################################################################################################### |
-- ## OPERAND FETCH ## |
-- ####################################################################################################### |
|
-- Stage "Operand Fetch" Control Unit -------------------------------------------------------- |
-- ---------------------------------------------------------------------------------------------- |
OF_CTRL_UNIT: process(CLK_I, DEC_CTRL_FF, OPCODE_MISC_I(91 downto 87)) |
variable enable_v : std_logic; |
begin |
--- Opcode Decoder Connection --- |
if rising_edge(CLK_I) then |
250,7 → 249,6
IMM_O <= (others => '0'); |
OPCODE_CTRL_O(9 downto 0) <= (others => '0'); |
elsif (G_HALT_I = '0') and (CTRL_REG_HALT = '0') then |
--OPCODE_CTRL_O(9 downto 0) <= OPCODE_MISC_I(96 downto 87); -- next offset & next dual op |
OPCODE_CTRL_O(9 downto 1) <= OPCODE_MISC_I(96 downto 88); -- next offset & next dual op |
OPCODE_CTRL_O(0) <= OPCODE_MISC_I(87) and (not DIS_OF); -- flag for multi cycle ops |
DEC_CTRL_FF <= OPCODE_CTRL_I; |
260,15 → 258,12
end if; |
end if; |
|
--- Check for NEVER condition --- |
enable_v := '1'; |
--- Check for NEVER EVER condition --- |
DEC_CTRL <= DEC_CTRL_FF; |
if (DEC_CTRL_FF(CTRL_COND_3 downto CTRL_COND_0) = COND_NV) then |
enable_v := '0'; |
DEC_CTRL(CTRL_EN) <= '0'; |
end if; |
|
DEC_CTRL <= DEC_CTRL_FF; |
DEC_CTRL(CTRL_EN) <= DEC_CTRL_FF(CTRL_EN) and enable_v; |
|
--- Multi Cycle OP Request --- |
MULTI_CYCLE_REQ <= '1'; |
if (OPCODE_MISC_I(91 downto 87) = "00000") then -- next dual op |
284,9 → 279,9
|
|
|
-- ####################################################################################################### |
-- ## MULTIPLICATION & SHIFT ## |
-- ####################################################################################################### |
-- ####################################################################################################### |
-- ## MULTIPLICATION & SHIFT ## |
-- ####################################################################################################### |
|
-- Pipeline Registers ------------------------------------------------------------------------ |
-- ---------------------------------------------------------------------------------------------- |
313,9 → 308,9
|
|
|
-- ##################################################################################################### |
-- ## ALU OPERATION & MCR / CP ACCESS ## |
-- ##################################################################################################### |
-- ##################################################################################################### |
-- ## ALU OPERATION & MCR / CP ACCESS ## |
-- ##################################################################################################### |
|
-- Pipeline Registers ------------------------------------------------------------------------ |
-- ---------------------------------------------------------------------------------------------- |
428,9 → 423,9
|
|
|
-- ##################################################################################################### |
-- ## DATA CACHE ACCESS ## |
-- ##################################################################################################### |
-- ##################################################################################################### |
-- ## DATA CACHE ACCESS ## |
-- ##################################################################################################### |
|
-- Pipeline Registers ------------------------------------------------------------------------ |
-- ---------------------------------------------------------------------------------------------- |
463,9 → 458,9
|
|
|
-- ##################################################################################################### |
-- ## DATA WRITE BACK ## |
-- ##################################################################################################### |
-- ##################################################################################################### |
-- ## DATA WRITE BACK ## |
-- ##################################################################################################### |
|
-- Pipeline Registers ------------------------------------------------------------------------ |
-- ---------------------------------------------------------------------------------------------- |
/storm_core/trunk/rtl/MC_SYS.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Machine Control System # |
-- # *************************************************** # |
-- # Last modified: 29.03.2012 # |
-- # Last modified: 13.05.2012 # |
-- ####################################################### |
|
library IEEE; |
265,6 → 265,7
FLAG_BUS(SREG_Z_FLAG) <= FLAG_I(1); -- Zero Flag |
FLAG_BUS(SREG_N_FLAG) <= FLAG_I(2); -- Negative Flag |
FLAG_BUS(SREG_O_FLAG) <= FLAG_I(3); -- Overflow Flag |
FLAG_BUS(SREG_SHIN_M) <= '0'; |
FLAG_BUS(SREG_FIQ_DIS) <= MCR_CMSR(SREG_FIQ_DIS); -- keep current interrupt settings |
FLAG_BUS(SREG_IRQ_DIS) <= MCR_CMSR(SREG_IRQ_DIS); -- keep current interrupt settings |
FLAG_BUS(SREG_DAB_DIS) <= MCR_CMSR(SREG_DAB_DIS); -- keep current interrupt settings |
273,10 → 274,10
--- Short Instruction Mode --- |
if (CTRL_I(CTRL_EN) = '1') and (CTRL_I(CTRL_BX) = '1') and (SHIN_EN = TRUE) then |
FLAG_BUS(SREG_SHIN_M) <= MCR_DATA_I(0); |
INVALID_BX_REQ <= MCR_DATA_I(0); |
INVALID_BX_REQ <= MCR_DATA_I(0); |
else |
FLAG_BUS(SREG_SHIN_M) <= MCR_CMSR(0); |
INVALID_BX_REQ <= '0'; |
FLAG_BUS(SREG_SHIN_M) <= MCR_CMSR(SREG_SHIN_M); |
INVALID_BX_REQ <= '0'; |
end if; |
|
--- Priority 1: Data Fetch Abort --- |
357,13 → 358,13
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
MCR_PC <= BOOT_VEC; -- start-up address |
MCR_CMSR <= x"000003DF"; -- all INTs disabled and we're in SYSTEM32 mode |
SMSR_FIQ <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_SVC <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_ABT <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_IRQ <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_UND <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_SYS <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
MCR_CMSR <= x"000003DF"; -- all INTs disabled and we are in SYSTEM32 mode |
SMSR_FIQ <= x"000003DF"; -- all INTs disabled and return to SYSTEM32 mode |
SMSR_SVC <= x"000003DF"; -- all INTs disabled and return to SYSTEM32 mode |
SMSR_ABT <= x"000003DF"; -- all INTs disabled and return to SYSTEM32 mode |
SMSR_IRQ <= x"000003DF"; -- all INTs disabled and return to SYSTEM32 mode |
SMSR_UND <= x"000003DF"; -- all INTs disabled and return to SYSTEM32 mode |
SMSR_SYS <= x"000003DF"; -- all INTs disabled and return to SYSTEM32 mode |
elsif (G_HALT_I = '0') then |
|
|
389,8 → 390,10
cmsr_acc_case_v := CONT_EXE & CTRL_I(CTRL_EN) & cont_ret_v & mwr_cmsr_v; |
case cmsr_acc_case_v is |
when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => |
MCR_CMSR(9 downto 0) <= FLAG_BUS(9 downto 0); -- interrupt de, ctrl, mode bits |
MCR_CMSR(09 downto 0) <= FLAG_BUS(09 downto 0); -- interrupt de, ctrl, mode bits |
-- MCR_CMSR(31 downto 0) <= FLAG_BUS(31 downto 0); |
when "0110" | "0111" => -- context down change |
-- when "0110" | "0111" | "0010" | "0011" => -- context down change |
case (current_mode_v) is -- current mode |
when FIQ32_MODE => MCR_CMSR <= SMSR_FIQ; |
when Supervisor32_MODE => MCR_CMSR <= SMSR_SVC; |
398,7 → 401,7
when IRQ32_MODE => MCR_CMSR <= SMSR_IRQ; |
when Undefined32_MODE => MCR_CMSR <= SMSR_UND; |
when System32_MODE => MCR_CMSR <= SMSR_SYS; |
when others => NULL; |
when others => MCR_CMSR <= MCR_CMSR; |
end case; |
when "0101" => -- manual write |
if (current_mode_v = User32_MODE) or (CTRL_I(CTRL_MREG_FA) = '1') then -- restricted access for user mode |
409,7 → 412,7
when "0100" => -- automatic access |
if (CTRL_I(CTRL_AF) = '1') then -- alter flags |
MCR_CMSR <= FLAG_BUS(31 downto 0); -- update whole sreg |
else |
else -- keep flags |
MCR_CMSR <= MCR_CMSR(31 downto 28) & FLAG_BUS(27 downto 0); -- update without flags |
end if; |
when others => -- keep CMSR |
422,7 → 425,7
case (smsr_acc_case_v) is |
-- Content up-change -- |
when "100" | "101" | "110" | "111" => |
case (NEW_MODE) is |
case (NEW_MODE) is -- save old machine status register |
when FIQ32_MODE => SMSR_FIQ <= MCR_CMSR; |
when Supervisor32_MODE => SMSR_SVC <= MCR_CMSR; |
when Abort32_MODE => SMSR_ABT <= MCR_CMSR; |
495,9 → 498,9
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
CP_REG_FILE <= (others => (others => '0')); -- clear all |
CP_REG_FILE(CP_ID_REG_0) <= x"07DC031D"; -- core update date |
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID |
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;) |
CP_REG_FILE(CP_ID_REG_0) <= x"07DC050D"; -- core update date |
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; |
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; |
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length |
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_PIO) <= '1'; -- IO area is protected |
else |
546,7 → 549,7
end if; |
end if; |
|
-- Internal IO Register ------------------------------------------- |
-- Internal IO Register ------------------------------------------------------- |
CP_REG_FILE(CP_IO_PORT)(CP_IO_I_MSB downto CP_IO_I_LSB) <= IO_PORT_I; |
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_IO_PORT) then |
CP_REG_FILE(CP_IO_PORT)(CP_IO_O_MSB downto CP_IO_O_LSB) <= MCR_DATA_I(CP_IO_O_MSB downto CP_IO_O_LSB); |
/storm_core/trunk/rtl/OPCODE_DECODER.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # ARM-Native OPCODE Decoding Unit # |
-- # *************************************************** # |
-- # Last modified: 29.03.2012 # |
-- # Last modified: 13.05.2012 # |
-- ####################################################### |
|
library IEEE; |
602,7 → 602,7
|
--- Special functions --- |
DEC_CTRL(CTRL_AF) <= INSTR_REG(20) and INSTR_REG(22) and pc_in_list_v; -- copy SMSR => CMSR when transf. the PC |
DEC_CTRL(CTRL_RD_USR) <= (not INSTR_REG(20)) and INSTR_REG(22); -- read regs from user bank |
DEC_CTRL(CTRL_RD_USR) <= (not INSTR_REG(20)) and INSTR_REG(22) ; -- read regs from user bank |
DEC_CTRL(CTRL_WR_USR) <= INSTR_REG(20) and INSTR_REG(22) and (not pc_in_list_v); -- write regs to user bank |
|
--- The memory access itself --- |
633,12 → 633,14
end loop; |
|
-- Control for BASE' write back -- |
DEC_CTRL(CTRL_COND_3 downto CTRL_COND_0) <= INSTR_REG(31 downto 28); -- enable wb cycle if wanted |
DEC_CTRL(CTRL_COND_3 downto CTRL_COND_0) <= INSTR_REG(31 downto 28); |
DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST = BASE |
DEC_CTRL(CTRL_WB_EN) <= INSTR_REG(21); -- WB EN |
NEXT_DUAL_OP <= "00001"; -- prepare for start |
REG_SEL(OP_C_IS_REG) <= '0'; |
DEC_CTRL(CTRL_MEM_ACC) <= '0'; -- no memory access, thank you |
DEC_CTRL(CTRL_RD_USR) <= '0'; -- read regs from current bank |
DEC_CTRL(CTRL_WR_USR) <= '0'; -- write regs to current bank |
if (INSTR_REG(23) = '0') then -- sub index |
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= A_SUB; -- ALU_CTRL = SUB |
else -- add index |
687,9 → 689,10
|
when others => -- COPROCESSOR REGISTER TRANSFER / SOFTWARE INTERRUPT |
-- ============================================================================================ |
DEC_CTRL(CTRL_SWI) <= INSTR_REG(25) and INSTR_REG(24); -- SOFTWARE INTERRUPT |
if (INSTR_REG(25 downto 24) = "11") then |
DEC_CTRL(CTRL_SWI) <= '1'; -- SOFTWARE INTERRUPT |
|
if (INSTR_REG(25 downto 24) = "10") and (INSTR_REG(11 downto 8) = SYS_CP_ADR) and (INSTR_REG(4) = '1') then -- CP #15 action |
elsif (INSTR_REG(25 downto 24) = "10") and (INSTR_REG(11 downto 8) = SYS_CP_ADR) and (INSTR_REG(4) = '1') then -- CP #15 action |
DEC_CTRL(CTRL_CP_ACC) <= '1'; -- coprocessor access |
DEC_CTRL(CTRL_CP_RW) <= not INSTR_REG(20); -- read/write |
DEC_CTRL(CTRL_CP_REG_3 downto CTRL_CP_REG_0) <= INSTR_REG(19 downto 16); |
/storm_core/trunk/doc/STORM CORE datasheet.pdf
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