OpenCores
URL https://opencores.org/ocsvn/dblclockfft/dblclockfft/trunk

Subversion Repositories dblclockfft

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    from Rev 34 to Rev 35
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Rev 34 → Rev 35

/dblclockfft/trunk/bench/cpp/Makefile
48,8 → 48,15
OBJDR:= ../../sw/fft-core/obj_dir
VSRCD = ../../sw/fft-core
TBODR:= ../rtl/obj_dir
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"')
ifneq ($(VERILATOR_ROOT),)
VERILATOR:=$(VERILATOR_ROOT)/bin/verilator
else
VERILATOR:=verilator
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"')
endif
export $(VERILATOR)
VROOT := $(VERILATOR_ROOT)
VDEFS:= $(shell ./vversion.sh)
VINC := -I$(VROOT)/include -I$(OBJDR)/ -I$(TBODR)/
# MPYLB:= $(OBJDR)/Vshiftaddmpy__ALL.a
MPYLB:= $(OBJDR)/Vlongbimpy__ALL.a
61,33 → 68,34
FFTLB:= $(OBJDR)/Vfftmain__ALL.a
IFTLB:= $(TBODR)/Vifft_tb__ALL.a
STGLB:= $(OBJDR)/Vfftstage_o2048__ALL.a
VSRCS:= $(VROOT)/include/verilated.cpp $(VROOT)/include/verilated_vcd_c.cpp
 
mpy_tb: mpy_tb.cpp fftsize.h twoc.h $(MPYLB)
g++ -g $(VINC) $< twoc.cpp $(MPYLB) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(MPYLB) $(VSRCS) -o $@
 
dblrev_tb: dblrev_tb.cpp twoc.cpp twoc.h fftsize.h $(DBLRV)
g++ -g $(VINC) $< twoc.cpp $(DBLRV) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(DBLRV) $(VSRCS) -o $@
 
dblstage_tb: dblstage_tb.cpp twoc.cpp twoc.h $(DBLSG)
g++ -g $(VINC) $< twoc.cpp $(DBLSG) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(DBLSG) $(VSRCS) -o $@
 
qtrstage_tb: qtrstage_tb.cpp twoc.cpp twoc.h $(QTRSG)
g++ -g $(VINC) $< twoc.cpp $(QTRSG) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(QTRSG) $(VSRCS) -o $@
 
butterfly_tb: butterfly_tb.cpp twoc.cpp twoc.h fftsize.h $(BFLYL)
g++ -g $(VINC) $< twoc.cpp $(BFLYL) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(BFLYL) $(VSRCS) -o $@
 
hwbfly_tb: hwbfly_tb.cpp twoc.cpp twoc.h $(HWBFY)
g++ -g $(VINC) $< twoc.cpp $(HWBFY) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(HWBFY) $(VSRCS) -o $@
 
fftstage_o2048_tb: fftstage_o2048_tb.cpp twoc.cpp twoc.h $(STGLB)
g++ -g $(VINC) $< twoc.cpp $(STGLB) $(VERILATOR_ROOT)/include/verilated.cpp -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(STGLB) $(VSRCS) -o $@
 
fft_tb: fft_tb.cpp twoc.cpp twoc.h fftsize.h $(FFTLB)
g++ -g $(VINC) $< twoc.cpp $(FFTLB) $(VERILATOR_ROOT)/include/verilated.cpp -lfftw3 -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(FFTLB) $(VSRCS) -lfftw3 -o $@
 
ifft_tb: ifft_tb.cpp twoc.cpp twoc.h fftsize.h $(IFTLB)
g++ -g $(VINC) $< twoc.cpp $(IFTLB) $(VERILATOR_ROOT)/include/verilated.cpp -lfftw3 -o $@
g++ -g $(VINC) $(VDEFS) $< twoc.cpp $(IFTLB) $(VSRCS) -lfftw3 -o $@
 
.PHONY: HEX
# HEX: cmem_e2048.hex cmem_e1024.hex cmem_e512.hex cmem_e256.hex
/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp
137,29 → 137,6
m_bfly->o_left,
m_bfly->o_right,
m_bfly->o_aux);
/*
printf("\tFI=%010lx",
((((long)m_bfly->v__DOT__r_aux_2)&1l)<<34)
|((((long)m_bfly->v__DOT__r_sum_r)&0x01ffffl)<<17)
|(((long)m_bfly->v__DOT__r_sum_i)&0x01ffffl));
printf("\tFO=%010lx SUMR=%05x SUMI=%05x A=%d",
m_bfly->v__DOT__fifo_read,
m_bfly->v__DOT__r_sum_r,
m_bfly->v__DOT__r_sum_i,
m_bfly->v__DOT__r_aux_2);
printf("\tML=%09lx, MR=%09lx, ",
m_left[ (m_addr-23)&(64-1)],
m_right[(m_addr-23)&(64-1)]);
*/
/*
printf("\tBLFTR=%10lx BLFTI=%10lx",
m_bfly->v__DOT__b_left_r & (~(-1l<<40)),
m_bfly->v__DOT__b_left_i & (~(-1l<<40)));
printf("\tMPYR=%10lx MPYI=%10lx",
m_bfly->v__DOT__mpy_r & (~(-1l<<40)),
m_bfly->v__DOT__mpy_i & (~(-1l<<40)));
printf("\n");
*/
 
if ((m_syncd)&&(m_left[(m_addr-m_offset)&(64-1)] != m_bfly->o_left)) {
printf("WRONG O_LEFT! (%lx(exp) != %lx(sut))\n",
/dblclockfft/trunk/bench/cpp/dblrev_tb.cpp
51,6 → 51,14
#define DATAMSK (DATALEN-1)
#define PAGEMSK (FFTSIZE)
 
#ifdef NEW_VERILATOR
#define VVAR(A) dblreverse__DOT_ ## A
#else
#define VVAR(A) v__DOT_ ## A
#endif
 
#define iaddr VVAR(_iaddr)
 
void tick(Vdblreverse *dblrev) {
dblrev->i_clk = 0;
dblrev->eval();
107,7 → 115,7
printf("k=%3d: IN = %6lx : %6lx, OUT = %6lx : %6lx, SYNC = %d\t(%x)\n",
k, dblrev->i_in_0, dblrev->i_in_1,
dblrev->o_out_0, dblrev->o_out_1, dblrev->o_sync,
dblrev->v__DOT__iaddr);
dblrev->iaddr);
 
if ((k>BREV_OFFSET)&&(((BREV_OFFSET==(k&(FFTMASK>>1)))?1:0) != dblrev->o_sync)) {
fprintf(stdout, "FAIL, BAD SYNC\n");
/dblclockfft/trunk/bench/cpp/fft_tb.cpp
49,6 → 49,29
 
#include "fftsize.h"
 
 
#ifdef NEW_VERILATOR
#define VVAR(A) fftmain__DOT_ ## A
#else
#define VVAR(A) v__DOT_ ## A
#endif
 
 
#define revstage_iaddr VVAR(_revstage__DOT__iaddr)
#define br_sync VVAR(_br_sync)
#define br_started VVAR(_r_br_started)
#define w_s2048 VVAR(_w_s2048)
#define w_s1024 VVAR(_w_s1024)
#define w_s512 VVAR(_w_s512)
#define w_s256 VVAR(_w_s256)
#define w_s128 VVAR(_w_s128)
#define w_s64 VVAR(_w_s64)
#define w_s32 VVAR(_w_s32)
#define w_s16 VVAR(_w_s16)
#define w_s8 VVAR(_w_s8)
#define w_s4 VVAR(_w_s4)
 
 
#define IWIDTH FFT_IWIDTH
#define OWIDTH FFT_OWIDTH
#define LGWIDTH FFT_LGWIDTH
264,57 → 287,42
m_iaddr, m_oaddr,
lft, rht, m_fft->o_left, m_fft->o_right);
 
/*
printf(" %011lx,%011lx", m_fft->v__DOT__w_e2048,
m_fft->v__DOT__w_o2048);
 
printf(" BF(%d,%11x,%11x,%11lx -> %d,%03x,%8x,%8x)", // %d,%11x,%11x)",
m_fft->v__DOT__stage_o2048__DOT__ib_sync,
m_fft->v__DOT__stage_o2048__DOT__ib_a,
m_fft->v__DOT__stage_o2048__DOT__ib_b,
m_fft->v__DOT__stage_o2048__DOT__ib_c,
m_fft->v__DOT__stage_o2048__DOT__ob_sync,
m_fft->v__DOT__stage_o2048__DOT__oB,
m_fft->v__DOT__stage_o2048__DOT__bfly__DOT__rnd_left_r,
m_fft->v__DOT__stage_o2048__DOT__bfly__DOT__rnd_right_r);
*/
 
#ifndef APPLY_BITREVERSE_LOCALLY
printf(" [%3x]%s", m_fft->v__DOT__revstage__DOT__iaddr,
(m_fft->v__DOT__br_sync)?"S"
:((m_fft->v__DOT__r_br_started)?".":"x"));
printf(" [%3x]%s", m_fft->revstage_iaddr,
(m_fft->br_sync)?"S"
:((m_fft->br_started)?".":"x"));
#endif
 
printf(" ");
#if (FFT_SIZE>=2048)
printf("%s", (m_fft->v__DOT__w_s2048)?"S":"-");
printf("%s", (m_fft->w_s2048)?"S":"-");
#endif
#if (FFT_SIZE>1024)
printf("%s", (m_fft->v__DOT__w_s1024)?"S":"-");
printf("%s", (m_fft->w_s1024)?"S":"-");
#endif
#if (FFT_SIZE>512)
printf("%s", (m_fft->v__DOT__w_s512)?"S":"-");
printf("%s", (m_fft->w_s512)?"S":"-");
#endif
#if (FFT_SIZE>256)
printf("%s", (m_fft->v__DOT__w_s256)?"S":"-");
printf("%s", (m_fft->w_s256)?"S":"-");
#endif
#if (FFT_SIZE>128)
printf("%s", (m_fft->v__DOT__w_s128)?"S":"-");
printf("%s", (m_fft->w_s128)?"S":"-");
#endif
#if (FFT_SIZE>64)
printf("%s", (m_fft->v__DOT__w_s64)?"S":"-");
printf("%s", (m_fft->w_s64)?"S":"-");
#endif
#if (FFT_SIZE>32)
printf("%s", (m_fft->v__DOT__w_s32)?"S":"-");
printf("%s", (m_fft->w_s32)?"S":"-");
#endif
#if (FFT_SIZE>16)
printf("%s", (m_fft->v__DOT__w_s16)?"S":"-");
printf("%s", (m_fft->w_s16)?"S":"-");
#endif
#if (FFT_SIZE>8)
printf("%s", (m_fft->v__DOT__w_s8)?"S":"-");
printf("%s", (m_fft->w_s8)?"S":"-");
#endif
#if (FFT_SIZE>4)
printf("%s", (m_fft->v__DOT__w_s4)?"S":"-");
printf("%s", (m_fft->w_s4)?"S":"-");
#endif
 
printf(" %s%s\n",
/dblclockfft/trunk/bench/cpp/fftstage_o2048_tb.cpp
47,6 → 47,16
#include "Vfftstage_o2048.h"
#include "verilated.h"
 
 
#ifdef NEW_VERILATOR
#define VVAR(A) fftstage_o2048__DOT_ ## A
#else
#define VVAR(A) v__DOT_ ## A
#endif
 
#define cmem VVAR(_cmem)
#define iaddr VVAR(_iaddr)
 
#define FFTBITS 11
#define FFTLEN (1<<FFTBITS)
#define FFTSIZE FFTLEN
180,7 → 190,7
i_data &= (~(-1l<<(2*IWIDTH)));
m_ftstage->i_data = i_data;
 
cv = m_ftstage->v__DOT__cmem[m_iaddr & SPANMASK];
cv = m_ftstage->cmem[m_iaddr & SPANMASK];
bc = m_iaddr & (1<<LGSPAN);
if (!bc)
m_vals[m_iaddr & (SPANMASK)] = i_data;
222,8 → 232,9
m_iaddr, m_oaddr,
i_sync, i_data & (~(-1l << (2*IWIDTH))),
m_ftstage->o_data, m_ftstage->o_sync,
m_ftstage->v__DOT__iaddr&(FFTMASK>>1),
m_ftstage->v__DOT__cmem[m_ftstage->v__DOT__iaddr&(SPANMASK>>1)] & (~(-1l<<(2*CWIDTH))),
 
m_ftstage->iaddr&(FFTMASK>>1),
m_ftstage->cmem[m_ftstage->iaddr&(SPANMASK>>1)] & (~(-1l<<(2*CWIDTH))),
m_out[raddr]);
 
if ((m_syncd)&&(m_ftstage->o_sync != ((((m_iaddr-m_offset)&((1<<(LGSPAN+1))-1))==0)?1:0))) {
/dblclockfft/trunk/bench/cpp/hwbfly_tb.cpp
46,6 → 46,13
#include "verilated.h"
#include "twoc.h"
 
#ifdef NEW_VERILATOR
#define VVAR(A) hwbfly__DOT_ ## A
#else
#define VVAR(A) v__DOT_ ## A
#endif
 
 
class BFLY_TB {
public:
Vhwbfly *m_bfly;
123,32 → 130,6
m_bfly->o_left,
m_bfly->o_right,
m_bfly->o_aux);
/*
printf("\tFI=%010lx",
((((long)m_bfly->v__DOT__r_aux_2)&1l)<<34)
|((((long)m_bfly->v__DOT__r_sum_r)&0x01ffffl)<<17)
|(((long)m_bfly->v__DOT__r_sum_i)&0x01ffffl));
printf("\tFO=%010lx SUMR=%05x SUMI=%05x A=%d",
m_bfly->v__DOT__left_saved,
m_bfly->v__DOT__r_sum_r,
m_bfly->v__DOT__r_sum_i,
m_bfly->v__DOT__r_aux_2);
printf("\tDIFR=%05x DIFI=%05x ",
m_bfly->v__DOT__r_dif_r,
m_bfly->v__DOT__r_dif_i);
printf("\tML=%09lx, MR=%09lx (o=%d)",
m_left[ (m_addr-4)&(64-1)],
m_right[(m_addr-4)&(64-1)], m_offset);
printf("\tBLFTR=%10lx BLFTI=%10lx",
m_bfly->v__DOT__b_left_r & (~(-1l<<40)),
m_bfly->v__DOT__b_left_i & (~(-1l<<40)));
printf("\tBRHTR=%10lx BRHTI=%10lx",
m_bfly->v__DOT__b_right_r & (~(-1l<<40)),
m_bfly->v__DOT__b_right_i & (~(-1l<<40)));
printf("\tMPYR=%10lx MPYI=%10lx",
m_bfly->v__DOT__mpy_r & (~(-1l<<40)),
m_bfly->v__DOT__mpy_i & (~(-1l<<40)));
*/
printf("\n");
 
if ((m_syncd)&&(m_left[(m_addr-m_offset)&(64-1)] != m_bfly->o_left)) {
/dblclockfft/trunk/bench/cpp/qtrstage_tb.cpp
54,6 → 54,21
#define ASIZ 32
#define AMSK (ASIZ-1)
 
#ifdef NEW_VERILATOR
#define VVAR(A) qtrstage__DOT_ ## A
#else
#define VVAR(A) v__DOT_ ## A
#endif
 
#define sum_r VVAR(_sum_r)
#define sum_i VVAR(_sum_i)
#define diff_r VVAR(_diff_r)
#define diff_i VVAR(_diff_i)
#define pipeline VVAR(_pipeline)
#define iaddr VVAR(_iaddr)
#define imem VVAR(_imem)
#define wait_for_sync VVAR(_wait_for_sync)
 
class QTRTEST_TB {
public:
Vqtrstage *m_qstage;
150,15 → 165,16
printf("k=%4d: ISYNC=%d, IN = %08x, OUT =%09lx, SYNC=%d\t%5x,%5x,%5x,%5x\t%x %4x %8x %d\n",
(m_addr-m_offset), isync, m_qstage->i_data,
m_qstage->o_data, m_qstage->o_sync,
m_qstage->v__DOT__sum_r,
m_qstage->v__DOT__sum_i,
m_qstage->v__DOT__diff_r,
m_qstage->v__DOT__diff_i,
m_qstage->v__DOT__pipeline,
m_qstage->v__DOT__iaddr,
m_qstage->v__DOT__imem,
m_qstage->v__DOT__wait_for_sync);
 
m_qstage->sum_r,
m_qstage->sum_i,
m_qstage->diff_r,
m_qstage->diff_i,
m_qstage->pipeline,
m_qstage->iaddr,
m_qstage->imem,
m_qstage->wait_for_sync);
 
check_results();
}
 
/dblclockfft/trunk/bench/cpp/vversion.sh
0,0 → 1,65
#!/bin/bash
################################################################################
##
## Filename: vversion.sh
##
## Project: Zip CPU -- a small, lightweight, RISC CPU soft core
##
## Purpose: To determine whether or not the verilator prefix for internal
## variables is v__DOT__ or the name of the top level followed by
## __DOT__. If it is the later, output -DNEW_VERILATOR, else be silent.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2017, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
if [[ -x ${VERILATOR_ROOT}/bin/verilator ]];
then
export VERILATOR=${VERILATOR_ROOT}/bin/verilator
fi
if [[ ! -x ${VERILATOR} ]];
then
export VERILATOR=verilator
fi
if [[ ! -x `which ${VERILATOR}` ]];
then
echo "Verilator not found in environment or in path"
exit -1
fi
 
VVERLINE=`${VERILATOR} -V | grep -i ^Verilator`
VVER=`echo ${VVERLINE} | cut -d " " -f 2`
LATER=`echo $VVER \>= 3.9 | bc`
if [[ $LATER > 0 ]];
then
echo "-DNEW_VERILATOR"
else
echo "-DOLD_VERILATOR"
fi
exit 0
dblclockfft/trunk/bench/cpp/vversion.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dblclockfft/trunk/bench/rtl/Makefile =================================================================== --- dblclockfft/trunk/bench/rtl/Makefile (revision 34) +++ dblclockfft/trunk/bench/rtl/Makefile (revision 35) @@ -41,13 +41,24 @@ ## ## ##########################################################################/ +## +## +# This is really simple ... +all: ifft_tb +CORED := fft-core +ifneq ($(VERILATOR_ROOT),) +VERILATOR:=$(VERILATOR_ROOT)/bin/verilator +else +VERILATOR:=verilator +VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"') +endif +export $(VERILATOR) +VROOT := $(VERILATOR_ROOT) +VSRCD := ../../sw/$(CORED) +VFLAGS := -Wall -MMD --trace -y $(VSRCD) -cc -OBJDR:= ../../sw/fft-core/obj_dir -VSRCD:= ../../sw/fft-core LCLDR:= obj_dir -VINC := -I/usr/share/verilator/include -I$(OBJDR)/ -I$(LCLDR)/ IFTLB:= $(LCLDR)/Vifft_tb__ALL.a -VERILATOR_ROOT := /usr/share/verilator .PHONY: ifft_tb ifft_tb: $(IFTLB) @@ -55,7 +66,7 @@ $(IFTLB): $(LCLDR)/Vifft_tb.cpp cd $(LCLDR); make -f Vifft_tb.mk $(LCLDR)/Vifft_tb.cpp: ifft_tb.v $(VSRCD)/fftmain.v $(VSRCD)/ifftmain.v - verilator -y $(VSRCD) -cc ifft_tb.v + $(VERILATOR) $(VFLAGS) ifft_tb.v .PHONY: clean clean:
/dblclockfft/trunk/sw/Makefile
49,6 → 49,15
OBJDR := $(CORED)/obj_dir
TESTSZ := 2048
BENCHD := ../bench/cpp
ifneq ($(VERILATOR_ROOT),)
VERILATOR:=$(VERILATOR_ROOT)/bin/verilator
else
VERILATOR:=verilator
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"')
endif
export $(VERILATOR)
VROOT := $(VERILATOR_ROOT)
VFLAGS := -Wall -MMD --trace -cc
 
fftgen: fftgen.o
$(CXX) $< -o $@
70,13 → 79,13
.PHONY: fft
fft: fftgen
./fftgen -f $(TESTSZ) -n 16 -p 6 -a $(BENCHD)/fftsize.h
cd $(CORED)/; verilator -cc fftmain.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) fftmain.v
cd $(OBJDR); make -f Vfftmain.mk
 
.PHONY: ifft
ifft: fftgen
./fftgen -f $(TESTSZ) -i -n 22 -p 6 -a $(BENCHD)/ifftsize.h
cd $(CORED)/; verilator -cc ifftmain.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) ifftmain.v
cd $(OBJDR); make -f Vifftmain.mk
 
.PHONY: shiftaddmpy
84,7 → 93,7
 
$(CORED)/shiftaddmpy.v: fft
$(OBJDR)/Vshiftaddmpy.cpp $(OBJDR)/Vshiftaddmpy.h: $(CORED)/shiftaddmpy.v
cd $(CORED)/; verilator -cc shiftaddmpy.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) shiftaddmpy.v
$(OBJDR)/Vshiftaddmpy__ALL.a: $(OBJDR)/Vshiftaddmpy.h
$(OBJDR)/Vshiftaddmpy__ALL.a: $(OBJDR)/Vshiftaddmpy.cpp
cd $(OBJDR)/; make -f Vshiftaddmpy.mk
94,7 → 103,7
 
$(CORED)/longbimpy.v: fft
$(OBJDR)/Vlongbimpy.cpp $(OBJDR)/Vlongbimpy.h: $(CORED)/longbimpy.v
cd $(CORED)/; verilator -cc longbimpy.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) longbimpy.v
$(OBJDR)/Vlongbimpy__ALL.a: $(OBJDR)/Vlongbimpy.h
$(OBJDR)/Vlongbimpy__ALL.a: $(OBJDR)/Vlongbimpy.cpp
cd $(OBJDR)/; make -f Vlongbimpy.mk
104,7 → 113,7
 
$(CORED)/butterfly.v: fft
$(OBJDR)/Vbutterfly.cpp $(OBJDR)/Vbutterfly.h: $(CORED)/butterfly.v
cd $(CORED)/; verilator -cc butterfly.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) butterfly.v
$(OBJDR)/Vbutterfly__ALL.a: $(OBJDR)/Vbutterfly.h
$(OBJDR)/Vbutterfly__ALL.a: $(OBJDR)/Vbutterfly.cpp
cd $(OBJDR)/; make -f Vbutterfly.mk
114,7 → 123,7
 
$(CORED)/hwbfly.v: fft
$(OBJDR)/Vhwbfly.cpp $(OBJDR)/Vhwbfly.h: $(CORED)/hwbfly.v
cd $(CORED)/; verilator -cc hwbfly.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) hwbfly.v
$(OBJDR)/Vhwbfly__ALL.a: $(OBJDR)/Vhwbfly.h
$(OBJDR)/Vhwbfly__ALL.a: $(OBJDR)/Vhwbfly.cpp
cd $(OBJDR)/; make -f Vhwbfly.mk
124,7 → 133,7
 
$(CORED)/dblreverse.v: fft
$(OBJDR)/Vdblreverse.cpp $(OBJDR)/Vdblreverse.h: $(CORED)/dblreverse.v
cd $(CORED)/; verilator -cc dblreverse.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) dblreverse.v
$(OBJDR)/Vdblreverse__ALL.a: $(OBJDR)/Vdblreverse.h
$(OBJDR)/Vdblreverse__ALL.a: $(OBJDR)/Vdblreverse.cpp
cd $(OBJDR)/; make -f Vdblreverse.mk
134,7 → 143,7
 
$(CORED)/qtrstage.v: fft
$(OBJDR)/Vqtrstage.cpp $(OBJDR)/Vqtrstage.h: $(CORED)/qtrstage.v
cd $(CORED)/; verilator -cc qtrstage.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) qtrstage.v
$(OBJDR)/Vqtrstage__ALL.a: $(OBJDR)/Vqtrstage.h
$(OBJDR)/Vqtrstage__ALL.a: $(OBJDR)/Vqtrstage.cpp
cd $(OBJDR)/; make -f Vqtrstage.mk
144,7 → 153,7
 
$(CORED)/dblstage.v: fft
$(OBJDR)/Vdblstage.cpp $(OBJDR)/Vdblstage.h: $(CORED)/dblstage.v
cd $(CORED)/; verilator -cc dblstage.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) dblstage.v
$(OBJDR)/Vdblstage__ALL.a: $(OBJDR)/Vdblstage.h
$(OBJDR)/Vdblstage__ALL.a: $(OBJDR)/Vdblstage.cpp
cd $(OBJDR)/; make -f Vdblstage.mk
154,7 → 163,7
 
$(CORED)/fftstage_o2048.v: fft
$(OBJDR)/Vfftstage_o2048.cpp $(OBJDR)/Vfftstage_o2048.h: $(CORED)/fftstage_o2048.v
cd $(CORED)/; verilator -cc fftstage_o2048.v
cd $(CORED)/; $(VERILATOR) $(VFLAGS) fftstage_o2048.v
$(OBJDR)/Vfftstage_o2048__ALL.a: $(OBJDR)/Vfftstage_o2048.h
$(OBJDR)/Vfftstage_o2048__ALL.a: $(OBJDR)/Vfftstage_o2048.cpp
cd $(OBJDR)/; make -f Vfftstage_o2048.mk
/dblclockfft/trunk/sw/fftgen.cpp
247,6 → 247,7
prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module truncate(i_clk, i_ce, i_val, o_val);\n"
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
288,6 → 289,7
prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module roundhalfup(i_clk, i_ce, i_val, o_val);\n"
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
320,7 → 322,7
"\t\talways @(posedge i_clk)\n"
"\t\t\tif (i_ce)\n"
"\t\t\tbegin\n"
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
"\t\t\t\t\to_val <= truncated_value;\n"
"\t\t\t\telse\n"
"\t\t\t\t\to_val <= rounded_up; // even value\n"
366,6 → 368,7
prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module roundfromzero(i_clk, i_ce, i_val, o_val);\n"
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
410,7 → 413,7
"\t\talways @(posedge i_clk)\n"
"\t\t\tif (i_ce)\n"
"\t\t\tbegin\n"
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
"\t\t\t\t\to_val <= truncated_value;\n"
"\t\t\t\telse if (sign_bit)\n"
"\t\t\t\t\to_val <= truncated_value;\n"
433,7 → 436,7
"\t\talways @(posedge i_clk)\n"
"\t\t\tif (i_ce)\n"
"\t\t\tbegin\n"
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
"\t\t\t\t\to_val <= truncated_value;\n"
"\t\t\t\telse if (|other_lost_bits) // Round up to\n"
"\t\t\t\t\to_val <= rounded_up; // closest value\n"
475,6 → 478,7
prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module convround(i_clk, i_ce, i_val, o_val);\n"
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
524,7 → 528,7
"\t\talways @(posedge i_clk)\n"
"\t\t\tif (i_ce)\n"
"\t\t\tbegin\n"
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
"\t\t\t\t\to_val <= truncated_value;\n"
"\t\t\t\telse if (last_valid_bit)// Round up to nearest\n"
"\t\t\t\t\to_val <= rounded_up; // even value\n"
547,7 → 551,7
"\t\talways @(posedge i_clk)\n"
"\t\t\tif (i_ce)\n"
"\t\t\tbegin\n"
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
"\t\t\t\t\to_val <= truncated_value;\n"
"\t\t\t\telse if (|other_lost_bits) // Round up to\n"
"\t\t\t\t\to_val <= rounded_up; // closest value\n"
596,6 → 600,7
"//\n",
(dbg)?"_dbg":"", prjname, creator);
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
 
fprintf(fp,
"module\tqtrstage%s(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync%s);\n"
676,7 → 681,7
"\t\tbegin\n"
"\t\t\twait_for_sync <= 1\'b1;\n"
"\t\t\tiaddr <= 0;\n"
"\t\tend else if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
"\t\tend else if ((i_ce)&&((!wait_for_sync)||(i_sync)))\n"
"\t\tbegin\n"
"\t\t\tiaddr <= iaddr + { {(LGWIDTH-1){1\'b0}}, 1\'b1 };\n"
"\t\t\twait_for_sync <= 1\'b0;\n"
811,6 → 816,7
"//\n", (dbg)?"_dbg":"", prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module\tdblstage%s(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync%s);\n"
"\tparameter\tIWIDTH=%d,OWIDTH=IWIDTH+1, SHIFT=%d;\n"
957,6 → 963,7
"//\n", prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module shiftaddmpy(i_clk, i_ce, i_a, i_b, o_r);\n"
"\tparameter\tAWIDTH=%d,BWIDTH=", TST_SHIFTADDMPY_AW);
1059,6 → 1066,7
"//\n", fname, prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module bimpy(i_clk, i_ce, i_a, i_b, o_r);\n"
"\tparameter\tBW=18, // Number of bits in i_b\n"
1114,6 → 1122,7
"//\n", fname, prjname, creator);
 
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module longbimpy(i_clk, i_ce, i_a, i_b, o_r);\n"
"\tparameter AW=%d, // The width of i_a, min width is 5\n"
1228,6 → 1237,14
"\t\tif (i_ce)\n"
"\t\t\to_r <= w_r[(AW+BW-1):0];\n"
"\n"
"\tgenerate if (IW > AW)\n"
"\tbegin : VUNUSED\n"
"\t\t// verilator lint_off UNUSED\n"
"\t\twire\t[(IW-AW)-1:0]\tunused;\n"
"\t\tassign\tunused = w_r[(IW+BW-1):(AW+BW)];\n"
"\t\t// verilator lint_on UNUSED\n"
"\tend endgenerate\n"
"\n"
"endmodule\n");
 
fclose(fp);
1276,6 → 1293,7
"//\n%s"
"//\n", prjname, creator);
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"\n\n"
"//\n"
1479,6 → 1497,7
"//\n%s"
"//\n", prjname, creator);
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
 
fprintf(fp,
"module\tbutterfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
1512,10 → 1531,7
"\n", lgdelay(16,xtracbits), bflydelay(16, xtracbits),
lgdelay(16,xtracbits));
fprintf(fp,
"\twire\t[(OWIDTH-1):0] o_left_r, o_left_i, o_right_r, o_right_i;\n"
"\n"
"\treg\t[(2*IWIDTH-1):0]\tr_left, r_right;\n"
"\treg\t\t\t\tr_aux, r_aux_2;\n"
"\treg\t[(2*CWIDTH-1):0]\tr_coef, r_coef_2;\n"
"\twire\tsigned\t[(IWIDTH-1):0]\tr_left_r, r_left_i, r_right_r, r_right_i;\n"
"\tassign\tr_left_r = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
1660,8 → 1676,6
"\tassign\tfifo_i = { {2{fifo_read[(IWIDTH+1)-1]}}, fifo_read[((IWIDTH+1)-1):0], {(CWIDTH-2){1\'b0}} };\n"
"\n"
"\n"
"\treg\tsigned\t[(OWIDTH-1):0] b_left_r, b_left_i,\n"
"\t\t\t\t\t\tb_right_r, b_right_i;\n"
"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
"\n");
fprintf(fp,
1719,12 → 1733,6
"\t\t\t// extra bits we need to get rid of.)\n"
"\t\t\tmpy_r <= p_one - p_two;\n"
"\t\t\tmpy_i <= p_three - p_one - p_two;\n"
"\n"
"\t\t\t// Second clock, round and latch for final clock\n"
"\t\t\tb_right_r <= rnd_right_r;\n"
"\t\t\tb_right_i <= rnd_right_i;\n"
"\t\t\tb_left_r <= rnd_left_r;\n"
"\t\t\tb_left_i <= rnd_left_i;\n"
"\t\tend\n"
"\n");
 
1789,15 → 1797,16
"//\n"
"// Purpose: This routine is identical to the butterfly.v routine found\n"
"// in 'butterfly.v', save only that it uses the verilog \n"
"// operator '*' in hopes that the synthesizer would be able\n"
"// to optimize it with hardware resources.\n"
"// operator '*' in hopes that the synthesizer would be able to optimize\n"
"// it with hardware resources.\n"
"//\n"
"// It is understood that a hardware multiply can complete its\n"
"// operation in a single clock.\n"
"// It is understood that a hardware multiply can complete its operation in\n"
"// a single clock.\n"
"//\n"
"//\n%s"
"//\n", prjname, creator);
fprintf(fp, "%s", cpyleft);
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fp,
"module hwbfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
"\t\to_left, o_right, o_aux);\n"
1813,11 → 1822,9
"\toutput\treg\to_aux;\n"
"\n", xtracbits);
fprintf(fp,
"\twire\t[(OWIDTH-1):0] o_left_r, o_left_i, o_right_r, o_right_i;\n"
"\n"
"\treg\t[(2*IWIDTH-1):0] r_left, r_right;\n"
"\treg\t r_aux, r_aux_2;\n"
"\treg\t[(2*CWIDTH-1):0] r_coef, r_coef_2;\n"
"\treg\t[(2*CWIDTH-1):0] r_coef;\n"
"\twire signed [(IWIDTH-1):0] r_left_r, r_left_i, r_right_r, r_right_i;\n"
"\tassign\tr_left_r = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
"\tassign\tr_left_i = r_left[ (IWIDTH-1):0];\n"
2029,6 → 2036,7
"//\n",
(inv)?"i":"", (odd)?'o':'e', stage*2, (dbg)?"_dbg":"", prjname, creator);
fprintf(fstage, "%s", cpyleft);
fprintf(fstage, "//\n//\n`default_nettype\tnone\n//\n");
fprintf(fstage, "module\t%sfftstage_%c%d%s(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync%s);\n",
(inv)?"i":"", (odd)?'o':'e', stage*2, (dbg)?"_dbg":"",
(dbg)?", o_dbg":"");
2140,7 → 2148,7
"\t\t\twait_for_sync <= 1\'b1;\n"
"\t\t\tiaddr <= 0;\n"
"\t\tend\n"
"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
"\t\telse if ((i_ce)&&((!wait_for_sync)||(i_sync)))\n"
"\t\tbegin\n"
"\t\t\t//\n"
"\t\t\t// First step: Record what we\'re not ready to use yet\n"
2149,7 → 2157,7
"\t\t\twait_for_sync <= 1\'b0;\n"
"\t\tend\n"
"\talways @(posedge i_clk) // Need to make certain here that we don\'t read\n"
"\t\tif ((i_ce)&&(~iaddr[LGSPAN])) // and write the same address on\n"
"\t\tif ((i_ce)&&(!iaddr[LGSPAN])) // and write the same address on\n"
"\t\t\timem[iaddr[(LGSPAN-1):0]] <= i_data; // the same clk\n"
"\n");
 
2209,10 → 2217,10
"\t\t\tb_started <= 0;\n"
"\t\tend else if (i_ce)\n"
"\t\tbegin\n"
"\t\t\to_sync <= (~oB[LGSPAN])?ob_sync : 1\'b0;\n"
"\t\t\to_sync <= (!oB[LGSPAN])?ob_sync : 1\'b0;\n"
"\t\t\tif (ob_sync||b_started)\n"
"\t\t\t\toB <= oB + { {(LGSPAN){1\'b0}}, 1\'b1 };\n"
"\t\t\tif ((ob_sync)&&(~oB[LGSPAN]))\n"
"\t\t\tif ((ob_sync)&&(!oB[LGSPAN]))\n"
"\t\t\t// A butterfly output is available\n"
"\t\t\t\tb_started <= 1\'b1;\n"
"\t\tend\n\n");
2232,7 → 2240,7
fprintf(fstage,
"\talways @(posedge i_clk)\n"
"\t\tif (i_ce)\n"
"\t\t\to_data <= (~oB[LGSPAN])?ob_a : omem[oB[(LGSPAN-1):0]];\n"
"\t\t\to_data <= (!oB[LGSPAN])?ob_a : omem[oB[(LGSPAN-1):0]];\n"
"\n");
fprintf(fstage, "endmodule\n");
}
2694,6 → 2702,7
fprintf(vmain, "%s", creator);
fprintf(vmain, "//\n");
fprintf(vmain, "%s", cpyleft);
fprintf(vmain, "//\n//\n`default_nettype\tnone\n//\n");
 
 
fprintf(vmain, "//\n");
2729,7 → 2738,7
}
fprintf(vmain, "\n\n");
fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_rst, i_ce,\n");
fprintf(vmain, "\t\t\t(~i_rst), i_left, i_right, br_left, br_right);\n");
fprintf(vmain, "\t\t\t(!i_rst), i_left, i_right, br_left, br_right);\n");
fprintf(vmain, "\n\n");
} else {
int nbits = nbitsin, dropbit=0;
2749,7 → 2758,8
if (mpystage)
fprintf(vmain, "\t// A hardware optimized FFT stage\n");
fprintf(vmain, "\n\n");
fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n", fftsize, fftsize);
fprintf(vmain, "\twire\t\tw_s%d;\n", fftsize);
fprintf(vmain, "\t// verilator lint_off UNUSED\n\twire\t\tw_os%d;\n\t// verilator lint_on UNUSED\n", fftsize);
fprintf(vmain, "\twire\t[%d:0]\tw_e%d, w_o%d;\n", 2*(obits+xtrapbits)-1, fftsize, fftsize);
fprintf(vmain, "\t%sfftstage_e%d%s\t#(IWIDTH,IWIDTH+%d,%d,%d,%d,%d,0)\tstage_e%d(i_clk, i_rst, i_ce,\n",
(inverse)?"i":"", fftsize,
2757,13 → 2767,13
xtracbits, obits+xtrapbits,
lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
fftsize);
fprintf(vmain, "\t\t\t(~i_rst), i_left, w_e%d, w_s%d%s);\n", fftsize, fftsize, ((dbg)&&(dbgstage == fftsize))?", o_dbg":"");
fprintf(vmain, "\t\t\t(!i_rst), i_left, w_e%d, w_s%d%s);\n", fftsize, fftsize, ((dbg)&&(dbgstage == fftsize))?", o_dbg":"");
fprintf(vmain, "\t%sfftstage_o%d\t#(IWIDTH,IWIDTH+%d,%d,%d,%d,%d,0)\tstage_o%d(i_clk, i_rst, i_ce,\n",
(inverse)?"i":"", fftsize,
xtracbits, obits+xtrapbits,
lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
fftsize);
fprintf(vmain, "\t\t\t(~i_rst), i_right, w_o%d, w_os%d);\n", fftsize, fftsize);
fprintf(vmain, "\t\t\t(!i_rst), i_right, w_o%d, w_os%d);\n", fftsize, fftsize);
fprintf(vmain, "\n\n");
 
 
2806,8 → 2816,10
 
if (mpystage)
fprintf(vmain, "\t// A hardware optimized FFT stage\n");
fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n",
tmp_size, tmp_size);
fprintf(vmain, "\twire\t\tw_s%d;\n",
tmp_size);
fprintf(vmain, "\t// verilator lint_off UNUSED\n\twire\t\tw_os%d;\n\t// verilator lint_on UNUSED\n",
tmp_size);
fprintf(vmain,"\twire\t[%d:0]\tw_e%d, w_o%d;\n",
2*(obits+xtrapbits)-1,
tmp_size, tmp_size);
2876,7 → 2888,8
if ((maxbitsout > 0)&&(obits > maxbitsout))
obits = maxbitsout;
 
fprintf(vmain, "\twire\t\tw_s4, w_os4;\n");
fprintf(vmain, "\twire\t\tw_s4;\n");
fprintf(vmain, "\t// verilator lint_off UNUSED\n\twire\t\tw_os4;\n\t// verilator lint_on UNUSED\n");
fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*(obits+xtrapbits)-1);
fprintf(vmain, "\tqtrstage%s\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
((dbg)&&(dbgstage==4))?"_dbg":"",

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