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URL https://opencores.org/ocsvn/m32632/m32632/trunk

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/m32632/trunk/TRIPUTER/TRIPUTER.qsf
0,0 → 1,309
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 153 11/29/2010 SJ Web Edition
# Date created = 23:26:08 July 09, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TRIPUTER_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY TRIPUTER
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:26:08 JULY 09, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7_H6
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name VERILOG_FILE STEUERUNG.v
set_global_assignment -name VERILOG_FILE SP_FPU.v
set_global_assignment -name VERILOG_FILE DP_FPU.v
set_global_assignment -name VERILOG_FILE DECODER.v
set_global_assignment -name VERILOG_FILE ICACHE.v
set_global_assignment -name VERILOG_FILE DCACHE.v
set_global_assignment -name VERILOG_FILE DATENPFAD.v
set_global_assignment -name VERILOG_FILE M32632.v
set_global_assignment -name VERILOG_FILE ADDR_UNIT.v
set_global_assignment -name VERILOG_FILE I_PFAD.v
set_global_assignment -name VERILOG_FILE ICACHE_SM.v
set_global_assignment -name VERILOG_FILE CACHE_LOGIK.v
set_global_assignment -name VERILOG_FILE ALIGNER.v
set_global_assignment -name VERILOG_FILE TRIPUTER.v
set_global_assignment -name VERILOG_FILE TOP_MISC.v
set_global_assignment -name VERILOG_FILE STEUER_MISC.v
set_global_assignment -name VERILOG_FILE REGISTERS.v
set_location_assignment PIN_D6 -to AUD_XCK
set_location_assignment PIN_Y25 -to HDMI_CLK
set_location_assignment PIN_F7 -to LEDR[0]
set_location_assignment PIN_F6 -to LEDR[1]
set_location_assignment PIN_G6 -to LEDR[2]
set_location_assignment PIN_G7 -to LEDR[3]
set_location_assignment PIN_J8 -to LEDR[4]
set_location_assignment PIN_J7 -to LEDR[5]
set_location_assignment PIN_K10 -to LEDR[6]
set_location_assignment PIN_K8 -to LEDR[7]
set_location_assignment PIN_H7 -to LEDR[8]
set_location_assignment PIN_J10 -to LEDR[9]
set_location_assignment PIN_L7 -to LEDG[0]
set_location_assignment PIN_K6 -to LEDG[1]
set_location_assignment PIN_D8 -to LEDG[2]
set_location_assignment PIN_E9 -to LEDG[3]
set_location_assignment PIN_A5 -to LEDG[4]
set_location_assignment PIN_B6 -to LEDG[5]
set_location_assignment PIN_H8 -to LEDG[6]
set_location_assignment PIN_H9 -to LEDG[7]
set_location_assignment PIN_AA18 -to HEXM[0]
set_location_assignment PIN_AD26 -to HEXM[1]
set_location_assignment PIN_AB19 -to HEXM[2]
set_location_assignment PIN_AE26 -to HEXM[3]
set_location_assignment PIN_AE25 -to HEXM[4]
set_location_assignment PIN_AC19 -to HEXM[5]
set_location_assignment PIN_AF24 -to HEXM[6]
set_location_assignment PIN_V19 -to HEXL[0]
set_location_assignment PIN_V18 -to HEXL[1]
set_location_assignment PIN_V17 -to HEXL[2]
set_location_assignment PIN_W18 -to HEXL[3]
set_location_assignment PIN_Y20 -to HEXL[4]
set_location_assignment PIN_Y19 -to HEXL[5]
set_location_assignment PIN_Y18 -to HEXL[6]
set_location_assignment PIN_AB24 -to RST_N
set_location_assignment PIN_AE19 -to SSW[9]
set_location_assignment PIN_Y11 -to SSW[8]
set_location_assignment PIN_AC9 -to SSW[0]
set_location_assignment PIN_AE10 -to SSW[1]
set_location_assignment PIN_AD13 -to SSW[2]
set_location_assignment PIN_AC8 -to SSW[3]
set_location_assignment PIN_W11 -to SSW[4]
set_location_assignment PIN_AB10 -to SSW[5]
set_location_assignment PIN_V10 -to SSW[6]
set_location_assignment PIN_AC10 -to SSW[7]
set_location_assignment PIN_R20 -to RCLK
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[0]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[1]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[2]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[3]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[4]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[5]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[6]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[7]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[8]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[9]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[10]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[11]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[12]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[13]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[14]"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to "SRAM:SRAMIF|di_reg[15]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRCO[0]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRCO[1]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRCO[2]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRCO[3]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRCO[4]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[0]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[1]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[2]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[3]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[4]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[5]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[6]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[7]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[8]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[9]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[10]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[11]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[12]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[13]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[14]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[15]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[16]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|SRAA[17]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[0]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[1]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[2]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[3]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[4]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[5]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[6]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[7]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[8]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[9]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[10]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[11]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[12]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[13]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[14]"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "SRAM:SRAMIF|do_reg[15]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[0]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[1]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[2]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[3]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[4]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[5]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[6]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[7]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[8]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[9]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[10]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[11]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[12]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[13]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[14]"
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to "SRAM:SRAMIF|oe_reg[15]"
set_location_assignment PIN_M24 -to SRAA[17]
set_location_assignment PIN_N24 -to SRAA[16]
set_location_assignment PIN_J26 -to SRAA[15]
set_location_assignment PIN_J25 -to SRAA[14]
set_location_assignment PIN_F22 -to SRAA[13]
set_location_assignment PIN_E21 -to SRAA[12]
set_location_assignment PIN_F21 -to SRAA[11]
set_location_assignment PIN_G20 -to SRAA[10]
set_location_assignment PIN_E23 -to SRAA[9]
set_location_assignment PIN_D22 -to SRAA[8]
set_location_assignment PIN_J21 -to SRAA[7]
set_location_assignment PIN_J20 -to SRAA[6]
set_location_assignment PIN_C25 -to SRAA[5]
set_location_assignment PIN_D25 -to SRAA[4]
set_location_assignment PIN_H20 -to SRAA[3]
set_location_assignment PIN_H19 -to SRAA[2]
set_location_assignment PIN_B26 -to SRAA[1]
set_location_assignment PIN_B25 -to SRAA[0]
set_location_assignment PIN_N23 -to SRCO[4]
set_location_assignment PIN_M22 -to SRCO[3]
set_location_assignment PIN_G25 -to SRCO[2]
set_location_assignment PIN_M25 -to SRCO[1]
set_location_assignment PIN_H25 -to SRCO[0]
set_location_assignment PIN_K21 -to SRDB[15]
set_location_assignment PIN_L22 -to SRDB[14]
set_location_assignment PIN_G22 -to SRDB[13]
set_location_assignment PIN_F23 -to SRDB[12]
set_location_assignment PIN_J23 -to SRDB[11]
set_location_assignment PIN_H22 -to SRDB[10]
set_location_assignment PIN_H24 -to SRDB[9]
set_location_assignment PIN_H23 -to SRDB[8]
set_location_assignment PIN_L24 -to SRDB[7]
set_location_assignment PIN_L23 -to SRDB[6]
set_location_assignment PIN_G24 -to SRDB[5]
set_location_assignment PIN_F24 -to SRDB[4]
set_location_assignment PIN_K23 -to SRDB[3]
set_location_assignment PIN_K24 -to SRDB[2]
set_location_assignment PIN_E25 -to SRDB[1]
set_location_assignment PIN_E24 -to SRDB[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRDB[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRDB[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRCO[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRCO[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRCO[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRCO[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRCO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRCO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRCO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRCO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRCO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRCO[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[16]
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to SRAA[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SRAA[17]
set_location_assignment PIN_L9 -to UA_TX
set_location_assignment PIN_M9 -to UA_RX
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/m32632/trunk/TRIPUTER/TRIPUTER.qws Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/m32632/trunk/TRIPUTER/TRIPUTER.qws
m32632/trunk/TRIPUTER/TRIPUTER.qws Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: m32632/trunk/TRIPUTER/TRIPUTER.sdc =================================================================== --- m32632/trunk/TRIPUTER/TRIPUTER.sdc (nonexistent) +++ m32632/trunk/TRIPUTER/TRIPUTER.sdc (revision 35) @@ -0,0 +1,110 @@ +## Copyright (C) 1991-2008 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition" + +## DATE "Mon Mar 08 15:49:34 2010" + +## +## DEVICE "EP4CE22F17C6" +## + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clock_ref} -period 20.000 -waveform { 0.000 10.000 } [get_ports {RCLK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + +#derive_pll_clocks +#create_generated_clock -name {clock_mclk} -source [get_ports {CLK}] -divide_by 1 -multiply_by 4 [get_pins {MPLL|altpll_component|auto_generated|pll1|clk[0]}] + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty 0.1 -to clock_ref + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -clock clock_ref 5 [get_ports {RST_N}] +set_input_delay -clock clock_ref 5 [get_ports {SSW[*}] +set_input_delay -clock clock_ref 5 [get_ports {UA_RX}] +set_input_delay -clock clock_ref 5 [get_ports {SRDB[*}] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock clock_ref 5 [get_ports {UA_TX}] +set_output_delay -clock clock_ref 5 [get_ports {SRAA[*}] +set_output_delay -clock clock_ref 5 [get_ports SRCO[4]] +set_output_delay -clock clock_ref 5 [get_ports SRCO[3]] +set_output_delay -clock clock_ref 5 -clock_fall [get_ports SRCO[2]] +set_output_delay -clock clock_ref 5 [get_ports SRCO[1]] +set_output_delay -clock clock_ref 5 [get_ports SRCO[0]] +set_output_delay -clock clock_ref 5 [get_ports {SRDB[*}] +set_output_delay -clock clock_ref 5 [get_ports {HEX*}] +set_output_delay -clock clock_ref 5 [get_ports {LED*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + + +#************************************************************** +# Set False Path +#************************************************************** + +# Control Signals from one clock domain to another clock domain + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + +#************************************************************** +# Set Input Transition +#************************************************************** + Index: m32632/trunk/TRIPUTER/TRIPUTER.sof.zip =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: m32632/trunk/TRIPUTER/TRIPUTER.sof.zip =================================================================== --- m32632/trunk/TRIPUTER/TRIPUTER.sof.zip (nonexistent) +++ m32632/trunk/TRIPUTER/TRIPUTER.sof.zip (revision 35)
m32632/trunk/TRIPUTER/TRIPUTER.sof.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: m32632/trunk/TRIPUTER/TRIPUTER.v =================================================================== --- m32632/trunk/TRIPUTER/TRIPUTER.v (nonexistent) +++ m32632/trunk/TRIPUTER/TRIPUTER.v (revision 35) @@ -0,0 +1,682 @@ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// Version: 0.1 +// Date: 2 December 2018 +// +// Modules contained in this file: +// 1. DRAM_MOD DRAM Model +// 2. MAINDEC Main Decoder +// 3. UART Universal Asynchronous Receiver & Transmitter +// 4. SRAM External SRAM Interface +// 5. TRIPUTER Top level of FPGA +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// 1. DRAM_MOD DRAM Model +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +module DRAM_MOD ( MCLK, RST_N, IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI, + IC_MDONE, DC_MDONE, ENWR, IC_INHIBIT, DC_INHIBIT, MEM_Q ); + + input MCLK; + input RST_N; + input IC_ACC; + input [28:0] IDRAM_ADR; + input DC_ACC; + input DC_WR; + input [28:0] DRAM_ADR; + input [35:0] DRAM_DI; + + output reg IC_MDONE; + output reg DC_MDONE; + output ENWR; + output reg IC_INHIBIT; + output reg DC_INHIBIT; + + output reg [127:0] MEM_Q; + +// +++++++++++++++++++ Memories ++++++++++++++++++++ + + parameter addr_msb = 16; // total memory is 128 kB + + reg [7:0] EDRAM_F [0:2**(addr_msb-3)-1]; // Byte-wide RAM blocks + reg [7:0] EDRAM_E [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_D [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_C [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_B [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_A [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_9 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_8 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_7 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_6 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_5 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_4 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_3 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_2 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_1 [0:2**(addr_msb-3)-1]; + reg [7:0] EDRAM_0 [0:2**(addr_msb-3)-1]; + + wire [15:0] wrbyte; + wire [addr_msb:4] addr; + wire dc_active; + +// +++++++++++++++++++++++++ Datapath +++++++++++++++++++ + + assign dc_active = DC_WR | (DC_ACC & ~DC_MDONE); + + assign addr = dc_active ? DRAM_ADR[addr_msb:4] : IDRAM_ADR[addr_msb:4]; + + always @(posedge MCLK) + begin + MEM_Q[127:120] <= EDRAM_F[addr]; // READ on rising edge + MEM_Q[119:112] <= EDRAM_E[addr]; + MEM_Q[111:104] <= EDRAM_D[addr]; + MEM_Q[103:96] <= EDRAM_C[addr]; + MEM_Q[95:88] <= EDRAM_B[addr]; + MEM_Q[87:80] <= EDRAM_A[addr]; + MEM_Q[79:72] <= EDRAM_9[addr]; + MEM_Q[71:64] <= EDRAM_8[addr]; + MEM_Q[63:56] <= EDRAM_7[addr]; + MEM_Q[55:48] <= EDRAM_6[addr]; + MEM_Q[47:40] <= EDRAM_5[addr]; + MEM_Q[39:32] <= EDRAM_4[addr]; + MEM_Q[31:24] <= EDRAM_3[addr]; + MEM_Q[23:16] <= EDRAM_2[addr]; + MEM_Q[15:8] <= EDRAM_1[addr]; + MEM_Q[7:0] <= EDRAM_0[addr]; + end + + assign wrbyte[0] = DC_WR & DRAM_DI[32] & (DRAM_ADR[3:2] == 2'b00); + assign wrbyte[1] = DC_WR & DRAM_DI[33] & (DRAM_ADR[3:2] == 2'b00); + assign wrbyte[2] = DC_WR & DRAM_DI[34] & (DRAM_ADR[3:2] == 2'b00); + assign wrbyte[3] = DC_WR & DRAM_DI[35] & (DRAM_ADR[3:2] == 2'b00); + assign wrbyte[4] = DC_WR & DRAM_DI[32] & (DRAM_ADR[3:2] == 2'b01); + assign wrbyte[5] = DC_WR & DRAM_DI[33] & (DRAM_ADR[3:2] == 2'b01); + assign wrbyte[6] = DC_WR & DRAM_DI[34] & (DRAM_ADR[3:2] == 2'b01); + assign wrbyte[7] = DC_WR & DRAM_DI[35] & (DRAM_ADR[3:2] == 2'b01); + assign wrbyte[8] = DC_WR & DRAM_DI[32] & (DRAM_ADR[3:2] == 2'b10); + assign wrbyte[9] = DC_WR & DRAM_DI[33] & (DRAM_ADR[3:2] == 2'b10); + assign wrbyte[10] = DC_WR & DRAM_DI[34] & (DRAM_ADR[3:2] == 2'b10); + assign wrbyte[11] = DC_WR & DRAM_DI[35] & (DRAM_ADR[3:2] == 2'b10); + assign wrbyte[12] = DC_WR & DRAM_DI[32] & (DRAM_ADR[3:2] == 2'b11); + assign wrbyte[13] = DC_WR & DRAM_DI[33] & (DRAM_ADR[3:2] == 2'b11); + assign wrbyte[14] = DC_WR & DRAM_DI[34] & (DRAM_ADR[3:2] == 2'b11); + assign wrbyte[15] = DC_WR & DRAM_DI[35] & (DRAM_ADR[3:2] == 2'b11); + + always @(posedge MCLK) + begin + if (wrbyte[15]) EDRAM_F[addr] <= DRAM_DI[31:24]; // WRITE on rising edge + if (wrbyte[14]) EDRAM_E[addr] <= DRAM_DI[23:16]; + if (wrbyte[13]) EDRAM_D[addr] <= DRAM_DI[15:8]; + if (wrbyte[12]) EDRAM_C[addr] <= DRAM_DI[7:0]; + if (wrbyte[11]) EDRAM_B[addr] <= DRAM_DI[31:24]; // WRITE on rising edge + if (wrbyte[10]) EDRAM_A[addr] <= DRAM_DI[23:16]; + if (wrbyte[9]) EDRAM_9[addr] <= DRAM_DI[15:8]; + if (wrbyte[8]) EDRAM_8[addr] <= DRAM_DI[7:0]; + if (wrbyte[7]) EDRAM_7[addr] <= DRAM_DI[31:24]; // WRITE on rising edge + if (wrbyte[6]) EDRAM_6[addr] <= DRAM_DI[23:16]; + if (wrbyte[5]) EDRAM_5[addr] <= DRAM_DI[15:8]; + if (wrbyte[4]) EDRAM_4[addr] <= DRAM_DI[7:0]; + if (wrbyte[3]) EDRAM_3[addr] <= DRAM_DI[31:24]; // WRITE on rising edge + if (wrbyte[2]) EDRAM_2[addr] <= DRAM_DI[23:16]; + if (wrbyte[1]) EDRAM_1[addr] <= DRAM_DI[15:8]; + if (wrbyte[0]) EDRAM_0[addr] <= DRAM_DI[7:0]; + end + +// +++++++++++++++++++++++++ Controllogic +++++++++++++++++++ + + // each access takes one clock cycle inside the DRAM model. Due to the timing requirement of xx_MDONE the read + // access is pipelined: it will take two clock cycles to serve a cache read request + + always @(posedge MCLK) DC_MDONE <= DC_ACC & ~DC_MDONE & ~DC_WR; + + always @(posedge MCLK) IC_MDONE <= IC_ACC & ~IC_MDONE & ~dc_active; + + always @(posedge MCLK) DC_INHIBIT <= ~DRAM_ADR[1]; // ~USE_CA => INHIBIT + + always @(posedge MCLK) IC_INHIBIT <= ~IDRAM_ADR[1]; // ~USE_CA => INHIBIT + + assign ENWR = 1'b1; // always active + +endmodule + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// 2. MAINDEC Main Decoder +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +module MAINDEC + (BCLK, RST_N, WRITE, READ, STATUS, SRAM_RDY, ADDR, BOOT_Q, SRAM_Q, UART_Q, BE, IO_DI, + UART_RD, UART_WR, CESRAM, NMI_N, DRD, READY, BRESET, ENDRAM, LEDR, LEDG, HEXL, HEXM, SSW ); + + input BCLK; + input RST_N; + input WRITE; + input READ; + input [3:0] STATUS; + input SRAM_RDY; + input [31:2] ADDR; + input [31:0] BOOT_Q; + input [31:0] SRAM_Q; + input [3:0] BE; + input [31:0] IO_DI; + + output UART_RD; + output [1:0] UART_WR; + + input [31:0] UART_Q; + output CESRAM; + + output reg NMI_N; + + output [31:0] DRD; + output reg READY; + output reg BRESET; + output reg ENDRAM; + + input [9:0] SSW; + + output reg [6:0] HEXL,HEXM; + output reg [9:0] LEDR; + output reg [7:0] LEDG; + + reg [31:0] DRD; + reg rd_rdy; + reg [3:0] init_cou; + reg [25:0] counter; + reg [9:0] ssw_reg; + reg nmie; + + wire wr_leds,wr_coun; + wire access; + + assign access = WRITE | READ; + + assign UART_WR = (WRITE & (ADDR[31:20] == 12'h202)) ? BE[1:0] : 2'd0; + assign UART_RD = READ & (ADDR[31:20] == 12'h202) & BE[0]; // Read Data Reg. -> Int to 0 + assign CESRAM = access & (ADDR[31:20] == 12'h201); + assign wr_coun = WRITE & (ADDR[31:20] == 12'h205) & ADDR[2]; + + assign wr_leds = WRITE & (ADDR[31:20] == 12'h204); + + always @(posedge BCLK) if (wr_leds && ADDR[2] && BE[1]) HEXM <= IO_DI[14:8]; + always @(posedge BCLK) if (wr_leds && ADDR[2] && BE[0]) HEXL <= IO_DI[6:0]; + always @(posedge BCLK) if (wr_leds && !ADDR[2] && BE[2]) LEDG <= IO_DI[23:16]; + always @(posedge BCLK) if (wr_leds && !ADDR[2] && BE[1]) LEDR[9:8] <= IO_DI[9:8]; + always @(posedge BCLK) if (wr_leds && !ADDR[2] && BE[0]) LEDR[7:0] <= IO_DI[7:0]; + + always @(posedge BCLK) ssw_reg <= SSW; + + always @(posedge BCLK) rd_rdy <= READ & ((ADDR[31:20] == 12'h200) | (ADDR[31:29] == 3'd0)) & ~rd_rdy; + + always @(access or ADDR or WRITE or rd_rdy or SRAM_RDY) + casex({access,ADDR[31:20]}) + 13'b1_000x_xxxx_xxxx : READY = rd_rdy; // if DRAM not activ + 13'b1_0010_xxxx_0000 : READY = rd_rdy; // Boot-ROM + 13'b1_0010_xxxx_0001 : READY = SRAM_RDY; + default : READY = access; // else only one clock !!! + endcase + + always @(ADDR or BOOT_Q or SRAM_Q or UART_Q or ssw_reg or counter or nmie) + casex({ADDR[31:20]}) + 12'h201 : DRD = SRAM_Q; + 12'h202 : DRD = UART_Q; + 12'h203 : DRD = {22'd0,ssw_reg[9:0]}; + 12'h205 : DRD = {(ADDR[2] ? nmie : 1'd0),5'd0,counter}; + default : DRD = BOOT_Q; // Boot-ROM + endcase + + // Program access in higher ROM area switches DRAM on + always @(posedge BCLK) ENDRAM <= (((ADDR[31:28] == 4'h2) & (STATUS == 4'h8) & READ) | ENDRAM) & BRESET; + + // ++++++++++++++++++++++++++ NMI Counter ++++++++++++++++++++++++++ + + always @(posedge BCLK) + if (!BRESET) counter <= 26'd0; + else counter <= (counter == 26'h2FA_F07F) ? 26'd0 : counter + 26'd1; // 50.000.000 = 2FA_F080 + + always @(posedge BCLK) NMI_N <= ~((counter[25:4] == 22'h2FA_F07) & nmie); // once per second + + always @(posedge BCLK or negedge BRESET) // NMI Enable + if (!BRESET) nmie <= 1'b0; + else if (wr_coun) nmie <= IO_DI[31]; // is SET able + + // ++++++++++++++++++++++++++ RESET Signal ++++++++++++++++++++++++++ + + always @(posedge BCLK or negedge RST_N) + if (!RST_N) init_cou <= 4'h0; + else init_cou <= init_cou + 4'h1; + + always @(posedge BCLK or negedge RST_N) + if (!RST_N) BRESET <= 1'b0; + else + if (init_cou == 4'hF) BRESET <= 1'b1; + +endmodule + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// 3. UART Universal Asynchronous Receiver & Transmitter +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +module UART(BCLK, BRESET, UART_RD, UART_WR, DIN, UA_RX, UA_TX, UART_Q, UA_INT); + + input BCLK; + input BRESET; + input UART_RD; + input [1:0] UART_WR; + input [15:0] DIN; + + output UA_TX; + input UA_RX; + + output [31:0] UART_Q; + output UA_INT; + + reg [1:0] iena; // Interrupt enable + + parameter baudrate = 10'd867; // 57600 Baud : 868 clocks of 20ns + + // +++++++++++++++++++++++++++++++ Transmitter +++++++++++++++++++++++++++++++++ + + reg [8:0] shifter_tx; + reg [3:0] txbits; + reg [9:0] txtimer; + reg tx_int; + reg trold; + + wire tx_load,tx_run,tx_shift; + + assign tx_load = UART_WR[0] & ~tx_run; // no Write during transmisson + + always @(posedge BCLK or negedge BRESET) + if (!BRESET) shifter_tx <= 9'h1FF; + else + if (tx_load) shifter_tx <= {DIN[7:0],1'b0}; + else + if (tx_shift) shifter_tx <= {1'b1,shifter_tx[8:1]}; // LSB first to send + + assign UA_TX = shifter_tx[0]; + + // ---1__2_one_3_two_4_three_5_four_6_five_7_six_8_seven_9_eight_10---11 + always @(posedge BCLK or negedge BRESET) + if (!BRESET) txbits <= 4'd0; + else + if (tx_load) txbits <= 4'd1; + else + if (tx_shift) txbits <= (txbits == 4'd10) ? 4'd0 : txbits + 4'd1; + + assign tx_run = |txbits; + always @(posedge BCLK) trold <= tx_run; + + always @(posedge BCLK) txtimer <= (~tx_run | tx_shift) ? 10'd0 : txtimer + 10'd1; + + assign tx_shift = (txtimer == baudrate); + + always @(posedge BCLK or negedge BRESET) + if (!BRESET) tx_int <= 1'b0; + else + if (tx_load) tx_int <= 1'b0; + else + if (UART_WR[1]) tx_int <= DIN[13]; + else + if (!tx_run && trold) tx_int <= 1'b1; + + // +++++++++++++++++++++++++++++++ Receiver +++++++++++++++++++++++++++++++++ + + reg [2:0] inshift; + reg [3:0] rxbits; + reg [8:0] shifter_rx; + reg [9:0] rxtimer; + reg [7:0] rxhold; + reg inbit,oldin; + reg rx_int; + reg rx_end; + + wire rx_go,rx_shift,rx_run; + + always @(posedge BCLK) inshift <= {inshift[1:0],UA_RX}; + + always @(posedge BCLK) inbit <= (inshift == 3'b111) ? 1'b1 : (inshift == 3'd0) ? 1'b0 : inbit; + + always @(posedge BCLK) oldin <= inbit; + + assign rx_go = ~inbit & oldin & (rxbits == 4'd0); + + // --1_2__3one_4two_5three_6four_7five_8six_9seven_10eight_-11-- + always @(posedge BCLK or negedge BRESET) + if (!BRESET) rxbits <= 4'd0; + else + if (rx_go) rxbits <= 4'd1; + else + if (rx_shift) rxbits <= (((rxbits == 4'd1) & inbit) | (rxbits == 4'd10)) ? 4'd0 : rxbits + 4'd1; + + always @(posedge BCLK) if (rx_shift) shifter_rx <= {inbit,shifter_rx[8:1]}; + + always @(posedge BCLK) rxtimer <= (~rx_run | rx_shift) ? 10'd0 : rxtimer + 10'd1; + + assign rx_shift = (rxtimer == ((rxbits == 4'd1) ? {1'b0,baudrate[9:1]} : baudrate)); + assign rx_run = |rxbits; + + always @(posedge BCLK) rx_end <= rx_shift & (rxbits == 4'd10) & inbit; // Stopbit must be "1" + + always @(posedge BCLK or negedge BRESET) + if (!BRESET) rx_int <= 1'b0; + else + if (UART_RD) rx_int <= 1'b0; + else + if (UART_WR[1]) rx_int <= DIN[10]; + else + if (rx_end) rx_int <= 1'b1; + + always @(posedge BCLK) if (rx_end) rxhold <= shifter_rx[7:0]; // hold received data + + assign UART_Q = {18'd0,tx_int,iena[1],tx_run,rx_int,iena[0],rx_run,rxhold}; + + // +++++++++++++++++++++++++++++++ Interrupt +++++++++++++++++++++++++++++++++ + + always @(posedge BCLK or negedge BRESET) + if (!BRESET) iena <= 2'd0; + else + if (UART_WR[1]) iena <= {DIN[12],DIN[9]}; + + assign UA_INT = (tx_int & iena[1]) | (rx_int & iena[0]); + +endmodule + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// 4. SRAM External SRAM Interface +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +module SRAM (BCLK, BRESET, CESRAM, WRITE, AA, BE, DIN, READY, SRAM_Q, SRCO, SRAA, SRDB); + + input BCLK; + input BRESET; + input CESRAM; + input WRITE; + input [18:1] AA; + input [3:0] BE; + input [31:0] DIN; + + output READY; + output [31:0] SRAM_Q; + + output reg [4:0] SRCO; + output reg [17:0] SRAA; // Word Address + inout [15:0] SRDB; + + reg [15:0] do_reg; + reg [2:0] state; + reg [17:0] save_aa; + reg [1:0] top_be,save_be,muxbe; + reg [15:0] top_do,save_do,muxdo; + reg [15:0] di_reg,pipe_reg; + reg [15:0] oe_reg; + + wire twoa; + wire [17:0] muxadr; + + genvar i; + + assign twoa = (BE[3] | BE[2]) & (BE[1] | BE[0]); // two Accesses + + always @(posedge BCLK or negedge BRESET) + if (!BRESET) state <= 3'd0; + else + casex ({CESRAM,WRITE,twoa,state}) + 6'b0x_x_000 : state <= 3'b000; // nothing to do + 6'b10_1_000 : state <= 3'b001; + 6'b10_0_000 : state <= 3'b010; + 6'b11_1_000 : state <= 3'b100; + 6'b11_0_000 : state <= 3'b110; + // Read + 6'bxx_x_001 : state <= 3'b010; + 6'bxx_x_010 : state <= 3'b011; + 6'bxx_x_011 : state <= 3'b000; // Send READY + // Write + 6'bxx_x_100 : state <= 3'b101; + 6'bxx_x_101 : state <= 3'b110; + 6'bxx_x_110 : state <= 3'b000; // State 7 at WRITE overlaps with State 0 + default : state <= 3'b000; + endcase + + always @(posedge BCLK) save_aa <= muxadr; + + assign muxadr[17:1] = (CESRAM & (state == 3'd0)) ? AA[18:2] : save_aa[17:1]; + assign muxadr[0] = (CESRAM & (state == 3'd0)) ? AA[1] : ( ((state == 3'd1) | (state == 3'd5)) ? 1'b1 : save_aa[0] ); + + always @(posedge BCLK) SRAA <= muxadr; + + always @(posedge BCLK) if (!state[2]) top_be = ~BE[3:2]; + always @(posedge BCLK) save_be <= muxbe; + + always @(*) + casex ({CESRAM,state}) + 4'b0_000 : muxbe = 2'b11; + 4'b1_000 : muxbe = AA[1] ? ~BE[3:2] : ~BE[1:0]; // READ has valid BE's + 4'bx_001 : muxbe = ~BE[3:2]; // READ is still active + 4'bx_101 : muxbe = top_be; + 4'bx_010 : muxbe = 2'b11; // State = 2 is End for READ ! + default : muxbe = save_be; + endcase + + always @(posedge BCLK) SRCO[1:0] <= muxbe; + + always @(posedge BCLK) if (!state[2]) top_do <= DIN[31:16]; + always @(posedge BCLK) save_do <= muxdo; + + always @(*) + casex ({CESRAM,state}) + 4'b1_000 : muxdo = AA[1] ? DIN[31:16] : DIN[15:0]; // READ has valid BE's + 4'bx_101 : muxdo = top_do; + default : muxdo = save_do; + endcase + + always @(posedge BCLK) do_reg <= muxdo; + + // Control Signals + always @(posedge BCLK) SRCO[4] <= ~((CESRAM & (state == 3'd0)) | (state == 3'd1) | (state == 3'd4) | (state == 3'd5) | (state == 3'd6)); // CE + always @(posedge BCLK) SRCO[3] <= ~((CESRAM & ~WRITE & (state == 3'd0)) | (state == 3'd1)); // OE + always @(negedge BCLK) SRCO[2] <= ~((state == 3'd4) | (state == 3'd6)); // WE + + always @(posedge BCLK) oe_reg <= {16{(CESRAM & WRITE & (state == 3'd0)) | (state == 3'd4) | (state == 3'd5) | (state == 3'd6)}}; + + generate + for (i=0;i<=15;i=i+1) + begin: oectrl + assign SRDB[i] = oe_reg[i] ? do_reg[i] : 1'bz; + end + endgenerate + + always @(posedge BCLK) di_reg <= SRDB; // Fast Input Register + always @(posedge BCLK) pipe_reg <= di_reg; + + assign SRAM_Q = {di_reg,(twoa ? pipe_reg : di_reg)}; + assign READY = CESRAM & (WRITE ? (state == 3'd0) : (state == 3'd3)); + +endmodule + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// 5. TRIPUTER Top level of FPGA +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +module TRIPUTER( RCLK, RST_N, SSW, UA_TX, UA_RX, SRCO, SRAA, SRDB, HEXM, HEXL, LEDR, LEDG, AUD_XCK, HDMI_CLK ); + + input RCLK; + input RST_N; + + input [9:0] SSW; + + input UA_RX; + output UA_TX; + + output [4:0] SRCO; + output [17:0] SRAA; + inout [15:0] SRDB; + + output [6:0] HEXM,HEXL; + output [9:0] LEDR; + output [7:0] LEDG; + + output AUD_XCK,HDMI_CLK; // only driving 0 + + reg [31:0] BOOT_ROM [0:511]; // 2 kByte + reg [31:0] BOOT_Q; + + wire [31:0] AA; + wire NMI_N; + wire BCLK; + wire DC_ACC; + wire DC_WR; + wire DC_MDONE; + wire [31:0] DIN; + wire [28:0] DRAM_ADR; + wire [35:0] DRAM_DI; + wire [127:0] DRAM_Q; + wire [31:0] DRD; + wire DC_INHIBIT; + wire IC_ACC; + wire IC_MDONE; + wire [28:0] IDRAM_ADR; + wire IC_INHIBIT; + wire READ; + wire READY; + wire [3:0] STATUS; + wire ENDRAM; + wire ENWR; + wire WRITE; + wire [3:0] BE; + wire CESRAM; + wire [31:0] SRAM_Q; + wire SRAM_RDY; + wire BRESET; + wire INT_N; + wire UART_RD; + wire [1:0] UART_WR; + wire [31:0] UART_Q; + + assign BCLK = RCLK; + assign AUD_XCK = 1'b0; + assign HDMI_CLK = 1'b0; + +M32632 CPU( + .BCLK(BCLK), + .BRESET(BRESET), + .DRAMSZ(3'b010), + .NMI_N(NMI_N), + .INT_N(~INT_N), + .IC_MDONE(IC_MDONE), + .IC_INHIBIT(IC_INHIBIT), + .DRAM_Q(DRAM_Q), + .ENWR(ENWR), + .DC_MDONE(DC_MDONE), + .DC_INHIBIT(DC_INHIBIT), + .ENDRAM(ENDRAM), + .COP_DONE(1'b0), + .COP_IN(64'd0), + .HOLD(1'b1), + .DMA_CHK(1'b0), + .DMA_AA(25'd0), + .IO_READY(READY), + .IO_Q(DRD), +// Outputs: + .STATUS(STATUS), + .ILO(), + .STATSIGS(), + .IC_ACC(IC_ACC), + .IDRAM_ADR(IDRAM_ADR), + .DC_WR(DC_WR), + .DC_ACC(DC_ACC), + .DRAM_ADR(DRAM_ADR), + .DRAM_DI(DRAM_DI), + .COP_GO(), + .COP_OP(), + .COP_OUT(), + .HLDA(), + .IO_RD(READ), + .IO_WR(WRITE), + .IO_A(AA), + .IO_BE(BE), + .IO_DI(DIN) ); + +DRAM_MOD DRAM( + .MCLK(BCLK), + .RST_N(BRESET), + .IC_ACC(IC_ACC), + .IDRAM_ADR(IDRAM_ADR), + .DC_WR(DC_WR), + .DC_ACC(DC_ACC), + .DRAM_ADR(DRAM_ADR), + .DRAM_DI(DRAM_DI), + .IC_MDONE(IC_MDONE), + .IC_INHIBIT(IC_INHIBIT), + .MEM_Q(DRAM_Q), + .ENWR(ENWR), + .DC_MDONE(DC_MDONE), + .DC_INHIBIT(DC_INHIBIT) ); + + +MAINDEC MDEC( + .BCLK(BCLK), + .WRITE(WRITE), + .READ(READ), + .ADDR(AA[31:2]), + .STATUS(STATUS), + .IO_DI(DIN), + .SRAM_RDY(SRAM_RDY), + .SRAM_Q(SRAM_Q), + .BOOT_Q(BOOT_Q), + .UART_Q(UART_Q), + .BE(BE), + .RST_N(RST_N), + .SSW(SSW), + .READY(READY), + .DRD(DRD), + .ENDRAM(ENDRAM), + .BRESET(BRESET), + .LEDR(LEDR), + .LEDG(LEDG), + .HEXM(HEXM), + .HEXL(HEXL), + .NMI_N(NMI_N), + .UART_RD(UART_RD), + .UART_WR(UART_WR), + .CESRAM(CESRAM) ); + +UART SERIF( + .BCLK(BCLK), + .BRESET(BRESET), + .UART_RD(UART_RD), + .UART_WR(UART_WR), + .DIN(DIN[15:0]), + .UART_Q(UART_Q), + .UA_INT(INT_N), + .UA_RX(UA_RX), + .UA_TX(UA_TX) ); + +SRAM SRAMIF( + .BCLK(BCLK), + .BRESET(BRESET), + .CESRAM(CESRAM), + .WRITE(WRITE), + .AA(AA[18:1]), + .DIN(DIN), + .BE(BE), + .SRAM_Q(SRAM_Q), + .READY(SRAM_RDY), + .SRCO(SRCO), + .SRAA(SRAA), + .SRDB(SRDB) ); + +initial + begin + $readmemh("boot_rom.txt", BOOT_ROM); + end + + always @(posedge BCLK) BOOT_Q <= BOOT_ROM[AA[10:2]]; + +endmodule Index: m32632/trunk/TRIPUTER/TRIPUTER_SIMU.v =================================================================== --- m32632/trunk/TRIPUTER/TRIPUTER_SIMU.v (nonexistent) +++ m32632/trunk/TRIPUTER/TRIPUTER_SIMU.v (revision 35) @@ -0,0 +1,90 @@ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// Version: 0.1 +// Date: 2 December 2018 +// +// Modules contained in this file: +// 1. TRIPUTER_SIMU Simulation Model of TRIPUTER +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +`timescale 1ns / 100ps + +module TRIPUTER_SIMU; + +reg RCLK; +reg RST_N; +wire [9:0] SSW; +wire UA_TX; +reg UA_RX; +wire [4:0] SRCO; +wire [17:0] SRAA; +wire [15:0] SRDB; +wire [6:0] HEXM; +wire [6:0] HEXL; +wire [9:0] LEDR; +wire [7:0] LEDG; +wire AUD_XCK; +wire HDMI_CLK; + +TRIPUTER CHIP( + RCLK, + RST_N, + SSW, + UA_TX, + UA_RX, + SRCO, + SRAA, + SRDB, + HEXM, + HEXL, + LEDR, + LEDG, + AUD_XCK, + HDMI_CLK); + + reg [7:0] memh [8191:0]; // 16 KB in total + reg [7:0] meml [8191:0]; + reg [7:0] ramh_q,raml_q; + +initial // Clock generator + begin + RCLK = 0; + #10 forever #10 RCLK = !RCLK; + end + +initial + begin + RST_N = 1'b0; + #105 RST_N = 1'b1; + end + +initial + begin + UA_RX = 1'b1; + #100000 UA_RX = 1'b0; + #17360 UA_RX = 1'b1; + #34720 UA_RX = 1'b0; + #52080 UA_RX = 1'b1; + #17360 UA_RX = 1'b0; + #34720 UA_RX = 1'b1; + end + + assign SSW = 10'd0; + + assign SRDB = SRCO[3] ? 16'hzzzz : {ramh_q,raml_q}; + + always @(posedge SRCO[2]) // WE + begin + if (!SRCO[1]) memh[SRAA[12:0]] <= SRDB[15:8]; + if (!SRCO[0]) meml[SRAA[12:0]] <= SRDB[7:0]; + end + + always @(negedge RCLK) // OE + begin + if (!SRCO[3]) ramh_q <= memh[SRAA[12:0]]; + if (!SRCO[3]) raml_q <= meml[SRAA[12:0]]; + end + +endmodule + Index: m32632/trunk/TRIPUTER/TRIPUTER_V01.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: m32632/trunk/TRIPUTER/TRIPUTER_V01.pdf =================================================================== --- m32632/trunk/TRIPUTER/TRIPUTER_V01.pdf (nonexistent) +++ m32632/trunk/TRIPUTER/TRIPUTER_V01.pdf (revision 35)
m32632/trunk/TRIPUTER/TRIPUTER_V01.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: m32632/trunk/TRIPUTER/boot_rom.txt =================================================================== --- m32632/trunk/TRIPUTER/boot_rom.txt (nonexistent) +++ m32632/trunk/TRIPUTER/boot_rom.txt (revision 35) @@ -0,0 +1,512 @@ +0020A017 +027F1000 +00000000 +00000000 +4020A057 +485F0000 +00A25700 +04FFFF00 +0000A66F +A4EFF60B +00030000 +0000A76F +DD670003 +04834685 +2020A1D7 +D8270000 +84029784 +D710DD2E +001020A0 +0012D500 +1081190F +771A101D +185D10DD +1A005885 +190F7185 +101D1081 +C4BE741A +714A84DA +84DAC8BE +851A7144 +20A0D75A +97000010 +000200A0 +00585F00 +17CF1A0F +20A0D77B +97000010 +000400A0 +00581D00 +DD34851A +190F005F +D77517CF +001020A0 +00A09700 +9D000004 +851A005F +00585D1A +17CF190F +20A0D775 +97000010 +000400A0 +00581D00 +0F00851A +7817CF19 +EC83D827 +D7948302 +031020A0 +84DAE700 +DAE70493 +6F00C684 +20A4EF1F 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+7C069409 +0042C072 +77EA005C +D0170162 +D07F1474 +8C008100 +E3D474D0 +C00081D0 +D4000020 +0020C003 +52807202 +69BFD827 +4E9CBE02 +4040A275 +007AEA04 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 Index: m32632/trunk/TRIPUTER/monitor.32K =================================================================== --- m32632/trunk/TRIPUTER/monitor.32K (nonexistent) +++ m32632/trunk/TRIPUTER/monitor.32K (revision 35) @@ -0,0 +1,473 @@ +; MONITOR for TRIPUTER V0.1 +; 27 May 2017 +sramsize .equ x'8000 + + movd x'20000010,r0 + jump r0 + + .align 16 + movd x'20400000,r1 ; address of LEDs + movqd 0,0(r1) ; all went off + movd x'FFFF,4(r1) ; the seven segment went off + lprd cfg,x'BF6 + lprd sp,x'300 + lprd intbase,x'300 + addr nmi,@x'304 + movd x'20200000,r7 ; UART - fix Register + addr welcome,r0 + bsr string +; SRAM-Test : Bit Test + movqw 1,r2 + movd x'20100000,r3 +l01: movw r2,0(r3) ; write + addqd 2,r3 + addw r2,r2 + cmpqw 0,r2 + bne l01 + movqw 1,r2 + movqw 0,r3 +l02: cmpw 0(r3),r2 ; read + bne err + addqd 2,r3 + addw r2,r2 + cmpqw 0,r2 + bne l02 + movl datfp,-15(r3) + cmpl datfp,-15(r3) + bne err +; Address steping + movd x'20100000,r3 + movd x'20000,r2 ; Initialize on 0 +l03: movqd 0,0(r3) + addqd 4,r3 + acbd -1,r2,l03 + movd x'20100000,r3 ; Test of 0 and 1 write + movd x'40000,r2 +l04: cmpqw 0,0(r3) + bne err + movqw -1,0(r3) + addqd 2,r3 + acbd -1,r2,l04 + movd x'20100000,r3 ; Test on 1 and 0 write + movd x'40000,r2 +l05: cmpqw -1,0(r3) + bne err + movqw 0,0(r3) + addqd 2,r3 + acbd -1,r2,l05 + movd x'20100000,r3 ; Test on 0 + movd x'40000,r2 +l06: cmpqw 0,0(r3) + bne err + addqd 2,r3 + acbd -1,r2,l06 + addr sram_ok,r0 + bsr string +; INT vector points to SRAM + movd x'20100300,r3 + addr nmi,4(r3) + addr int,0(r3) + lprd intbase,r3 + lprd sp,x'20100300 + lprd sb,x'20100400 ; working area + movqd 0,-4(sb) ; counter in NMI + sbitb 31,x'300004(r7) ; NMI enable +; iDRAM-Test : Bit Test + movqd 1,r2 + movqd 0,r3 +l21: movd r2,0(r3) ; write + addqd 4,r3 + addd r2,r2 + cmpqd 0,r2 + bne l21 + movqd 1,r2 + movqd 0,r3 +l22: cmpd 0(r3),r2 ; read + bne err + addqd 4,r3 + addd r2,r2 + cmpqd 0,r2 + bne l22 + movl datfp,-15(r3) + cmpl datfp,-15(r3) + bne err +; Address stepping + movqd 0,r3 + movw sramsize,r2 ; Initialize to 0 +l23: movqd 0,0(r3) + addqd 4,r3 + acbw -1,r2,l23 + movqd 0,r3 ; Test on 0 and 1 write + movw sramsize,r2 +l24: cmpqd 0,0(r3) + bne err + movqd -1,0(r3) + addqd 4,r3 + acbw -1,r2,l24 + movqd 0,r3 ; Test on 1 und 0 write + movd sramsize,r2 +l25: cmpqd -1,0(r3) + bne err + movqd 0,0(r3) + addqd 4,r3 + acbw -1,r2,l25 + movqd 0,r3 ; Test on 0 + movw sramsize,r2 +l26: cmpqd 0,0(r3) + bne err + addqd 4,r3 + acbw -1,r2,l26 +; Now all Data right initialize + movd x'300,r0 + lprd sp,r0 + lprd sb,x'400 ; working area + addr int,0(r0) + addr nmi,4(r0) + lprd intbase,r0 + movqd 0,-8(sb) ; readpointer of RX buffer + movqd 0,-12(sb) ; writepointer of RX buffer + movqb 0,-4(sb) ; count byte for NMI + movqd 0,-20(sb) ; pointer for Dump + addr idram_ok,r0 + bsr string + bispsrw x'800 ; Int enable + sbitb 9,0(r7) ; UART RX Int on + addr string,-24(sb) ; save address of string service routine +; *************************************************************** +; Endless loop : wait on Input from UART +; *************************************************************** +new: movd x'20240002,-2(sb) + sprd sb,r0 + bsr string + movqd 0,-16(sb) ; Number of characters in buffer +loop: wait + cmpd -8(sb),-12(sb) ; has the UART something received? + beq loop ; No +; Auswertung + movd -8(sb),r1 + movb x'100(sb)[r1:b],r0 + addqb 1,-8(sb) + checkb r1,cvalid,r0 ; special character ? + bfs sys1 ; Yes + movd -16(sb),r1 + cmpqd 0,r1 + bne sys2 + cmpb '+',r0 + beq sys3 + cmpb '-',r0 + beq sys4 +sys2: movb r0,0(sb)[r1:b] + addr 1(r1),-16(sb) +sys0: bsr out + br loop +sys1: cmpb 8,r0 ; Delete + bne sys5 + cmpqd 0,-16(sb) + beq loop + addqd -1,-16(sb) + bsr out + movb ' ',r0 + bsr out + movb 8,r0 + br sys0 +sys5: cmpb 13,r0 ; CR only output + beq sys0 + cmpb 10,r0 ; LF now analyzing input + bne new +; Analyzing input: + bsr out + sprd sb,r2 + movd -16(sb),r1 ; Number of characters in buffer +sys7: cmpqd 0,r1 + beq new + movb 0(r2),r0 + addqd 1,r2 + addqd -1,r1 + cmpb ' ',r0 + beq sys7 ; next character + bicb x'20,r0 ; only capital letters + movqd 0,r6 + cmpb 'L',r0 ; "Load" + beq sys6 + movqd 1,r6 + cmpb 'R',r0 ; "Run" + beq sys6 + movqd 2,r6 + cmpb 'D',r0 ; "Dump" + beq sys6 + br erin ; Error in input +; now look for ' ' and address input +sys6: cmpqd 0,r1 + beq erin ; no input any more + cmpb ' ',0(r2) + addqd 1,r2 + addqd -1,r1 + bne sys6 +; now look for characters +sys8: cmpqd 0,r1 + beq erin + cmpb ' ',0(r2) + addqd 1,r2 + addqd -1,r1 + beq sys8 +; Addresse build + movqd 0,r4 +sy10: movb -1(r2),r3 + checkb r5,cziff,r3 + bfc sy11 + bicb x'20,r3 + checkb r5,cabc,r3 + bfs erin ; illegal character -> Abort + addb 10,r5 +sy11: ashd 4,r4 + orb r5,r4 + cmpqd 0,r1 + beq sys9 + addqd 1,r2 + addqd -1,r1 + br sy10 +; Now execute ... + .align 4 +sys9: casew sy12[r6:w] +sy12: .word syld-sys9 + .word sygo-sys9 + .word sydu-sys9 +; Program Call +sygo: jsr r4 + movd x'20200000,r7 + br new +; make Dump , R4 is pointer +sys4: subd 512,-20(sb) +sys3: movd -20(sb),r4 + movb 13,r0 ; make CR before + bsr out +sydu: movb 16,r5 ; Number of Lines +sy18: sprd sb,r0 ; Pointer to String + movzbd 28,r1 +sy13: extd r1,r4,r2,4 + movb datah[r2:b],0(r0) + addqd 1,r0 + addqb -4,r1 + cmpqb -4,r1 + bne sy13 + movb 16,r6 +sy15: movb ' ',0(r0) + addqd 1,r0 + addr -1(r6),r2 + andb 3,r2 + cmpqb 3,r2 + bne sy14 + movb ' ',0(r0) + addqd 1,r0 +sy14: extsd 0(r4),r2,4,4 + movb datah[r2:b],0(r0) + extsd 0(r4),r2,0,4 + movb datah[r2:b],1(r0) + addqd 2,r0 + addqd 1,r4 + acbb -1,r6,sy15 + movw x'2720,0(r0) + addqd 2,r0 + addr -16(r4),r4 + movb 16,r6 +sy16: movb 0(r4),r2 + checkb r1,cvalid,r2 + bfc sy17 + movb '.',r2 +sy17: movb r2,0(r0) + addqd 1,r0 + addqd 1,r4 + acbb -1,r6,sy16 + movd x'0A0D27,0(r0) + addqd 3,r0 + movzbw r0,-2(sb) + sprd sb,r0 + bsr string + acbb -1,r5,sy18 + movd r4,-20(sb) + br new +; Example: +; ":200000006DA60BF757A000000C80CF0F00D7A1FFFFFE00D4A315165C7810D4A30D185C7800" +; ":007FE001A0" +; R4 pointer to memory +; R5 "0" counter +syld: movqd 0,r5 +sy23: bsr getchar + cmpb ':',r0 + bne abort ; Abort if not ':' - what happens after this don't care + movqd 0,r6 ; Checksum=0 + bsr getbyte + cmpqb 0,r0 + beq sy19 ; End + movb r0,r1 + bsr getbyte + movzbd r0,r2 + lshd 8,r2 + bsr getbyte + movb r0,r2 + bsr getbyte + cmpqb 0,r0 + bne abort ; if not 0 - Abort. Limited to 64K +sy20: bsr getbyte + movb r0,r4[r2:b] + addqd 1,r2 + addqd 1,r5 + acbb -1,r1,sy20 + bsr getbyte + cmpqd 0,r6 + bne abort +sy21: bsr getchar ; CR and LF read + cmpb 10,r0 ; there are Files without CR ! + bne sy21 +; show how many load up to now R2 -> decimal + movd 10000,r0 + addr 1(sb),r3 + movd x'D0006,-2(sb) + movd r5,r2 +sy22: movd r2,r1 + divd r0,r1 + orb x'30,r1 + movb r1,0(r3) + addqd 1,r3 + modd r0,r2 + divd 10,r0 + cmpqd 0,r0 + bne sy22 + sprd sb,r0 + bsr string + br sy23 +; ******* Load finished ******* +sy19: movqb 4,r1 +sy24: bsr getbyte + acbb -1,r1,sy24 + cmpqd 0,r6 + bne abort +sy25: bsr getchar ; CR and LF read + cmpb 10,r0 + bne sy25 + addr crlf,r0 +sy26: bsr string + br new + +erin: addr erinfo,r0 + br sy26 + +getchar: + save [r1] +gec1: cmpd -8(sb),-12(sb) + beq gec1 + movd -8(sb),r1 + movb x'100(sb)[r1:b],r0 + addqb 1,-8(sb) + restore [r1] + ret 0 + +getbyte: + save [r1,r2] + bsr getchar + checkb r1,cziff,r0 + bfc geb1 + bicb x'20,r0 + checkb r1,cabc,r0 + bfc geb2 + orw x'A00,r6 +geb2: addb 10,r1 +geb1: ashd 4,r1 + bsr getchar + checkb r2,cziff,r0 + bfc geb3 + bicb x'20,r0 + checkb r2,cabc,r0 + bfc geb4 + orw x'A00,r6 +geb4: addb 10,r2 +geb3: orb r2,r1 + addb r1,r6 ; add to Checksum + movb r1,r0 + restore [r1,r2] + ret 0 + +abort: + addr lderr,r0 + bsr string + br new + +out: tbitb 11,0(r7) + bfs out + movb r0,0(r7) + ret 0 + +string: + save [r1,r7] + movd x'20200000,r7 + movw -2(r0),r1 +st3: cmpqw 0,r1 + beq st1 +st2: tbitb 11,0(r7) + bfs st2 + movb 0(r0),0(r7) + addqd 1,r0 + acbw -1,r1,st2 +st1: restore [r1,r7] + ret 0 + +datal: ; 0 1 2 3 4 5 6 7 8 9 A B C D E F + .byte x'3F,6,x'5B,x'4F,x'66,x'6D,x'7D,x'07,x'7F,x'6F,x'77,x'7C,x'39,x'5E,x'79,x'71 + +datah: .byte '0123456789ABCDEF' + + .align 4 +datfp: .double x'87654321,x'0FEDCBA9 +cvalid: .byte x'7E,x'20 +cziff: .byte '90' +cabc: .byte 'FA' + + .word txt_1-sram_ok +sram_ok: .byte '512K SRAM ok.',13,10 +txt_1: .word txt_2-welcome +welcome: .byte 13,10,'Hardware: TRIPUTER V0.1 , 27 May 2017' + .byte 13,10,'Software: MONITOR V0.1 , 27 May 2017',13,10 +txt_2: .word txt_3-idram_ok +idram_ok: .byte '128K iDRAM ok.',13,10 +txt_3: .word txt_4-error +error: .byte 'Memory Fault !!!',13,10 +txt_4: .word txt_6-lderr +lderr: .byte 13,10,'Error in Load!',13,10 +txt_6: .word txt_7-crlf +crlf: .byte 13,10 +txt_7: .word txt_8-erinfo +erinfo: .byte 'Error in input!',13,10 +txt_8: + + .align 4 +nmi: save [r0,r1] + movb -4(sb),r0 + extsd r0,r1,0,4 + comb datal[r1:b],x'200004(r7) + extsd r0,r1,4,4 + comb datal[r1:b],x'200005(r7) + bispsrb 1 + addpb 0,r0 + cmpb x'60,r0 + beq nmi1 +nmi2: movb r0,-4(sb) + restore [r0,r1] + rett 0 +nmi1: movqb 0,r0 + br nmi2 + + .align 4 +int: save [r0] ; RX UART + movd -12(sb),r0 + movb 0(r7),x'100(sb)[r0:b] + addqb 1,-12(sb) + movb x'100(sb)[r0:b],x'200000(r7) + movb r0,x'200002(r7) + restore [r0] + reti + +err: addr error,r0 + bsr string +err1: comw x'4040,4(r1) ; 0 = leuchten + br err1 + Index: m32632/trunk/TRIPUTER/read_me.txt =================================================================== --- m32632/trunk/TRIPUTER/read_me.txt (nonexistent) +++ m32632/trunk/TRIPUTER/read_me.txt (revision 35) @@ -0,0 +1,22 @@ +Welcome to TRIPUTER. + +This is the test environment for the CPU M32632. It is based on the FPGA board Cyclone V GX +Starter Kit from Terasic. The kit uses an FPGA from Intel (former Altera). + +Here comes a list of the files in the directory: + +TRIPUTER.qws the project file for Quartus +TRIPUTER.qsf the definition file for the project +TRIPUTER.v the top level of the design hierarchy for the FPGA +TRIPUTER.sdc the timing definition file +TRIPUTER_SIMU.v the top level of the design hierarchy for a simulation +TRIPUTER.sof the configuration file for the FPGA +TRIPUTER_V01.pdf a detailed description of the functionality of TRIPUTER +boot_rom.txt the content of the boot rom +monitor.32K the assembler source code of the boot rom +read_me.txt this file + +Please note: the communication over the serial link requires a carriage-return followed by +a line-feed to enter the command. + +If you have any problems please write an email to fpga@cpu-ns32k.net

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