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URL https://opencores.org/ocsvn/openverifla/openverifla/trunk

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    from Rev 34 to Rev 35
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Rev 34 → Rev 35

/openverifla/trunk/openverifla_2.2.f/verilog/verifla/memory_of_verifla.v
25,10 → 25,6
input [LA_MEM_WORDLEN_BITS-1:0] dina;
 
reg [LA_MEM_WORDLEN_BITS-1:0] mem[LA_MEM_LAST_ADDR:0];
`ifdef DEBUG_LA
reg [LA_DATA_INPUT_WORDLEN_BITS-1:0] m1[LA_MEM_LAST_ADDR:0];
reg [LA_IDENTICAL_SAMPLES_BITS-1:0] m2[LA_MEM_LAST_ADDR:0];
`endif
 
//assign doutb = mem[addrb];
// This works too as a consequence of send_capture_of_verifla architecture.
43,9 → 39,7
always @(posedge clk)
begin
if(wea) begin
mem[addra] <= dina;
//m1[addra] <= dina[LA_DATA_INPUT_WORDLEN_BITS-1:0];
//m2[addra] <= dina[LA_MEM_WORDLEN_BITS-1:LA_DATA_INPUT_WORDLEN_BITS];
mem[addra] <= dina;
end
end
`else
58,9 → 52,7
mem[i] <= LA_MEM_EMPTY_SLOT;
end else begin
if(wea) begin
mem[addra] <= dina;
//m1[addra] <= dina[LA_DATA_INPUT_WORDLEN_BITS-1:0];
//m2[addra] <= dina[LA_MEM_WORDLEN_BITS-1:LA_DATA_INPUT_WORDLEN_BITS];
mem[addra] <= dina;
end
end
end
70,7 → 62,7
integer i;
for(i=0; i<=LA_MEM_LAST_ADDR; i=i+1)
mem[i] <= LA_MEM_EMPTY_SLOT;
//$readmemh("mem2018.mif", mem);
//$readmemh("mem2018-2.mif", mem);
end
 
endmodule
/openverifla/trunk/openverifla_2.2.f/vhdl/verifla/monitor_of_verifla.vhd
45,26 → 45,18
--MON_STATE_WAIT_TRIGGER_MATCH, MON_STATE_AFTER_TRIGGER, MON_STATE_DATA_CAPTURED,
--MON_STATE_SC_RUN, MON_STATE_WAIT_SC_DONE);
-- This way, at reset we can set any start state.
constant MON_STATE_IDLE_INT: integer :=0;
constant MON_STATE_DO_MEM_CLEAN_INT: integer :=1;
constant MON_STATE_PREPARE_RUN_INT: integer :=2;
constant MON_STATE_WAIT_TRIGGER_MATCH_INT: integer :=3;
constant MON_STATE_AFTER_TRIGGER_INT: integer :=4;
constant MON_STATE_DATA_CAPTURED_INT: integer :=5;
constant MON_STATE_SC_RUN_INT: integer :=6;
constant MON_STATE_WAIT_SC_DONE_INT: integer :=7;
constant MON_STATE_IDLE: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_IDLE_INT,4));
constant MON_STATE_DO_MEM_CLEAN: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_DO_MEM_CLEAN_INT,4));
constant MON_STATE_PREPARE_RUN: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_PREPARE_RUN_INT,4));
constant MON_STATE_WAIT_TRIGGER_MATCH: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_WAIT_TRIGGER_MATCH_INT,4));
constant MON_STATE_AFTER_TRIGGER: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_AFTER_TRIGGER_INT,4));
constant MON_STATE_DATA_CAPTURED: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_DATA_CAPTURED_INT,4));
constant MON_STATE_SC_RUN: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_SC_RUN_INT,4));
constant MON_STATE_WAIT_SC_DONE: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(MON_STATE_WAIT_SC_DONE_INT,4));
constant MON_STATE_IDLE: integer :=0;
constant MON_STATE_DO_MEM_CLEAN: integer :=1;
constant MON_STATE_PREPARE_RUN: integer :=2;
constant MON_STATE_WAIT_TRIGGER_MATCH: integer :=3;
constant MON_STATE_AFTER_TRIGGER: integer :=4;
constant MON_STATE_DATA_CAPTURED: integer :=5;
constant MON_STATE_SC_RUN: integer :=6;
constant MON_STATE_WAIT_SC_DONE: integer :=7;
 
signal sys_run_reg: std_logic;
signal sc_run_aux, next_sc_run_aux: std_logic;
signal mon_state, next_mon_state: std_logic_vector(3 downto 0);
signal mon_state, next_mon_state: integer; -- state_type;
signal next_mon_samples_after_trigger, mon_samples_after_trigger:
std_logic_vector(LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1 downto 0);
signal next_mon_write_address, mon_write_address:
144,8 → 136,8
mem_port_A_address <= (others => '0');
mem_port_A_data_in <= (others => '0');
mem_port_A_wen <= '0';
case to_integer(unsigned(mon_state)) is
when MON_STATE_IDLE_INT =>
case mon_state is
when MON_STATE_IDLE =>
if((sys_run_reg = '1') or (user_run = '1')) then
if((LA_MEM_CLEAN_BEFORE_RUN = 1) or (user_run = '1')) then
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
165,7 → 157,7
else
next_mon_state <= MON_STATE_IDLE;
end if;
when MON_STATE_DO_MEM_CLEAN_INT =>
when MON_STATE_DO_MEM_CLEAN =>
mem_port_A_address <= mon_write_address;
mem_port_A_data_in <= LA_MEM_EMPTY_SLOT;
mem_port_A_wen <= '1';
177,7 → 169,7
-- at the new posedge clock, will clean memory at its last address
next_mon_state <= MON_STATE_PREPARE_RUN;
end if;
when MON_STATE_PREPARE_RUN_INT =>
when MON_STATE_PREPARE_RUN =>
-- mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
-- we share the same clock as memory.
mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
188,7 → 180,7
next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
when MON_STATE_WAIT_TRIGGER_MATCH_INT =>
when MON_STATE_WAIT_TRIGGER_MATCH =>
-- circular queue
if((mon_current_data_in and LA_TRIGGER_MASK) /= (LA_TRIGGER_VALUE and LA_TRIGGER_MASK)) then
next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
262,7 → 254,7
next_bt_queue_tail_address <= mon_write_address;
next_mon_samples_after_trigger <= std_logic_vector(to_unsigned(1, LA_MAX_SAMPLES_AFTER_TRIGGER_BITS));
end if;
when MON_STATE_AFTER_TRIGGER_INT =>
when MON_STATE_AFTER_TRIGGER =>
if((to_integer(unsigned(mon_samples_after_trigger)) < LA_MAX_SAMPLES_AFTER_TRIGGER) and
(to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR)) then
mem_port_A_wen <= '1';
314,7 → 306,7
mem_port_A_wen <= '0';
next_mon_state <= MON_STATE_DATA_CAPTURED;
end if;
when MON_STATE_DATA_CAPTURED_INT =>
when MON_STATE_DATA_CAPTURED =>
-- Save bt_queue_tail_address
mem_port_A_address <= LA_BT_QUEUE_TAIL_ADDRESS_SLV;
mem_port_A_data_in <=
322,10 → 314,10
-- {{(LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS){1'b0}}, bt_queue_tail_address};
mem_port_A_wen <= '1';
next_mon_state <= MON_STATE_SC_RUN;
when MON_STATE_SC_RUN_INT =>
when MON_STATE_SC_RUN =>
next_mon_state <= MON_STATE_WAIT_SC_DONE;
next_sc_run_aux <= '1';
when MON_STATE_WAIT_SC_DONE_INT =>
when MON_STATE_WAIT_SC_DONE =>
-- sc_run must already be 1.
if(ack_sc_run = '1') then
next_sc_run_aux <= '0';

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