OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

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  • This comparison shows the changes necessary to convert path 
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    from Rev 34 to Rev 35
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Rev 34 → Rev 35

/uart_block/trunk/hdl/iseProject/isim.log
1,20 → 1,24
ISim log file
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
# exit 0
ISim log file
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_wishbone_slave.vhd:stim_proc
INFO: Simulator is stopped.
/uart_block/trunk/hdl/iseProject/testSerial_receiver.vhd
15,7 → 15,6
COMPONENT serial_receiver
PORT(
rst : IN std_logic;
baudClk : IN std_logic;
baudOverSampleClk : IN std_logic;
serial_in : IN std_logic;
data_ready : OUT std_logic;
36,14 → 35,13
 
-- Clock period definitions
constant baudClk_period : time := 8.6805 us;
constant baudOverSampleClk_period : time := 1 us;
constant baudOverSampleClk_period : time :=1.085 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: serial_receiver PORT MAP (
rst => rst,
baudClk => baudClk,
rst => rst,
baudOverSampleClk => baudOverSampleClk,
serial_in => serial_in,
data_ready => data_ready,
/uart_block/trunk/hdl/iseProject/fuseRelaunch.cmd
1,14 → 35,13
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_beh.prj" "testUart_communication_block"
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave"
/uart_block/trunk/hdl/iseProject/Sim_ConfigReceiver.wcfg
0,0 → 1,40
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="pkgdefinitions" />
<top_module name="std_logic_1164" />
<top_module name="testserial_receiver" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="6" />
<wvobject fp_name="/testserial_receiver/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/testserial_receiver/serial_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_in</obj_property>
<obj_property name="ObjectShortName">serial_in</obj_property>
</wvobject>
<wvobject fp_name="/testserial_receiver/baudoversampleclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">baudoversampleclk</obj_property>
<obj_property name="ObjectShortName">baudoversampleclk</obj_property>
</wvobject>
<wvobject fp_name="/testserial_receiver/uut/syncdetected" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">syncdetected</obj_property>
<obj_property name="ObjectShortName">syncdetected</obj_property>
</wvobject>
<wvobject fp_name="/testserial_receiver/data_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_ready</obj_property>
<obj_property name="ObjectShortName">data_ready</obj_property>
</wvobject>
<wvobject fp_name="/testserial_receiver/data_byte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_byte[7:0]</obj_property>
<obj_property name="ObjectShortName">data_byte[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wave_config>
/uart_block/trunk/hdl/iseProject/testSerial_transmitter_isim_beh.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/fuse.log
1,33 → 1,37
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_beh.prj testUart_communication_block
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 37468 KB
Fuse CPU Usage: 1080 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling package numeric_std
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavior of entity testuart_communication_block
Time Resolution for simulation is 1ps.
Compiled 15 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe
Fuse Memory Usage: 90156 KB
Fuse CPU Usage: 1250 ms
GCC CPU Usage: 500 ms
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 62: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling package numeric_std
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
Compiling architecture behavior of entity testuart_wishbone_slave
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 21 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
Fuse Memory Usage: 37428 KB
Fuse CPU Usage: 420 ms
/uart_block/trunk/hdl/iseProject/webtalk_pn.xml
3,10 → 3,10
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat May 05 20:13:16 2012">
<application name="pn" timeStamp="Sat May 05 22:40:10 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="29" type="project"/>
<property name="ProjectIteration" value="30" type="project"/>
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/>
</section>
27,7 → 27,7
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/>
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWbtProjectIteration" value="29" type="process"/>
<property name="PROP_intWbtProjectIteration" value="30" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
/uart_block/trunk/hdl/iseProject/iseProject.xise
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
60,17 → 60,17
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL">
80,11 → 80,11
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="164"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/>
331,8 → 331,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_communication_block" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
348,7 → 348,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
398,7 → 398,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_communication_block|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/uart_block/trunk/hdl/iseProject/xst/work/hdpdeps.ref
12,73 → 12,73
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/02.08:07:03 O.87xd
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/05.19:53:55 O.87xd
EN work/baud_generator 1336240857 \
EN work/baud_generator 1336250413 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336240856
AR work/baud_generator/Behavioral 1336240858 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336240857
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336250412
AR work/baud_generator/Behavioral 1336250414 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336250413
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd
EN work/divisor 1336240863 FL E:/uart_block/hdl/iseProject/divisor.vhd \
EN work/divisor 1336250419 FL E:/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1336240856
AR work/divisor/Behavioral 1336240864 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336240863
PB work/pkgDefinitions 1336250412
AR work/divisor/Behavioral 1336250420 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336250419
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd
EN work/INTERCON_P2P 1336240875 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \
EN work/INTERCON_P2P 1336250431 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \
PB ieee/std_logic_1164 1325952872
AR work/INTERCON_P2P/Behavioral 1336240876 \
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336240875 \
AR work/INTERCON_P2P/Behavioral 1336250432 \
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336250431 \
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/05.19:53:54 O.87xd
PH work/pkgDefinitions 1336240855 \
PH work/pkgDefinitions 1336250411 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1336240856 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336240855
PB work/pkgDefinitions 1336250412 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336250411
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.01:05:05 O.87xd
EN work/SERIALMASTER 1336240871 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \
EN work/SERIALMASTER 1336250427 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336240856
AR work/SERIALMASTER/Behavioral 1336240872 \
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336240871
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/05.20:00:38 O.87xd
EN work/serial_receiver 1336240861 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336250412
AR work/SERIALMASTER/Behavioral 1336250428 \
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336250427
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/05.22:39:11 O.87xd
EN work/serial_receiver 1336250417 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1336240856
AR work/serial_receiver/Behavioral 1336240862 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336240861
PB work/pkgDefinitions 1336250412
AR work/serial_receiver/Behavioral 1336250418 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336250417
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1336240859 \
EN work/serial_transmitter 1336250415 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336240856
AR work/serial_transmitter/Behavioral 1336240860 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336250412
AR work/serial_transmitter/Behavioral 1336250416 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1336240859
EN work/serial_transmitter 1336250415
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd
EN work/SYC0001a 1336240869 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \
EN work/SYC0001a 1336250425 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \
PB ieee/std_logic_1164 1325952872
AR work/SYC0001a/SYC0001a1 1336240870 \
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336240869
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd
EN work/uart_communication_blocks 1336240867 \
AR work/SYC0001a/SYC0001a1 1336250426 \
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336250425
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/05/05.22:40:08 O.87xd
EN work/uart_communication_blocks 1336250423 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336240856
AR work/uart_communication_blocks/Behavioral 1336240868 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336250412
AR work/uart_communication_blocks/Behavioral 1336250424 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
EN work/uart_communication_blocks 1336240867 CP baud_generator \
EN work/uart_communication_blocks 1336250423 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd
EN work/uart_control 1336240865 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
EN work/uart_control 1336250421 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336240856
AR work/uart_control/Behavioral 1336240866 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336240865 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336250412
AR work/uart_control/Behavioral 1336250422 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336250421 \
CP divisor
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd
EN work/uart_wishbone_slave 1336240873 \
EN work/uart_wishbone_slave 1336250429 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336240856
AR work/uart_wishbone_slave/Behavioral 1336240874 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336250412
AR work/uart_wishbone_slave/Behavioral 1336250430 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
EN work/uart_wishbone_slave 1336240873 CP uart_control \
EN work/uart_wishbone_slave 1336250429 CP uart_control \
CP uart_communication_blocks
/uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
1,22 → 1,22
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336240868
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336240866
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336240870
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336240875
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336240856
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336240861
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336240874
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336240860
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336240867
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336240863
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336240864
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336240858
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336240869
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336240871
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336240865
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336240876
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336240859
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336240855
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336240872
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336240873
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336240857
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336240862
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336250424
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336250422
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336250426
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336250431
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336250412
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336250417
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336250430
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336250416
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336250423
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336250419
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336250420
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336250414
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336250425
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336250427
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336250421
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336250432
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336250415
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336250411
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336250428
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336250429
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336250413
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336250418
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/serial_receiver.vhd
8,8 → 8,7
 
entity serial_receiver is
Port (
rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
rst : in STD_LOGIC;
baudOverSampleClk : in STD_LOGIC;
serial_in : in STD_LOGIC;
data_ready : out STD_LOGIC;
20,7 → 19,6
signal current_s: rxStates;
signal filterRx : rxFilterStates;
signal syncDetected : std_logic;
signal getPoint : std_logic;
 
begin
-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
97,105 → 95,88
current_s <= bit0;
data_ready <= '0';
byteReceived := (others => '0');
waitBestPoint := 0;
getPoint <= '0';
waitBestPoint := 0;
elsif rising_edge(baudOverSampleClk) then
case current_s is
when bit0 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(0) := serial_in;
current_s <= bit1;
getPoint <= '1';
current_s <= bit1;
end if;
 
when bit1 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(1) := serial_in;
current_s <= bit2;
getPoint <= '1';
current_s <= bit2;
end if;
 
when bit2 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(2) := serial_in;
current_s <= bit3;
getPoint <= '1';
current_s <= bit3;
end if;
 
when bit3 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(3) := serial_in;
current_s <= bit4;
getPoint <= '1';
current_s <= bit4;
end if;
 
when bit4 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(4) := serial_in;
current_s <= bit5;
getPoint <= '1';
current_s <= bit5;
end if;
 
when bit5 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(5) := serial_in;
current_s <= bit6;
getPoint <= '1';
current_s <= bit6;
end if;
 
when bit6 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(6) := serial_in;
current_s <= bit7;
getPoint <= '1';
current_s <= bit7;
end if;
when bit7 =>
data_ready <= '0';
if (waitBestPoint < numTicks) then
waitBestPoint := waitBestPoint + 1;
getPoint <= '0';
waitBestPoint := waitBestPoint + 1;
else
waitBestPoint := 0;
byteReceived(7) := serial_in;
data_byte <= byteReceived;
current_s <= rx_stop;
getPoint <= '1';
current_s <= rx_stop;
end if;
 
when rx_stop =>
206,8 → 187,7
when rx_idle =>
data_ready <= '1';
data_byte <= byteReceived;
current_s <= rx_idle;
current_s <= rx_idle;
end case;
end if;
end process;
/uart_block/trunk/hdl/iseProject/iseProject.gise
149,7 → 149,6
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_communication_block_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_wishbone_slave_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
203,14 → 202,12
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914584" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335914584">
<transform xil_pn:end_ts="1336250815" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336250815">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.vhd"/>
<outfile xil_pn:name="SERIALMASTER.vhd"/>
<outfile xil_pn:name="SYC0001a.vhd"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
227,27 → 224,24
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1335899449" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335899449">
<transform xil_pn:end_ts="1336250968" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1336250968">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335899449" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335899449">
<transform xil_pn:end_ts="1336250968" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1336250968">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335914584" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335914584">
<transform xil_pn:end_ts="1336250441" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-7719148281395352834" xil_pn:start_ts="1336250441">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1335914584" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335914584">
<transform xil_pn:end_ts="1336250815" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336250815">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.vhd"/>
<outfile xil_pn:name="SERIALMASTER.vhd"/>
<outfile xil_pn:name="SYC0001a.vhd"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
264,31 → 258,22
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1335914587" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335914584">
<transform xil_pn:end_ts="1336250972" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1336250968">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testUart_wishbone_slave_beh.prj"/>
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335914664" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335914664">
<transform xil_pn:end_ts="1336250972" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1336250972">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
318,12 → 303,10
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336240864" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336240853">
<transform xil_pn:end_ts="1336250421" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336250409">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.lso"/>
<outfile xil_pn:name="INTERCON_P2P.ngc"/>
<outfile xil_pn:name="INTERCON_P2P.ngr"/>
347,10 → 330,12
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336241592" xil_pn:in_ck="4758608941402184672" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336241583">
<transform xil_pn:end_ts="1336249519" xil_pn:in_ck="4758608941402184672" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336249504">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.bld"/>
<outfile xil_pn:name="INTERCON_P2P.ngd"/>
<outfile xil_pn:name="INTERCON_P2P_cs.blc"/>
359,10 → 344,11
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1336241596" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336241592">
<transform xil_pn:end_ts="1336249526" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336249519">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.pcf"/>
375,10 → 361,11
<outfile xil_pn:name="INTERCON_P2P_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1336241607" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336241596">
<transform xil_pn:end_ts="1336249541" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336249526">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="INTERCON_P2P.ncd"/>
<outfile xil_pn:name="INTERCON_P2P.pad"/>
<outfile xil_pn:name="INTERCON_P2P.par"/>
390,10 → 377,13
<outfile xil_pn:name="INTERCON_P2P_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1336241621" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336241607">
<transform xil_pn:end_ts="1336249555" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336249541">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="intercon_p2p.bgn"/>
403,26 → 393,28
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1336240611" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336240610">
<transform xil_pn:end_ts="1336249692" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336249691">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1336093998" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336093998">
<transform xil_pn:end_ts="1336249854" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336249853">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1336243447" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1336243447">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1336241680" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1336241675">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336241607" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336241605">
<transform xil_pn:end_ts="1336249541" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336249538">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="INTERCON_P2P.twr"/>
<outfile xil_pn:name="INTERCON_P2P.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/uart_block/trunk/hdl/iseProject/Sim_ConfigTransmitter.wcfg
0,0 → 1,35
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="E:/uart_block/hdl/iseProject/testSerial_transmitter_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="pkgdefinitions" />
<top_module name="std_logic_1164" />
<top_module name="testserial_transmitter" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="5" />
<wvobject fp_name="/testserial_transmitter/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/testserial_transmitter/baudclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">baudclk</obj_property>
<obj_property name="ObjectShortName">baudclk</obj_property>
</wvobject>
<wvobject fp_name="/testserial_transmitter/data_byte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_byte[7:0]</obj_property>
<obj_property name="ObjectShortName">data_byte[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/testserial_transmitter/data_sent" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_sent</obj_property>
<obj_property name="ObjectShortName">data_sent</obj_property>
</wvobject>
<wvobject fp_name="/testserial_transmitter/serial_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_out</obj_property>
<obj_property name="ObjectShortName">serial_out</obj_property>
</wvobject>
</wave_config>
/uart_block/trunk/hdl/iseProject/iseconfig/iseProject.projectmgr
7,6 → 7,7
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/INTERCON_P2P - Behavioral E:|uart_block|hdl|iseProject|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral</ClosedNode>
<ClosedNode>/INTERCON_P2P - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral</ClosedNode>
<ClosedNode>/serial_transmitter - Behavioral E:|uart_block|hdl|iseProject|serial_transmitter.vhd</ClosedNode>
<ClosedNode>/uart_wishbone_slave - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|uart_wishbone_slave.vhd/uUartCommunicationBlocks - uart_communication_blocks - Behavioral</ClosedNode>
17,7 → 18,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000259000000020000000000000000000000000200000064ffffffff000000810000000300000002000002590000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001ef000000020000000000000000000000000200000064ffffffff000000810000000300000002000001ef0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>INTERCON_P2P - Behavioral (E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd)</CurrentItem>
</ItemView>
34,7 → 35,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Design Utilities</CurrentItem>
</ItemView>
47,7 → 48,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000002f1000000040101000100000000000000000000000064ffffffff000000810000000000000004000000690000000100000000000000240000000100000000000000660000000100000000000001fe0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000301000000040101000100000000000000000000000064ffffffff0000008100000000000000040000006900000001000000000000002400000001000000000000006600000001000000000000020e0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>pkgDefinitions.vhd</CurrentItem>
</ItemView>
67,21 → 68,26
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate Post-Place &amp; Route Static Timing</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Analyze Design Using ChipScope</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >10</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Analyze Design Using ChipScope</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/INTERCON_P2P - Behavioral E:|uart_block|hdl|iseProject|INTERCON_P2P.vhd</ClosedNode>
<ClosedNode>/INTERCON_P2P - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|INTERCON_P2P.vhd</ClosedNode>
<ClosedNode>/testBaud_generator - behavior E:|uart_block|hdl|iseProject|testBaud_generator.vhd</ClosedNode>
<ClosedNode>/testBaud_generator - behavior |home|laraujo|work|uart_block|hdl|iseProject|testBaud_generator.vhd</ClosedNode>
102,13 → 108,13
<ClosedNode>/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Unassigned User Library Modules</SelectedItem>
<SelectedItem>testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000259000000020000000000000000000000000200000064ffffffff000000810000000300000002000002590000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001bd000000020000000000000000000000000200000064ffffffff000000810000000300000002000001bd0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>Unassigned User Library Modules</CurrentItem>
<CurrentItem>testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
138,7 → 144,7
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000040100000002</SourceProcessView>
<CurrentView>Behavioral Simulation</CurrentView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
157,12 → 163,12
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem></CurrentItem>
</ItemView>
</Project>
/uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/Sim_ConfigWishboneSlave.wcfg
0,0 → 1,68
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="pkgdefinitions" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="testuart_wishbone_slave" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="12" />
<wvobject fp_name="/testuart_wishbone_slave/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/adr_i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i0[1:0]</obj_property>
<obj_property name="ObjectShortName">adr_i0[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/dat_i0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i0[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i0[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/serial_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_in</obj_property>
<obj_property name="ObjectShortName">serial_in</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/dat_o0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o0[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o0[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/serial_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_out</obj_property>
<obj_property name="ObjectShortName">serial_out</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/data_avaible" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_avaible</obj_property>
<obj_property name="ObjectShortName">data_avaible</obj_property>
</wvobject>
<wvobject fp_name="/testuart_wishbone_slave/clk_i_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_i_period</obj_property>
<obj_property name="ObjectShortName">clk_i_period</obj_property>
</wvobject>
</wave_config>
/uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/serial_receiver.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testSerial_receiver.vhd&quot; into library work</arg>
</msg>
 
</messages>
/uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
5,976 → 5,970
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">80</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">CYC_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">80</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">CYC_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">80</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">SEL_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">80</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">SEL_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">95</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">data_Avaible</arg>&apos; of component &apos;<arg fmt="%s" index="4">uart_wishbone_slave</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">95</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">data_Avaible</arg>&apos; of component &apos;<arg fmt="%s" index="4">uart_wishbone_slave</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="1610" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>&quot; line <arg fmt="%d" index="2">46</arg>: Width mismatch. &lt;<arg fmt="%s" index="3">byteIncome</arg>&gt; has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide.
<msg type="warning" file="Xst" num="1610" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>&quot; line <arg fmt="%d" index="2">46</arg>: Width mismatch. &lt;<arg fmt="%s" index="3">byteIncome</arg>&gt; has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide.
</msg>
 
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">62</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">reminder</arg>&apos; of component &apos;<arg fmt="%s" index="4">divisor</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">62</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">reminder</arg>&apos; of component &apos;<arg fmt="%s" index="4">divisor</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DAT_I&lt;31:8&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DAT_I&lt;31:8&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
 
<msg type="warning" file="Xst" num="1305" delta="old" >Output &lt;<arg fmt="%s" index="1">CYC_O</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
<msg type="warning" file="Xst" num="1305" delta="new" >Output &lt;<arg fmt="%s" index="1">CYC_O</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
 
<msg type="warning" file="Xst" num="1305" delta="old" >Output &lt;<arg fmt="%s" index="1">SEL_O</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
<msg type="warning" file="Xst" num="1305" delta="new" >Output &lt;<arg fmt="%s" index="1">SEL_O</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
 
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">baudClk</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">data_avaible</arg>&gt; is never assigned.
</msg>
 
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">getPoint</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;half_cycle0_22&gt; </arg>
</msg>
 
<msg type="warning" file="Xst" num="1306" delta="old" >Output &lt;<arg fmt="%s" index="1">data_avaible</arg>&gt; is never assigned.
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;half_cycle0_13&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;half_cycle0_22&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;half_cycle0_9&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;half_cycle0_13&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;half_cycle0_0&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;half_cycle0_9&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;half_cycle0_3&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;half_cycle0_0&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;half_cycle0_27&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;half_cycle0_3&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;half_cycle0_23&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;half_cycle0_27&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;half_cycle0_18&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;half_cycle0_23&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;half_cycle0_21&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;half_cycle0_18&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;half_cycle0_12&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;half_cycle0_21&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;half_cycle0_12&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;half_cycle0_26&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;half_cycle0_1&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;half_cycle0_26&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;cycle_wait_oversample_31&gt; &lt;cycle_wait_oversample_30&gt; &lt;half_cycle_31&gt; &lt;half_cycle0_31&gt; &lt;half_cycle0_30&gt; &lt;half_cycle0_29&gt; &lt;half_cycle0_28&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;half_cycle0_1&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;half_cycle0_17&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;cycle_wait_oversample_31&gt; &lt;cycle_wait_oversample_30&gt; &lt;half_cycle_31&gt; &lt;half_cycle0_31&gt; &lt;half_cycle0_30&gt; &lt;half_cycle0_29&gt; &lt;half_cycle0_28&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;half_cycle0_7&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;half_cycle0_17&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;half_cycle0_4&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;half_cycle0_7&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;half_cycle0_20&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;half_cycle0_4&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;half_cycle0_15&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;half_cycle0_20&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;half_cycle0_11&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;half_cycle0_15&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;half_cycle0_25&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;half_cycle0_11&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;half_cycle0_6&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;half_cycle0_25&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;half_cycle0_16&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;half_cycle0_6&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;half_cycle0_19&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;half_cycle0_16&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;half_cycle0_14&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;half_cycle0_19&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;half_cycle0_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;half_cycle0_14&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;half_cycle0_8&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;half_cycle0_2&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;half_cycle0_10&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;half_cycle0_8&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;half_cycle0_5&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;half_cycle0_10&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;half_cycle0_24&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;half_cycle0_5&gt; </arg>
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">uBaudGen</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;half_cycle0_24&gt; </arg>
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_clk_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uBaudGen</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">config_baud_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uBaudGen</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uMasterSerial</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">N_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">N_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">D_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">D_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uDiv</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivDividend_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">sigDivNumerator_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">uUartControl</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;half_cycle0_22&gt; </arg>
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;half_cycle0_13&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;half_cycle0_22&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;half_cycle0_9&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;half_cycle0_13&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;half_cycle0_0&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;half_cycle0_9&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;half_cycle0_3&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;half_cycle0_0&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;half_cycle0_27&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;half_cycle0_3&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;half_cycle0_23&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;half_cycle0_27&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;half_cycle0_18&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;half_cycle0_23&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;half_cycle0_21&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;half_cycle0_18&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;half_cycle0_12&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;half_cycle0_21&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;half_cycle0_12&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;half_cycle0_26&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;half_cycle0_1&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;half_cycle0_26&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;half_cycle0_17&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;half_cycle0_1&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;half_cycle0_7&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;half_cycle0_17&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;half_cycle0_4&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;half_cycle0_7&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;half_cycle0_20&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;half_cycle0_4&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;half_cycle0_15&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;half_cycle0_20&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;half_cycle0_11&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;half_cycle0_15&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;half_cycle0_25&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;half_cycle0_11&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;half_cycle0_6&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;half_cycle0_25&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;half_cycle0_16&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;half_cycle0_6&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;half_cycle0_19&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;half_cycle0_16&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;half_cycle0_14&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;half_cycle0_19&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;half_cycle0_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;half_cycle0_14&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;half_cycle0_8&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;half_cycle0_2&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;half_cycle0_10&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;half_cycle0_8&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;half_cycle0_5&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;half_cycle0_10&gt; </arg>
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;half_cycle0_24&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;half_cycle0_5&gt; </arg>
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;half_cycle0_24&gt; </arg>
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_4</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_4</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_23</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">nextState_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycles2Wait_23</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">nextState_5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">nextState_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">serial_receiver</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;data_ready&gt; </arg>
</msg>
 
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">nextState_5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">SERIALMASTER</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="2042" delta="new" >Unit <arg fmt="%s" index="1">uart_control</arg>: <arg fmt="%d" index="2">32</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">serial_receiver</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;data_ready&gt; </arg>
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">waitBestPoint_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">serial_receiver</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">uart_control</arg>: <arg fmt="%d" index="2">32</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
 
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">waitBestPoint_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">serial_receiver</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">waitBestPoint_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">serial_receiver</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">waitBestPoint_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">serial_receiver</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1293" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">waitBestPoint_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">serial_receiver</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">waitBestPoint_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">serial_receiver</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">INTERCON_P2P</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">INTERCON_P2P</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;11&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;11&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;18&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;18&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;24&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;24&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;26&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;26&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;27&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;27&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;28&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;28&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;29&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;29&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;30&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;30&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;31&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;31&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="warning" file="Xst" num="638" delta="new" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;8&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
</msg>
 
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;8&gt;</arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O&lt;10&gt;</arg> signal will be lost.
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
</messages>
 
/uart_block/trunk/hdl/iseProject/fuse.xmsgs
1,12 → 1,12
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression
</msg>
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 62: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression
</msg>
 
</messages>
 
 
/uart_block/trunk/hdl/iseProject/xilinxsim.ini
1,12 → 1,12
work=isim/work
work=isim/work
/uart_block/trunk/hdl/iseProject/isim.cmd
1,3 → 1,3
onerror {resume}
wave add /
run 1000 ms;
onerror {resume}
wave add /
run 1000 ms;
/uart_block/trunk/hdl/iseProject/Sim_ConfigCommBlocks.wcfg
0,0 → 1,59
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="pkgdefinitions" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="testuart_communication_block" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="10" />
<wvobject fp_name="/testuart_communication_block/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/cycle_wait_baud" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cycle_wait_baud[31:0]</obj_property>
<obj_property name="ObjectShortName">cycle_wait_baud[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/byte_tx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">byte_tx[7:0]</obj_property>
<obj_property name="ObjectShortName">byte_tx[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/serial_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_in</obj_property>
<obj_property name="ObjectShortName">serial_in</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/start_tx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">start_tx</obj_property>
<obj_property name="ObjectShortName">start_tx</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/byte_rx" type="array" db_ref_id="1">
<obj_property name="ElementShortName">byte_rx[7:0]</obj_property>
<obj_property name="ObjectShortName">byte_rx[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/data_sent_tx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_sent_tx</obj_property>
<obj_property name="ObjectShortName">data_sent_tx</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/data_received_rx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">data_received_rx</obj_property>
<obj_property name="ObjectShortName">data_received_rx</obj_property>
</wvobject>
<wvobject fp_name="/testuart_communication_block/serial_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">serial_out</obj_property>
<obj_property name="ObjectShortName">serial_out</obj_property>
</wvobject>
</wave_config>
/uart_block/trunk/hdl/iseProject/uart_communication_blocks.vhd
39,8 → 39,7
 
component serial_receiver is
Port (
rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
rst : in STD_LOGIC;
baudOverSampleClk : in STD_LOGIC;
serial_in : in STD_LOGIC;
data_ready : out STD_LOGIC;
69,8 → 68,7
-- Instantiate serial_receiver
uReceiver : serial_receiver port map(
rst => rst,
baudClk => baud_tick,
rst => rst,
baudOverSampleClk => baud_tick_oversample,
serial_in => serial_in,
data_ready => data_received_rx,

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