OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 343 to Rev 344
    ↔ Reverse comparison
  •

Rev 343 → Rev 344

/trunk/gen_or1k_isa/sources/or32.c
29,10 → 29,6
#endif
#include "opcode/or32.h"
 
#ifndef debug
#define debug
#endif
 
/* **INDENT-OFF** */
 
CONST struct or32_letter or32_letters[] =
487,13 → 483,13
last_match = i;
}
debug("%08X %08X\n", mask, cur_mask);
debug(8, "%08X %08X\n", mask, cur_mask);
if (ninstr == 0)
return 0;
if (ninstr == 1)
{
/* Leaf holds instruction index. */
debug("%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
debug(8, "%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
*cur = LEAF_FLAG | last_match;
cur++;
nuncovered--;
505,18 → 501,18
for (len = best_len + 1; len < MIN(MAX_LEN, 33 - i); len++)
{
unsigned long m = (1UL << ((unsigned long)len)) - 1;
/*debug(" (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);*/
debug(9, " (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);
if ((m & (cur_mask >> (unsigned)i)) == m)
{
best_len = len;
best_first = i;
/*debug("!");*/
debug(9, "!");
}
else
break;
}
}
/*debug("\n");*/
debug(9, "\n");
if (!best_len)
{
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
527,7 → 523,7
fprintf (stderr, "\n");
exit (1);
}
debug("%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
debug(8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
*cur = best_first;
cur++;
*cur = (1 << best_len) - 1;
548,17 → 544,17
&& ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
ti[j].in_pass = curpass;
 
/*debug("%08X %08X %i\n", mask, cur_mask, best_first);*/
debug(9, "%08X %08X %i\n", mask, cur_mask, best_first);
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
if (c)
{
debug("%i> #%X -> %u\n", next - automata, i, cur - automata);
debug(8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
*next = cur - automata;
cur = c;
}
else
{
debug("%i> N/A\n", next - automata);
debug(8, "%i> N/A\n", next - automata);
*next = 0;
}
next++;
596,7 → 592,7
if (!(*args)) {
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
cur->data = 0;
debug("#%08X %08X\n", cur->type, cur->data);
debug(8, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
612,7 → 608,7
{
unsigned long arg;
arg = insn_extract(*args, opcode->encoding);
debug("%s : %08X ------\n", opcode->name, arg);
debug(3, "%s : %08X ------\n", opcode->name, arg);
if (letter_signed (*args))
{
type |= OPTYPE_SIG;
637,7 → 633,7
cur->type = type | shr;
cur->data = mask;
arg &= ~(((1 << mask) - 1) << shr);
debug("|%08X %08X\n", cur->type, cur->data);
debug(3, "|%08X %08X\n", cur->type, cur->data);
cur++;
}
args++;
647,7 → 643,7
/* Next param is displacement. Later we will treat them as one operand. */
cur--;
cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
657,7 → 653,7
{
cur--;
cur->type = type | cur->type | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
667,7 → 663,7
{
cur->type = type;
cur->data = 0;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
683,7 → 679,7
}
cur--;
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
debug("#%08X %08X\n", cur->type, cur->data);
debug(3, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
712,7 → 708,7
ti[i].insn_mask = ones | zeros;
ti[i].insn = ones;
ti[i].in_pass = curpass = 0;
/*debug("%s: %s %08X %08X\n", or32_opcodes[i].name,
/*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
}
758,19 → 754,19
while (!(*a & LEAF_FLAG))
{
unsigned int first = *a;
debug("%i ", a - automata);
debug(8, "%i ", a - automata);
a++;
i = (insn >> first) & *a;
a++;
if (!*(a + i))
{ /* Invalid instruction found? */
debug("XXX\n", i);
debug(8, "XXX\n", i);
return -1;
}
a = automata + *(a + i);
}
i = *a & ~LEAF_FLAG;
debug("%i\n", i);
debug(8, "%i\n", i);
/* Final check - do we have direct match?
(based on or32_opcodes this should be the only possibility,
but in case of invalid/missing instruction we must perform a check) */
/trunk/gen_or1k_isa/sources/opcode/or32.c
29,10 → 29,6
#endif
#include "opcode/or32.h"
 
#ifndef debug
#define debug
#endif
 
/* **INDENT-OFF** */
 
CONST struct or32_letter or32_letters[] =
487,13 → 483,13
last_match = i;
}
debug("%08X %08X\n", mask, cur_mask);
debug(8, "%08X %08X\n", mask, cur_mask);
if (ninstr == 0)
return 0;
if (ninstr == 1)
{
/* Leaf holds instruction index. */
debug("%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
debug(8, "%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
*cur = LEAF_FLAG | last_match;
cur++;
nuncovered--;
505,18 → 501,18
for (len = best_len + 1; len < MIN(MAX_LEN, 33 - i); len++)
{
unsigned long m = (1UL << ((unsigned long)len)) - 1;
/*debug(" (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);*/
debug(9, " (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);
if ((m & (cur_mask >> (unsigned)i)) == m)
{
best_len = len;
best_first = i;
/*debug("!");*/
debug(9, "!");
}
else
break;
}
}
/*debug("\n");*/
debug(9, "\n");
if (!best_len)
{
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
527,7 → 523,7
fprintf (stderr, "\n");
exit (1);
}
debug("%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
debug(8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
*cur = best_first;
cur++;
*cur = (1 << best_len) - 1;
548,17 → 544,17
&& ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
ti[j].in_pass = curpass;
 
/*debug("%08X %08X %i\n", mask, cur_mask, best_first);*/
debug(9, "%08X %08X %i\n", mask, cur_mask, best_first);
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
if (c)
{
debug("%i> #%X -> %u\n", next - automata, i, cur - automata);
debug(8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
*next = cur - automata;
cur = c;
}
else
{
debug("%i> N/A\n", next - automata);
debug(8, "%i> N/A\n", next - automata);
*next = 0;
}
next++;
596,7 → 592,7
if (!(*args)) {
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
cur->data = 0;
debug("#%08X %08X\n", cur->type, cur->data);
debug(8, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
612,7 → 608,7
{
unsigned long arg;
arg = insn_extract(*args, opcode->encoding);
debug("%s : %08X ------\n", opcode->name, arg);
debug(3, "%s : %08X ------\n", opcode->name, arg);
if (letter_signed (*args))
{
type |= OPTYPE_SIG;
637,7 → 633,7
cur->type = type | shr;
cur->data = mask;
arg &= ~(((1 << mask) - 1) << shr);
debug("|%08X %08X\n", cur->type, cur->data);
debug(3, "|%08X %08X\n", cur->type, cur->data);
cur++;
}
args++;
647,7 → 643,7
/* Next param is displacement. Later we will treat them as one operand. */
cur--;
cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
657,7 → 653,7
{
cur--;
cur->type = type | cur->type | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
667,7 → 663,7
{
cur->type = type;
cur->data = 0;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
683,7 → 679,7
}
cur--;
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
debug("#%08X %08X\n", cur->type, cur->data);
debug(3, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
712,7 → 708,7
ti[i].insn_mask = ones | zeros;
ti[i].insn = ones;
ti[i].in_pass = curpass = 0;
/*debug("%s: %s %08X %08X\n", or32_opcodes[i].name,
/*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
}
758,19 → 754,19
while (!(*a & LEAF_FLAG))
{
unsigned int first = *a;
debug("%i ", a - automata);
debug(8, "%i ", a - automata);
a++;
i = (insn >> first) & *a;
a++;
if (!*(a + i))
{ /* Invalid instruction found? */
debug("XXX\n", i);
debug(8, "XXX\n", i);
return -1;
}
a = automata + *(a + i);
}
i = *a & ~LEAF_FLAG;
debug("%i\n", i);
debug(8, "%i\n", i);
/* Final check - do we have direct match?
(based on or32_opcodes this should be the only possibility,
but in case of invalid/missing instruction we must perform a check) */
/trunk/insight/opcodes/or32.c
29,10 → 29,6
#endif
#include "opcode/or32.h"
 
#ifndef debug
#define debug
#endif
 
/* **INDENT-OFF** */
 
CONST struct or32_letter or32_letters[] =
487,13 → 483,13
last_match = i;
}
debug("%08X %08X\n", mask, cur_mask);
debug(8, "%08X %08X\n", mask, cur_mask);
if (ninstr == 0)
return 0;
if (ninstr == 1)
{
/* Leaf holds instruction index. */
debug("%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
debug(8, "%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
*cur = LEAF_FLAG | last_match;
cur++;
nuncovered--;
505,18 → 501,18
for (len = best_len + 1; len < MIN(MAX_LEN, 33 - i); len++)
{
unsigned long m = (1UL << ((unsigned long)len)) - 1;
/*debug(" (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);*/
debug(9, " (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);
if ((m & (cur_mask >> (unsigned)i)) == m)
{
best_len = len;
best_first = i;
/*debug("!");*/
debug(9, "!");
}
else
break;
}
}
/*debug("\n");*/
debug(9, "\n");
if (!best_len)
{
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
527,7 → 523,7
fprintf (stderr, "\n");
exit (1);
}
debug("%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
debug(8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
*cur = best_first;
cur++;
*cur = (1 << best_len) - 1;
548,17 → 544,17
&& ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
ti[j].in_pass = curpass;
 
/*debug("%08X %08X %i\n", mask, cur_mask, best_first);*/
debug(9, "%08X %08X %i\n", mask, cur_mask, best_first);
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
if (c)
{
debug("%i> #%X -> %u\n", next - automata, i, cur - automata);
debug(8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
*next = cur - automata;
cur = c;
}
else
{
debug("%i> N/A\n", next - automata);
debug(8, "%i> N/A\n", next - automata);
*next = 0;
}
next++;
596,7 → 592,7
if (!(*args)) {
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
cur->data = 0;
debug("#%08X %08X\n", cur->type, cur->data);
debug(8, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
612,7 → 608,7
{
unsigned long arg;
arg = insn_extract(*args, opcode->encoding);
debug("%s : %08X ------\n", opcode->name, arg);
debug(3, "%s : %08X ------\n", opcode->name, arg);
if (letter_signed (*args))
{
type |= OPTYPE_SIG;
637,7 → 633,7
cur->type = type | shr;
cur->data = mask;
arg &= ~(((1 << mask) - 1) << shr);
debug("|%08X %08X\n", cur->type, cur->data);
debug(3, "|%08X %08X\n", cur->type, cur->data);
cur++;
}
args++;
647,7 → 643,7
/* Next param is displacement. Later we will treat them as one operand. */
cur--;
cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
657,7 → 653,7
{
cur--;
cur->type = type | cur->type | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
667,7 → 663,7
{
cur->type = type;
cur->data = 0;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
683,7 → 679,7
}
cur--;
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
debug("#%08X %08X\n", cur->type, cur->data);
debug(3, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
712,7 → 708,7
ti[i].insn_mask = ones | zeros;
ti[i].insn = ones;
ti[i].in_pass = curpass = 0;
/*debug("%s: %s %08X %08X\n", or32_opcodes[i].name,
/*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
}
758,19 → 754,19
while (!(*a & LEAF_FLAG))
{
unsigned int first = *a;
debug("%i ", a - automata);
debug(8, "%i ", a - automata);
a++;
i = (insn >> first) & *a;
a++;
if (!*(a + i))
{ /* Invalid instruction found? */
debug("XXX\n", i);
debug(8, "XXX\n", i);
return -1;
}
a = automata + *(a + i);
}
i = *a & ~LEAF_FLAG;
debug("%i\n", i);
debug(8, "%i\n", i);
/* Final check - do we have direct match?
(based on or32_opcodes this should be the only possibility,
but in case of invalid/missing instruction we must perform a check) */
/trunk/or1ksim/sim.cfg
96,8 → 96,10
verbose = 0/1
whether to print out extra messages
debug = 0/1
whether to print out sim debug information
debug = 0-9
= 0 disabled debug messages
1-9 level of sim debug information, greater the number more verbose is
the output
profile = 0/1
whether to generate profiling file 'sim.profile'
/trunk/or1ksim/cpu/or32/execute.c
102,7 → 102,7
if (delta < RAW_RANGE)
raw_stats.range[delta]++;
debug("atoi ret1\n");
debug(9, "atoi ret1\n");
return reg[regno];
} else {
printf("\nEXCEPTION: read out of registers\n");
250,7 → 250,7
 
unsigned long eval_operand32 (int op_no, int *breakpoint)
{
debug ("%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
return eval_mem32 (op[op_no], breakpoint);
else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG)
264,7 → 264,7
 
unsigned long eval_operand16 (int op_no, int *breakpoint)
{
debug ("%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
return eval_mem16 (op[op_no], breakpoint);
else {
278,7 → 278,7
 
unsigned long eval_operand8 (int op_no, int *breakpoint)
{
debug ("%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
return eval_mem8 (op[op_no], breakpoint);
else {
361,7 → 361,7
pc_phy = pc;
pcnext += 4;
ResetDebugUnit();
debug("reset ...");
debug(1, "reset ...\n");
/* MM1409: All programs should set their stack pointer! */
except_handle(EXCEPT_RESET, 0);
372,7 → 372,7
/* Fetch returns nonzero if instruction should NOT be executed. */
inline int fetch() {
struct mem_entry *entry;
debug("fetch()\n");
debug(5, "fetch()\n");
 
/* Do this here rather than update_pc so the reset exception
will happen normally. NOTE: During debugging and
667,7 → 667,7
mstats.bnez.backward++;
mstats.sbp_bf.all++;
if (flag) {
debug("\nl.bf relative: pc=%x pcnext=%x\n", pc, pcnext);
debug(5, "\nl.bf relative: pc=%x pcnext=%x\n", pc, pcnext);
pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
if (eval_operand32(0, &breakpoint) < pc)
801,13 → 801,13
set_operand32(0, eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint), &breakpoint);
}
void l_j() {
debug("\nl.j relative: pc=%x pcnext=%x\n", pc, pcnext);
debug(5, "\nl.j relative: pc=%x pcnext=%x\n", pc, pcnext);
pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
cur->func_unit = jump;
next_delay_insn = 1;
}
void l_jal() {
debug("\nl.jal relative: pc=%x pcnext=%x\n", pc, pcnext);
debug(5, "\nl.jal relative: pc=%x pcnext=%x\n", pc, pcnext);
pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
cur->func_unit = jump;
862,7 → 862,7
mstats.beqz.backward++;
mstats.sbp_bnf.all++;
if (flag == 0) {
debug("\nl.bnf relative: pc=%x pcnext=%x\n", pc, pcnext);
debug(5, "\nl.bnf relative: pc=%x pcnext=%x\n", pc, pcnext);
pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
mstats.beqz.taken++;
952,7 → 952,7
case 202:
stackaddr = eval_reg(4);
simprintf(stackaddr, eval_reg(3));
debug("simprintf %x %x %x\n", stackaddr, fmtaddr, args);
debug(5, "simprintf %x %x %x\n", stackaddr, fmtaddr, args);
break;
case 203:
printf("syscall exit(%d)\n", eval_reg (3));
/trunk/or1ksim/cpu/or32/or32.c
29,10 → 29,6
#endif
#include "opcode/or32.h"
 
#ifndef debug
#define debug
#endif
 
/* **INDENT-OFF** */
 
CONST struct or32_letter or32_letters[] =
487,13 → 483,13
last_match = i;
}
debug("%08X %08X\n", mask, cur_mask);
debug(8, "%08X %08X\n", mask, cur_mask);
if (ninstr == 0)
return 0;
if (ninstr == 1)
{
/* Leaf holds instruction index. */
debug("%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
debug(8, "%i>I%i %s\n", cur - automata, last_match, or32_opcodes[last_match].name);
*cur = LEAF_FLAG | last_match;
cur++;
nuncovered--;
505,18 → 501,18
for (len = best_len + 1; len < MIN(MAX_LEN, 33 - i); len++)
{
unsigned long m = (1UL << ((unsigned long)len)) - 1;
/*debug(" (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);*/
debug(9, " (%i(%08X & %08X>>%i = %08X, %08X)",len,m, cur_mask, i, (cur_mask >> (unsigned)i), (cur_mask >> (unsigned)i) & m);
if ((m & (cur_mask >> (unsigned)i)) == m)
{
best_len = len;
best_first = i;
/*debug("!");*/
debug(9, "!");
}
else
break;
}
}
/*debug("\n");*/
debug(9, "\n");
if (!best_len)
{
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
527,7 → 523,7
fprintf (stderr, "\n");
exit (1);
}
debug("%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
debug(8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len, best_first, ninstr);
*cur = best_first;
cur++;
*cur = (1 << best_len) - 1;
548,17 → 544,17
&& ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
ti[j].in_pass = curpass;
 
/*debug("%08X %08X %i\n", mask, cur_mask, best_first);*/
debug(9, "%08X %08X %i\n", mask, cur_mask, best_first);
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
if (c)
{
debug("%i> #%X -> %u\n", next - automata, i, cur - automata);
debug(8, "%i> #%X -> %u\n", next - automata, i, cur - automata);
*next = cur - automata;
cur = c;
}
else
{
debug("%i> N/A\n", next - automata);
debug(8, "%i> N/A\n", next - automata);
*next = 0;
}
next++;
596,7 → 592,7
if (!(*args)) {
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
cur->data = 0;
debug("#%08X %08X\n", cur->type, cur->data);
debug(8, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
612,7 → 608,7
{
unsigned long arg;
arg = insn_extract(*args, opcode->encoding);
debug("%s : %08X ------\n", opcode->name, arg);
debug(3, "%s : %08X ------\n", opcode->name, arg);
if (letter_signed (*args))
{
type |= OPTYPE_SIG;
637,7 → 633,7
cur->type = type | shr;
cur->data = mask;
arg &= ~(((1 << mask) - 1) << shr);
debug("|%08X %08X\n", cur->type, cur->data);
debug(3, "|%08X %08X\n", cur->type, cur->data);
cur++;
}
args++;
647,7 → 643,7
/* Next param is displacement. Later we will treat them as one operand. */
cur--;
cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
657,7 → 653,7
{
cur--;
cur->type = type | cur->type | OPTYPE_OP;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
667,7 → 663,7
{
cur->type = type;
cur->data = 0;
debug(">%08X %08X\n", cur->type, cur->data);
debug(3, ">%08X %08X\n", cur->type, cur->data);
cur++;
type = 0;
i++;
683,7 → 679,7
}
cur--;
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
debug("#%08X %08X\n", cur->type, cur->data);
debug(3, "#%08X %08X\n", cur->type, cur->data);
cur++;
return cur;
}
712,7 → 708,7
ti[i].insn_mask = ones | zeros;
ti[i].insn = ones;
ti[i].in_pass = curpass = 0;
/*debug("%s: %s %08X %08X\n", or32_opcodes[i].name,
/*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
}
758,19 → 754,19
while (!(*a & LEAF_FLAG))
{
unsigned int first = *a;
debug("%i ", a - automata);
debug(8, "%i ", a - automata);
a++;
i = (insn >> first) & *a;
a++;
if (!*(a + i))
{ /* Invalid instruction found? */
debug("XXX\n", i);
debug(8, "XXX\n", i);
return -1;
}
a = automata + *(a + i);
}
i = *a & ~LEAF_FLAG;
debug("%i\n", i);
debug(8, "%i\n", i);
/* Final check - do we have direct match?
(based on or32_opcodes this should be the only possibility,
but in case of invalid/missing instruction we must perform a check) */
/trunk/or1ksim/cpu/or16/execute.c
88,7 → 88,7
{
int regno;
debug("eval_reg(%s)\n", regstr);
debug(9, "eval_reg(%s)\n", regstr);
if (regstr && (*regstr == '%'))
regno = atoi(regstr + 2);
else
255,10 → 255,10
/* disp = atoi(operand); operand == "nn(rXX)" */
disp = strtol(operand, NULL, 0);
 
debug("eval_operand: disp=%u");
debug(9, "eval_operand: disp=%u\n");
regstr = strstr(operand, "(%r") + 1; /* regstr == "rXX)" */
*strstr(regstr, ")") = '\0'; /* regstr == "rXX" */
debug("eval_operand: regstr=%s", regstr);
debug(9, "eval_operand: regstr=%s\n", regstr);
memaddr = eval_reg(regstr) + disp;
return eval_mem32(memaddr,breakpoint);
275,7 → 275,7
{
char operand[OPERANDNAME_LEN];
debug("set_operand %s <= %u\n", dstoperand, value);
debug(9, "set_operand %s <= %u\n", dstoperand, value);
strcpy(operand, dstoperand);
 
if (*operand == '#') { /* immediate */
325,7 → 325,7
memset(icomplet, 0, sizeof(icomplet));
pctemp = eval_label("_main");
pc = pctemp;
debug("reset ...");
debug(1, "reset ...\n");
set_reg32(STACK_REG, MEMORY_LEN - STACK_SIZE);
}
 
582,7 → 582,7
strtol(cur->op1, &endptr, 0);
if (*endptr == '\0') {
debug("\nh.jmp relative: pc=%x pctemp=%x\n", pc, pctemp);
debug(4,"\nh.jmp relative: pc=%x pctemp=%x\n", pc, pctemp);
pctemp = pc + (signed)eval_operand(cur->op1,&breakpoint) - 2;
} else
pctemp = eval_operand(cur->op1,&breakpoint);
595,7 → 595,7
 
strtol(cur->op1, &endptr, 0);
if (*endptr == '\0') {
debug("\nh.jal relative: pc=%x pctemp=%x\n", pc, pctemp);
debug(4,"\nh.jal relative: pc=%x pctemp=%x\n", pc, pctemp);
pctemp = pc + (signed)eval_operand(cur->op1,&breakpoint) - 4;
} else
pctemp = eval_operand(cur->op1,&breakpoint);
629,7 → 629,7
strtol(cur->op1, &endptr, 0);
if (*endptr == '\0') {
debug("\nh.bf relative: pc=%x pctemp=%x\n", pc, pctemp);
debug(4,"\nh.bf relative: pc=%x pctemp=%x\n", pc, pctemp);
pctemp = pc + (signed)eval_operand(cur->op1,&breakpoint) - 2;
} else
pctemp = eval_operand(cur->op1,&breakpoint);
657,7 → 657,7
strtol(cur->op1, &endptr, 0);
if (*endptr == '\0') {
debug("\nh.bnf relative: pc=%x pctemp=%x\n", pc, pctemp);
debug(4,"\nh.bnf relative: pc=%x pctemp=%x\n", pc, pctemp);
pctemp = pc + (signed)eval_operand(cur->op1,&breakpoint) - 2;
} else
pctemp = eval_operand(cur->op1,&breakpoint);
1043,8 → 1043,8
if (strcmp(cur->insn, "h.shlai32") == 0) {
signed long temp1;
cur->func_unit = shift;
/* debug("shla: op3:%d op4:%d", eval_operand(cur->op3,&breakpoint), eval_operand(cur->o
debug("shla: op4=%s", cur->op4,&breakpoint); */
debug(9, "shla: op3:%d op4:%d\n", eval_operand(cur->op3,&breakpoint), eval_operand(cur->o
debug(9, "shla: op4=%s\n", cur->op4,&breakpoint); */
 
temp1 = eval_operand(cur->op1,&breakpoint);
temp1 <<= (0x001f & eval_operand(cur->op2,&breakpoint));
1088,8 → 1088,8
if (strcmp(cur->insn, "h.shla32") == 0) {
signed long temp1;
cur->func_unit = shift;
/* debug("shla: op3:%d op4:%d", eval_operand(cur->op3,&breakpoint), eval_operand(cur->op4,&breakpoint));
debug("shla: op4=%s", cur->op4); */
debug(9, "shla: op3:%d op4:%d\n", eval_operand(cur->op3,&breakpoint), eval_operand(cur->op4,&breakpoint));
debug(9, "shla: op4=%s\n", cur->op4);
 
temp1 = eval_operand(cur->op1,&breakpoint);
temp1 <<= (0x001f & eval_operand(cur->op2,&breakpoint));
1120,7 → 1120,7
stackaddr = eval_reg(FRAME_REG);
simprintf(stackaddr, eval_reg("r3"));
debug("simprintf %x %x %x\n", stackaddr, fmtaddr, args);
debug(3, "simprintf %x %x %x\n", stackaddr, fmtaddr, args);
/* Illegal opcode */
} else {
printf("\nEXCEPTION: illegal opcode %s ", cur->insn);
/trunk/or1ksim/cpu/common/stats.c
44,7 → 44,7
 
int check_depend()
{
debug("check_depend");
debug(2,"check_depend\n");
return depend_operands(&icomplet[0], &iqueue[0]);
}
 
73,7 → 73,7
{
int i = 0;
debug("adddstats start\n");
debug(3,"adddstats start\n");
 
while((strcmp(dstats[i].insn1, item1) || strcmp(dstats[i].insn2, item2)) &&
(strlen(dstats[i].insn1)) &&
/trunk/or1ksim/cpu/common/parse.c
154,7 → 154,7
char insn_first2_char[3];
int vaddr = (!config.filename) ? translate(address,breakpoint) : translate(freemem,breakpoint);
debug("addprogram 1\n");
debug(9,"addprogram 1\n");
 
setsim_mem32 (vaddr, insn);
 
248,7 → 248,7
 
/* loading section */
freemem = COFF_LONG_H(coffscnhdr.s_paddr);
debug("Starting to load at 0x%x", freemem);
debug(2,"Starting to load at 0x%x\n", freemem);
if (fseek(inputfs, COFF_LONG_H(coffscnhdr.s_scnptr), SEEK_SET) == -1) {
fclose(inputfs);
perror("readfile_coff");
260,10 → 260,10
if (len == 2)
{
fseek(inputfs, -2, SEEK_CUR);
debug("readfile_coff: %x 0x%x ", sectsize, insn >> 16);
debug(8,"readfile_coff: %x 0x%x \n", sectsize, insn >> 16);
}
else
debug("readfile_coff: %x 0x%x ", sectsize, insn);
debug(8,"readfile_coff: %x 0x%x \n", sectsize, insn);
addprogram (freemem, insn, &breakpoint);
sectsize -= len;
}
318,7 → 318,7
if (*((unsigned long *)coffsymhdr.e.e.e_zeroes)) {
if (strlen(coffsymhdr.e.e_name) && strlen(coffsymhdr.e.e_name) < 9)
add_label(COFF_LONG_H(coffsymhdr.e_value), coffsymhdr.e.e_name);
debug("[%i] Symbol: %s,", count++, coffsymhdr.e.e_name);
debug(8, "[%i] Symbol: %s,", count++, coffsymhdr.e.e_name);
} else {
long fpos = ftell (inputfs);
328,13 → 328,13
if ((*(s++) = fgetc(inputfs)) == 0) break;
tmp[32] = 0;
add_label(COFF_LONG_H(coffsymhdr.e_value), &tmp[0]);
debug("[%i] Symbol: %s,", count++, &tmp[0]);
debug(8, "[%i] Symbol: %s,", count++, &tmp[0]);
}
fseek(inputfs, fpos, SEEK_SET);
}
debug(" val: 0x%.8x,", COFF_LONG_H(coffsymhdr.e_value));
debug(" type: %x, %x, auxs: %i\n", COFF_SHORT_H(coffsymhdr.e_type), *((unsigned short *)coffsymhdr.e_type), n);
debug(9, " val: 0x%.8x,", COFF_LONG_H(coffsymhdr.e_value));
debug(9, " type: %x, %x, auxs: %i\n", COFF_SHORT_H(coffsymhdr.e_type), *((unsigned short *)coffsymhdr.e_type), n);
}
 
for (i = 0; i < n; i++)
/trunk/or1ksim/cpu/or1k/except.c
24,6 → 24,7
#include "abstract.h"
#include "except.h"
#include "sprs.h"
#include "sim-config.h"
 
static void except_handle_backend(int,unsigned long,unsigned long);
 
137,18 → 138,24
 
static void except_handle_backend(int except, unsigned long ea, unsigned long pc_saved)
{
pending.valid = 0;
pending.type = 0;
pending.address = 0;
pending.saved = 0;
/* Ignore masked exceptions */
if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
if (config.sim.verbose)
printf("INFO: Exception occured while exception detection was disabled.\n");
return;
}
pending.valid = 0;
pending.type = 0;
pending.address = 0;
pending.saved = 0;
 
#if ONLY_VIRTUAL_MACHINE
printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
cont_run = 0;
#else
 
if (delay_insn) {
printf(" INFO: Exception during execution of delay slot insn.\n");
printf("INFO: Exception during execution of delay slot insn.\n");
pc -= 4;
}
#if 0
159,12 → 166,6
execute();
}
#endif
 
if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
printf("ABORT: Exception occured while exception detection was disabled.\n");
cont_run = 0;
return;
}
pc_saved = pc & ~0x3;
mtspr(SPR_EPCR_BASE, pc_saved);
/trunk/or1ksim/testbench/Makefile.in
93,7 → 93,7
VERSION = @VERSION@
 
IND_TESTS = exit cbasic local_global mul mycompress dhry
OR1K_TESTS = basic cache excpt cfg dmatest eth # pic
OR1K_TESTS = basic cache excpt cfg dmatest eth acv_uart # pic
# Subdirectory tests
SUB_TESTS =
OR1K_SUB_TESTS = uos
137,6 → 137,8
@OR1K_EXCEPT_FALSE@dmatest_SOURCES =
@OR1K_EXCEPT_TRUE@eth_SOURCES = $(OR1K_SUPPORT_S) support.h eth.c
@OR1K_EXCEPT_FALSE@eth_SOURCES =
@OR1K_EXCEPT_TRUE@acv_uart_SOURCES = $(OR1K_SUPPORT_S) support.h acv_uart.c
@OR1K_EXCEPT_FALSE@acv_uart_SOURCES =
@OR1K_EXCEPT_TRUE@SUBDIRS = support $(SUB_TESTS) $(OR1K_SUB_TESTS)
@OR1K_EXCEPT_FALSE@SUBDIRS = support $(SUB_TESTS)
@OR1K_EXCEPT_TRUE@OR1K_SUPPORT_S = except.S
210,6 → 212,11
eth_LDADD = $(LDADD)
eth_DEPENDENCIES = support/libsupport.a
eth_LDFLAGS =
@OR1K_EXCEPT_TRUE@acv_uart_OBJECTS = except.o acv_uart.o
@OR1K_EXCEPT_FALSE@acv_uart_OBJECTS =
acv_uart_LDADD = $(LDADD)
acv_uart_DEPENDENCIES = support/libsupport.a
acv_uart_LDFLAGS =
COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
CCLD = $(CC)
LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(LDFLAGS) -o $@
222,11 → 229,12
TAR = gtar
GZIP_ENV = --best
DIST_SUBDIRS = support uos support
DEP_FILES = .deps/basic.P .deps/cache.P .deps/cbasic.P .deps/cfg.P \
.deps/dhry.P .deps/dmatest.P .deps/eth.P .deps/except.P .deps/excpt.P \
.deps/exit.P .deps/local_global.P .deps/mul.P .deps/mycompress.P
SOURCES = $(exit_SOURCES) $(cbasic_SOURCES) $(local_global_SOURCES) $(mul_SOURCES) $(mycompress_SOURCES) $(dhry_SOURCES) $(basic_SOURCES) $(cache_SOURCES) $(excpt_SOURCES) $(cfg_SOURCES) $(dmatest_SOURCES) $(eth_SOURCES)
OBJECTS = $(exit_OBJECTS) $(cbasic_OBJECTS) $(local_global_OBJECTS) $(mul_OBJECTS) $(mycompress_OBJECTS) $(dhry_OBJECTS) $(basic_OBJECTS) $(cache_OBJECTS) $(excpt_OBJECTS) $(cfg_OBJECTS) $(dmatest_OBJECTS) $(eth_OBJECTS)
DEP_FILES = .deps/acv_uart.P .deps/basic.P .deps/cache.P .deps/cbasic.P \
.deps/cfg.P .deps/dhry.P .deps/dmatest.P .deps/eth.P .deps/except.P \
.deps/excpt.P .deps/exit.P .deps/local_global.P .deps/mul.P \
.deps/mycompress.P
SOURCES = $(exit_SOURCES) $(cbasic_SOURCES) $(local_global_SOURCES) $(mul_SOURCES) $(mycompress_SOURCES) $(dhry_SOURCES) $(basic_SOURCES) $(cache_SOURCES) $(excpt_SOURCES) $(cfg_SOURCES) $(dmatest_SOURCES) $(eth_SOURCES) $(acv_uart_SOURCES)
OBJECTS = $(exit_OBJECTS) $(cbasic_OBJECTS) $(local_global_OBJECTS) $(mul_OBJECTS) $(mycompress_OBJECTS) $(dhry_OBJECTS) $(basic_OBJECTS) $(cache_OBJECTS) $(excpt_OBJECTS) $(cfg_OBJECTS) $(dmatest_OBJECTS) $(eth_OBJECTS) $(acv_uart_OBJECTS)
 
all: all-redirect
.SUFFIXES:
335,6 → 343,10
@rm -f eth
$(LINK) $(eth_LDFLAGS) $(eth_OBJECTS) $(eth_LDADD) $(LIBS)
 
acv_uart: $(acv_uart_OBJECTS) $(acv_uart_DEPENDENCIES)
@rm -f acv_uart
$(LINK) $(acv_uart_LDFLAGS) $(acv_uart_OBJECTS) $(acv_uart_LDADD) $(LIBS)
 
# This directory's subdirectories are mostly independent; you can cd
# into them and run `make' without going through this Makefile.
# To change the values of `make' variables: instead of editing Makefiles,
/trunk/or1ksim/testbench/except.S
34,7 → 34,7
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r0,lo(end_except)
l.lwz r10,_excpt_buserr(r0)
l.lwz r10,lo(_excpt_buserr)(r0)
l.jr r10
l.nop
 
154,7 → 154,7
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r0,lo(end_except)
l.lwz r10,_excpt_syscall(r0)
l.lwz r10,lo(_excpt_syscall)(r0)
l.jr r10
l.nop
 
/trunk/or1ksim/testbench/basic.s
3,7 → 3,8
 
#define 2 2
 
.section .reset
.section .except
.org 0x100
_reset:
l.nop
l.j _regs
/trunk/or1ksim/testbench/excpt.S
1,7 → 1,8
/* Test sys exceptions */
#include "support/spr_defs.h"
 
.section .reset
.section .except
.org 0x100
_reset:
l.addi r1,r0,0x7f00
l.jal _sys1
/trunk/or1ksim/testbench/acv_uart.c
0,0 → 1,237
/* UART test using ACV */
 
#include "spr_defs.h"
#include "support.h"
 
#define UART_ADDR (0x9c000000)
#define UART_RBR (UART_ADDR + 0)
#define UART_THR (UART_ADDR + 0)
#define UART_IER (UART_ADDR + 1)
#define UART_IIR (UART_ADDR + 2)
#define UART_FCR (UART_ADDR + 2)
#define UART_LCR (UART_ADDR + 3)
#define UART_MCR (UART_ADDR + 4)
#define UART_LSR (UART_ADDR + 5)
#define UART_MSR (UART_ADDR + 6)
 
#define UART_DLL (UART_ADDR + 0)
#define UART_DLH (UART_ADDR + 1)
 
#ifndef __LINE__
#define __LINE__ 0
#endif
 
/* fails if x is false */
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
/* Waits a few cycles that uart can prepare its data */
#define WAIT() {asm ("l.nop");asm ("l.nop");asm ("l.nop");asm ("l.nop");}
/* fails if there is an error */
#define NO_ERROR() { unsigned x = getreg (UART_LSR); if ((x & 0x1e) && !(x & 0x80)) printf ("LSR7 ERR\n"); ASSERT(!(x & 0x80));}
 
void fail (char *func, int line)
{
#ifndef __FUNCTION__
#define __FUNCTION__ "?"
#endif
printf ("Test failed in %s:%i\n", func, line);
exit (1);
}
 
inline void setreg (unsigned long addr, unsigned char value)
{
*((volatile unsigned char *)addr) = value;
}
 
inline unsigned long getreg (unsigned long addr)
{
return *((volatile unsigned char *)addr);
}
 
void interrupt_handler ()
{
printf ("Int\n");
}
 
/* Test reset values and r/w properties of some registers */
 
void register_test ()
{
printf ("register test\n");
{ /* test reset values */
ASSERT(getreg (UART_RBR) == 0x00); //0
ASSERT(getreg (UART_IER) == 0x00); //1
ASSERT(getreg (UART_IIR) == 0xc1); //2
ASSERT(getreg (UART_LCR) == 0x03); //3
ASSERT(getreg (UART_MCR) == 0x00); //4
ASSERT(getreg (UART_LSR) == 0x60); //5
ASSERT(getreg (UART_MSR) == 0x00); //6
 
setreg(UART_LCR, 0x80); //enable latches
ASSERT(getreg (UART_DLL) == 0x00); //0
ASSERT(getreg (UART_DLH) == 0x00); //1
setreg(UART_LCR, 0x00); //disable latches
}
 
{ /* test if status registers are read only */
unsigned long tmp;
int i;
tmp = getreg (UART_LSR);
setreg (UART_LSR, ~tmp);
ASSERT(getreg (UART_LSR) == tmp);
 
for (i = 0; i < 9; i++) {
setreg (UART_LSR, 1 < i);
ASSERT(getreg (UART_LSR) == tmp);
}
tmp = getreg (UART_MSR);
setreg (UART_MSR, ~tmp);
ASSERT(getreg (UART_MSR) == tmp);
for (i = 0; i < 9; i++) {
setreg (UART_MSR, 1 < i);
ASSERT(getreg (UART_MSR) == tmp);
}
}
ASSERT (!(getreg (UART_LSR) & 0x1f));
{ /* test whether MCR is write only, be careful not to set the loopback bit */
ASSERT(getreg (UART_MCR) == 0x00);
setreg (UART_MCR, 0x45);
ASSERT(getreg (UART_MCR) == 0x00);
setreg (UART_MCR, 0xaa);
ASSERT(getreg (UART_MCR) == 0x00);
}
ASSERT (!(getreg (UART_LSR) & 0x1f));
{ /* Test if Divisor latch byte holds the data */
int i;
setreg(UART_LCR, 0x80); //enable latches
ASSERT(getreg (UART_LCR) == 0x80);
for (i = 0; i < 16; i++) {
unsigned short tmp = 0xdead << i;
setreg (UART_DLH, tmp >> 8);
setreg (UART_DLL, tmp & 0xff);
ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
}
ASSERT (!(getreg (UART_LSR) & 0x1f));
for (i = 0; i < 16; i++) {
unsigned short tmp = 0xdead << i;
setreg (UART_DLL, tmp >> 8);
setreg (UART_DLH, tmp & 0xff);
ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
}
setreg(UART_LCR, 0x00); //disable latches
ASSERT(getreg (UART_LCR) == 0x00);
ASSERT (!(getreg (UART_LSR) & 0x1f));
}
{ /* Test LCR, if it holds our data */
int i;
for (i = 0; i < 6; i++) {
unsigned short tmp = (0xde << i) & 0x3f;
setreg (UART_LCR, tmp);
ASSERT(getreg (UART_LCR) == tmp);
}
ASSERT (!(getreg (UART_LSR) & 0x1f));
}
/* Other registers will be tested later, if they function correctly,
since we cannot test them now, without destroying anything. */
}
 
/* Initializes uart and sends a few bytes to VAPI. It is then activated and send something back. */
 
void send_recv_test ()
{
char *s;
printf ("send_recv_test");
/* Init */
setreg (UART_IER, 0x00); /* disable interrupts */
WAIT();
ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
setreg (UART_FCR, 0x06); /* clear RX and TX FIFOs */
setreg (UART_LCR, 0x80);
setreg (UART_DLH, 10 >> 8);
setreg (UART_DLL, 10 & 0xff);
setreg (UART_LCR, 0x83); /* 8N1 @ 10 => 160 instructions for one cycle */
ASSERT(getreg (UART_LCR) == 0x83);
printf ("basic\n");
ASSERT (!(getreg (UART_LSR) & 0x01));
 
/* Send a string */
s = "send_";
while (*s) {
/* Wait for tx fifo to be empty */
while (!(getreg (UART_LSR) & 0x20));
NO_ERROR();
setreg (UART_THR, *s); /* send character */
NO_ERROR();
s++;
}
ASSERT (!(getreg (UART_LSR) & 0x01));
s = "test_";
while (*s) {
/* Wait for tx fifo and tx to be empty */
while (!(getreg (UART_LSR) & 0x40));
NO_ERROR();
setreg (UART_THR, *s); /* send character */
NO_ERROR();
s++;
}
ASSERT (!(getreg (UART_LSR) & 0x01));
/* Send characters with delay inbetween */
s = "is_running";
while (*s) {
int i;
/* Wait for tx fifo and tx to be empty */
while (!(getreg (UART_LSR) & 0x40));
NO_ERROR();
setreg (UART_THR, *s); /* send character */
NO_ERROR();
for (i = 0; i < 1600; i++) /* wait at least ten chars before sending next one */
asm volatile ("l.nop");
s++;
}
/* Receives and compares the string */
s = "recv_test";
while (*s) {
/* Wait for rx fifo to be */
while (!(getreg (UART_LSR) & 0x01));
NO_ERROR();
ASSERT (getreg (UART_RBR) == *s); /* compare character */
NO_ERROR();
s++;
}
}
 
void loopback_test ()
{
printf ("loopback test\n");
setreg (UART_MCR, 0);
}
 
int main ()
{
/* Use our low priority interrupt handler */
excpt_lpint = (unsigned long)interrupt_handler;
/* Enable interrupts */
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR);
register_test ();
send_recv_test ();
/* break_test ();
different_modes_test ();
loopback_send_rcv_test ();
interrupt_test ();
fifo_test ();
loopback_test ();
modem_test ();
line_error_test ();
speed_error_test ();
frame_error_test ();
modem_error_test ();*/
return 0;
}
trunk/or1ksim/testbench/acv_uart.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/or1ksim/testbench/except.ld =================================================================== --- trunk/or1ksim/testbench/except.ld (revision 343) +++ trunk/or1ksim/testbench/except.ld (revision 344) @@ -1,6 +1,6 @@ MEMORY { - flash : ORIGIN = 0x00000100, LENGTH = 0x00001f00 + flash : ORIGIN = 0x00000000, LENGTH = 0x00001fff ram : ORIGIN = 0x00002000, LENGTH = 0x00010000 }
/trunk/or1ksim/testbench/cfg.S
1,7 → 1,8
/* Configuration tester */
#include "spr_defs.h"
.section .reset
.section .except
.org 0x100
_reset:
l.addi r1,r0,0x7f00
l.jal _main
/trunk/or1ksim/testbench/acv_uart.cfg
0,0 → 1,69
/* default.cfg -- Simulator testbench default configuration script file
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
section memory
memory_table_file = "simmem.cfg"
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
end
 
section cpu
ver = 0x1200
rev = 0x0001
/* upr = */
superscalar = 0
hazards = 0
history = 0
dependstats = 0
dependency = 0
slp = 0
btic = 0
bpb = 0
end
 
section sim
debug = 4
profile = 0
prof_fn = "sim.profile"
verbose = 1
/* iprompt = 0 */
exe_log = 0
exe_log_fn = "executed.log"
end
 
section uart
enabled = 1
nuarts = 1
device 0
baseaddr = 0x9c000000
jitter = -1 /* async behaviour */
16550 = 1
irq = 4
vapi_id = 0x00010000
enddevice
end
 
section VAPI
enabled = 0
server_port = 9998
end
trunk/or1ksim/testbench/acv_uart.cfg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/or1ksim/testbench/Makefile.am =================================================================== --- trunk/or1ksim/testbench/Makefile.am (revision 343) +++ trunk/or1ksim/testbench/Makefile.am (revision 344) @@ -22,7 +22,7 @@ ################### Tests ##################### # tests in this directory IND_TESTS = exit cbasic local_global mul mycompress dhry -OR1K_TESTS = basic cache excpt cfg dmatest eth # pic +OR1K_TESTS = basic cache excpt cfg dmatest eth acv_uart # pic # Subdirectory tests SUB_TESTS = OR1K_SUB_TESTS = uos @@ -57,6 +57,7 @@ pic_SOURCES = $(OR1K_SUPPORT_S) support.h pic.c dmatest_SOURCES = $(OR1K_SUPPORT_S) support.h dmatest.c eth_SOURCES = $(OR1K_SUPPORT_S) support.h eth.c +acv_uart_SOURCES = $(OR1K_SUPPORT_S) support.h acv_uart.c ################################################ else @@ -73,6 +74,7 @@ pic_SOURCES = dmatest_SOURCES = eth_SOURCES = +acv_uart_SOURCES = ############################################### endif
/trunk/or1ksim/peripheral/16450.c
67,30 → 67,23
{
int chipsel;
debug("uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
debug(4, "uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
 
for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
break;
else if (chipsel == NR_UARTS)
return;
if (chipsel >= NR_UARTS) return;
 
if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
switch (addr % UART_ADDR_SPACE) {
case UART_DLL:
uarts[chipsel].regs.dll = value;
break;
set_char_clks(chipsel);
return;
case UART_DLH:
uarts[chipsel].regs.dlh = value;
break;
case UART_LCR:
uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
break;
default:
debug("write out of range (addr %x, DLAB=1)\n", addr);
return;
}
set_char_clks(chipsel);
return;
}
switch (addr % UART_ADDR_SPACE) {
123,10 → 116,8
uarts[chipsel].regs.scr = value;
break;
default:
debug("write out of range (addr %x)\n", addr);
debug(1, "write out of range (addr %x)\n", addr);
}
set_char_clks(chipsel);
return;
}
 
/* Read a specific UART register. */
135,26 → 126,26
unsigned char value = 0;
int chipsel;
debug("uart_read_byte(%x)\n", addr);
debug(4, "uart_read_byte(%x)", addr);
for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
break;
else if (chipsel == NR_UARTS)
return 0;
 
if (chipsel >= NR_UARTS)
return 0;
 
if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
switch (addr % UART_ADDR_SPACE) {
case UART_DLL:
value = uarts[chipsel].regs.dll;
break;
debug(4, "= %x\n", value);
return value;
case UART_DLH:
value = uarts[chipsel].regs.dlh;
break;
default:
debug("read out of range (addr %x, DLAB=1)\n", addr);
debug(4, "= %x\n", value);
return value;
}
return value;
}
switch (addr % UART_ADDR_SPACE) {
174,7 → 165,7
value = uarts[chipsel].regs.ier & UART_VALID_IER;
break;
case UART_IIR:
value = uarts[chipsel].regs.iir & UART_VALID_IIR;
value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
uarts[chipsel].istat.thre_int = 0;
break;
case UART_LCR:
181,7 → 172,7
value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
break;
case UART_MCR:
value = uarts[chipsel].regs.mcr & UART_VALID_MCR;
value = 0;
break;
case UART_LSR:
value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
197,8 → 188,9
value = uarts[chipsel].regs.scr;
break;
default:
debug("read out of range (addr %x)\n", addr);
debug(1, "read out of range (addr %x)\n", addr);
}
debug(4, " = %x\n", value);
return value;
}
 
206,7 → 198,7
void uart_vapi_read (unsigned long id, unsigned long data)
{
int uart;
debug("UART: id %08x, data %08x\n", id, data);
debug(4, "UART: id %08x, data %08x\n", id, data);
uart = id & VAPI_DEVICE_ID;
uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_RX_BUF;
260,8 → 252,11
uarts[i].fifo_len = 16;
else
uarts[i].fifo_len = 1;
 
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
uarts[i].regs.lcr = UART_LCR_RESET;
}
}
 
291,7 → 286,7
} else
uarts[i].regs.lsr |= UART_LSR_TXSERE;
} else if (uarts[i].char_clks >= uarts[i].istat.txser_clks++) {
debug("TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
debug(8, "TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
if (uarts[i].regs.mcr & UART_MCR_LOOP)
uarts[i].iregs.loopback = uarts[i].iregs.txser;
else {
310,7 → 305,7
/* Receive */
if (uarts[i].istat.rxser_full) {
if (uarts[i].char_clks >= uarts[i].istat.rxser_clks++) {
debug("Receiving via UART%d...\n", i);
debug(8, "Receiving via UART%d...\n", i);
uarts[i].istat.rxser_full = 0;
uarts[i].istat.rxser_clks = 0;
345,7 → 340,7
/* Loopback */
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
debug("uart_clock: Loopback\n");
debug(5, "uart_clock: Loopback\n");
if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
uarts[i].regs.msr |= UART_MSR_DDCD;
419,7 → 414,7
printf("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
printf("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
printf("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
printf("Using IRQ%i", config.uarts[i].irq);
printf("Using IRQ%i\n", config.uarts[i].irq);
if (config.uarts[i].vapi_id)
printf ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
else
/trunk/or1ksim/peripheral/mc.c
43,7 → 43,7
{
int chipsel;
debug("mc_write_word(%x,%08x)\n", addr, (unsigned)value);
debug(5, "mc_write_word(%x,%08x)\n", addr, (unsigned)value);
 
addr -= config.mc.baseaddr;
68,7 → 68,7
set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);
break;
} else
debug("write out of range (addr %x)\n", addr + config.mc.baseaddr);
debug(1, "write out of range (addr %x)\n", addr + config.mc.baseaddr);
}
}
 
78,7 → 78,7
unsigned char value = 0;
int chipsel;
debug("mc_read_word(%x)\n", addr);
debug(5, "mc_read_word(%x)\n", addr);
 
addr -= config.mc.baseaddr;
 
100,7 → 100,7
else
value = mc.csc[addr >> 3];
} else
debug("read out of range (addr %x)\n", addr + config.mc.baseaddr);
debug(1, "read out of range (addr %x)\n", addr + config.mc.baseaddr);
break;
}
return value;
/trunk/or1ksim/peripheral/16450.h
89,7 → 89,7
#define UART_IER 1 /* R/W: Interrupt Enable Register */
#define UART_IIR 2 /* R: Interrupt ID Register */
#define UART_LCR 3 /* R/W: Line Control Register */
#define UART_MCR 4 /* R/W: Modem Control Register */
#define UART_MCR 4 /* W: Modem Control Register */
#define UART_LSR 5 /* R: Line Status Register */
#define UART_MSR 6 /* R: Modem Status Register */
#define UART_SCR 7 /* R/W: Scratch Register */
119,7 → 119,7
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
 
#define UART_LCR_RESET 0x03
/*
* Bit definitions for the Line Status Register
*/
/trunk/or1ksim/mmu/dmmu.c
136,7 → 136,7
/* Did we find our tlb entry? */
if (way >= 0) { /* Yes, we did. */
dmmu_stats.loads_tlbhit++;
debug("DTLB hit (virtaddr=%x).\n", virtaddr);
debug(5, "DTLB hit (virtaddr=%x).\n", virtaddr);
 
/* Set LRUs */
for (i = 0; i < DTLB_WAYS; i++)
/trunk/or1ksim/mmu/immu.c
136,7 → 136,7
/* Did we find our tlb entry? */
if (way >= 0) { /* Yes, we did. */
immu_stats.fetch_tlbhit++;
debug("ITLB hit (virtaddr=%x).\n", virtaddr);
debug(5, "ITLB hit (virtaddr=%x).\n", virtaddr);
 
/* Set LRUs */
for (i = 0; i < ITLB_WAYS; i++)
/trunk/or1ksim/toplevel.c
52,7 → 52,7
#include "gdbcomm.h"
 
/* CVS revision number. */
const char rcsrev[] = "$Revision: 1.44 $";
const char rcsrev[] = "$Revision: 1.45 $";
 
/* Continuos run versus single step tracing switch. */
int cont_run;
81,18 → 81,18
0
};
 
inline void debug(const char *format, ...)
inline void debug(int level, const char *format, ...)
{
char *p;
va_list ap;
 
if (config.sim.debug) {
if (config.sim.debug >= level) {
if ((p = malloc(1000)) == NULL)
return;
va_start(ap, format);
(void) vsnprintf(p, 1000, format, ap);
va_end(ap);
printf("%s\n", p);
printf("%s", p);
fflush(stdout);
free(p);
} else {
636,6 → 636,7
unsigned int addr;
if (cont_run > 0) cont_run--;
if(fetch()) {
printf ("Breakpoint hit.\n");
cont_run = 0; /* memory breakpoint encountered */
break;
}
/trunk/or1ksim/support/simprintf.c
65,7 → 65,7
 
simgetstr(stackaddr, regparam);
debug("simprintf: stackaddr: 0x%.8lx", stackaddr);
debug(6, "simprintf: stackaddr: 0x%.8lx\n", stackaddr);
if ((f = fopen("stdout.txt", "a+"))) {
unsigned long arg;
unsigned long argaddr;
78,14 → 78,14
#else
argaddr = 3;
#endif
debug("simprintf: %s", fmtstrpart);
debug(6, "simprintf: %s\n", fmtstrpart);
while(strlen(fmtstrpart)) {
debug("simprintf(): 1");
debug(6, "simprintf(): 1");
if ((fmtstrend = strstr(fmtstrpart + 1, "%")))
*fmtstrend = '\0';
debug(" 2");
debug(6," 2");
if (strstr(fmtstrpart, "%")) {
debug(" 3");
debug(6, " 3");
#if STACK_ARGS
arg = eval_mem32(argaddr,&breakpoint);
argaddr += 4;
93,7 → 93,7
sprintf(regstr, "r%u", ++argaddr);
arg = eval_reg(regstr);
#endif
debug(" 4: fmtstrpart=%p fmtstrpart=%s arg=%p", fmtstrpart, fmtstrpart, arg);
debug(6, " 4: fmtstrpart=%p fmtstrpart=%s arg=%p\n", fmtstrpart, fmtstrpart, arg);
if (strncmp(fmtstrpart, "%s", 2) == 0) {
int len = 0;
char *str;
105,26 → 105,26
for(; eval_mem8(arg,&breakpoint); len++)
*(str+len) = eval_mem8(arg++,&breakpoint);
*(str+len) = eval_mem8(arg,&breakpoint); /* null ch */
/* debug("4a: len=%d str=%s\n", len, str);
debug("4b:"); */
debug(6, "4a: len=%d str=%s\n", len, str);
debug(6, "4b:");
fprintf(f, fmtstrpart, str);
free(str);
} else
fprintf(f, fmtstrpart, arg);
} else {
debug(" 5");
debug(6, " 5");
fprintf(f, fmtstrpart);
debug(fmtstrpart);
debug(6, fmtstrpart);
}
if (!fmtstrend)
break;
debug(" 6");
debug(6, " 6");
fmtstrpart = fmtstrend;
*fmtstrpart = '%';
debug(" 7");
debug(6, " 7");
}
debug(" 8");
debug(6," 8\n");
if (fclose(f))
perror(strerror(errno));
}

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