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- from Rev 347 to Rev 348
- ↔ Reverse comparison
Rev 347 → Rev 348
/phr/trunk/codigo/implementaciones/fft/model/template/fparedes/fft_hdl2.m
0,0 → 1,88
function seg=fft_hdl2(b) |
close all |
clc |
%clear all |
global N; |
N=16; |
NB=24; |
step=1; |
forward=1; |
b=sin(2^-5*pi*(0:N-1))/5; |
%b=randn(1,N)/10; |
a=fi(b,1,NB,NB-1); |
|
|
ar=fi(bitrevorder(a.double),1,NB,NB-1,'OverflowMode','Saturate'); |
as=zeros(1,N); |
|
tf=fi(exp((-1)^forward*2*pi*1i*(0:N-1)/N),1,NB,NB-1,'OverflowMode','Saturate'); |
seg=ar.double; |
while step<=N/2 |
round(log2(step)); |
|
for j=0:step-1 |
i=1; |
while i<=N-j |
twiddle=tf(j*((N/2)/step)+1); |
x0=seg(i+j); |
x1=seg(i+j+step); |
|
prod=fi(twiddle.double * x1,1,NB,NB-round(log2(step+1)),'OverflowMode','Saturate'); |
|
y0 = fi(x0 + prod.double,1,NB,NB-1-round(log2(step)),'OverflowMode','Saturate'); |
y1 = fi(x0 - prod.double,1,NB,NB-1-round(log2(step)),'OverflowMode','Saturate'); |
seg(i+j)= y0.double; |
seg(i+j+step)=y1.double ; |
% disp(['xo: ' num2str(i+j)]) |
% disp(['x1: ' num2str(i+j+step)] ) |
% disp(['tf: ' num2str(j*((N/2)/step)+1)]) |
disp(['i:' num2str(i) ' - j:' num2str(j) ' - step:' num2str(step)]) |
%disp(['i:' num2str(i)]) |
%disp(['step:' num2str(step)]) |
%disp('----------') |
i=i+step*2; |
end |
end |
|
step=step*2; |
end |
|
|
if forward==0 |
seg=seg/N; |
else |
seg; |
end |
%as.double-fft(a.double) |
max(20*log10(abs(seg-fft(a.double)))) |
|
% Second algorithm |
disp('Second algorithm') |
for q=0:log2(N)-1 |
%disp(['step:' num2str(2^q)]); |
for w=1:N/2 |
%disp(['i:' num2str()]) |
ret_idx(q,w); |
end |
end |
|
return |
|
function [i,j]=ret_idx(step,end_count) |
global N; |
count=1; |
step=2^step; |
for j=0:step-1 |
i=1; |
while i<=N-j |
if (count==end_count) |
disp(['i:' num2str(i) ' - j:' num2str(j) ' - step:' num2str(step)]) |
return |
end |
count=count+1; |
i=i+step*2; |
|
end |
end |
|
return |
/phr/trunk/codigo/implementaciones/fft/doc/fft.pdf
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phr/trunk/codigo/implementaciones/fft/doc/fft.pdf
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+application/octet-stream
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Index: phr/trunk/codigo/implementaciones/fft/doc/vhdl_math_tricks_mapld_2003.pdf
===================================================================
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Index: phr/trunk/codigo/implementaciones/fft/doc/vhdl_math_tricks_mapld_2003.pdf
===================================================================
--- phr/trunk/codigo/implementaciones/fft/doc/vhdl_math_tricks_mapld_2003.pdf (nonexistent)
+++ phr/trunk/codigo/implementaciones/fft/doc/vhdl_math_tricks_mapld_2003.pdf (revision 348)
phr/trunk/codigo/implementaciones/fft/doc/vhdl_math_tricks_mapld_2003.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/fft.vhd
===================================================================
--- phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/fft.vhd (nonexistent)
+++ phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/fft.vhd (revision 348)
@@ -0,0 +1,100 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:59:21 11/02/2011
+-- Design Name:
+-- Module Name: fft - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+use work.misc.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fft is
+ Generic (NB : integer:=18;
+ N : integer:=32);
+ Port ( x_real : in signed (NB-1 downto 0);
+ x_imag : in signed (NB-1 downto 0);
+ x_adr : out unsigned(log2(N)-1 downto 0);
+ y_real : out signed (NB-1 downto 0);
+ y_imag : out signed (NB-1 downto 0);
+ y_adr : out unsigned(log2(N)-1 downto 0);
+ clk : in STD_LOGIC;
+ ce : in STD_LOGIC);
+end fft;
+
+architecture Behavioral of fft is
+
+
+--type arreglo_real is array(0 to log2(N)-1) of vector;
+--type arreglo_imag is array(0 to log2(N)-1) of vector;
+
+type vector is array(0 to N-1) of signed(NB-1 downto 0);
+type matriz is array(natural range 0 to log2(N)-1, natural range 0 to N-1 ) of signed(NB-1 downto 0);
+
+signal matriz_real : matriz;
+signal matriz_imag : matriz;
+signal tf_real : vector;
+signal tf_imag : vector;
+
+component butterfly
+ Generic (NB : integer :=18);
+ Port ( x0_real : in signed (NB-1 downto 0);
+ x0_imag : in signed (NB-1 downto 0);
+ x1_real : in signed (NB-1 downto 0);
+ x1_imag : in signed (NB-1 downto 0);
+ tf_real : in signed (NB-1 downto 0);
+ tf_imag : in signed (NB-1 downto 0);
+ y0_real : out signed (NB-1 downto 0);
+ y0_imag : out signed (NB-1 downto 0);
+ y1_real : out signed (NB-1 downto 0);
+ y1_imag : out signed (NB-1 downto 0);
+ clk : in STD_LOGIC);
+end component;
+
+begin
+
+depth:
+ for log_step in 0 to log2(N)-1 generate
+ begin
+ wide:
+ for bt_idx in 1 to N/2 generate
+ begin
+ but : butterfly
+ Generic Map(NB =>NB)
+ Port Map(
+ x0_real =>matriz_real(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)),
+ x0_imag =>matriz_imag(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)),
+ x1_real =>matriz_real(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)+2**log_step),
+ x1_imag =>matriz_real(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)+2**log_step),
+ tf_real =>tf_real(get_j*((N/2)/2**log_step)),
+ tf_imag =>tf_imag(get_j*((N/2)/2**log_step)),
+ y0_real =>matriz_real(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)),
+ y0_imag =>matriz_imag(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)),
+ y1_real =>matriz_real(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)+2**log_step),
+ y1_imag =>matriz_imag(log_step)(get_i(log_step,bt_idx,N)+get_j(log_step,bt_idx,N)+2**log_step),
+ clk =>clk);
+ end generate
+ end generate;
+
+
+end Behavioral;
+
Index: phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/butterfly.vhd
===================================================================
--- phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/butterfly.vhd (nonexistent)
+++ phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/butterfly.vhd (revision 348)
@@ -0,0 +1,86 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:51:03 11/02/2011
+-- Design Name:
+-- Module Name: butterfly - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity butterfly is
+ Generic (NB : integer :=18);
+ Port ( x0_real : in signed (NB-1 downto 0);
+ x0_imag : in signed (NB-1 downto 0);
+ x1_real : in signed (NB-1 downto 0);
+ x1_imag : in signed (NB-1 downto 0);
+ tf_real : in signed (NB-1 downto 0);
+ tf_imag : in signed (NB-1 downto 0);
+ y0_real : out signed (NB-1 downto 0);
+ y0_imag : out signed (NB-1 downto 0);
+ y1_real : out signed (NB-1 downto 0);
+ y1_imag : out signed (NB-1 downto 0);
+
+ clk : in STD_LOGIC);
+end butterfly;
+
+architecture Behavioral of butterfly is
+
+component complex_mult
+ Generic(NB : integer :=16);
+ Port ( a_real : in signed(NB-1 downto 0);
+ b_real : in signed (NB-1 downto 0);
+ a_imag : in signed (NB-1 downto 0);
+ b_imag : in signed (NB-1 downto 0);
+ o_real : out signed (NB-1 downto 0);
+ o_imag : out signed (NB-1 downto 0);
+ clk : in STD_LOGIC);
+end component;
+
+signal x1tf_real : signed (NB-1 downto 0);
+signal x1tf_imag : signed (NB-1 downto 0);
+
+begin
+
+twiddle_mult : complex_mult
+Generic Map(NB=>NB)
+Port Map(
+ a_real => x1_real,
+ b_real => tf_real,
+ a_imag => x1_imag,
+ b_imag => tf_imag,
+ o_real => x1tf_real,
+ o_imag => x1tf_imag,
+ clk => clk);
+process(clk)
+begin
+if rising_edge(clk) then
+ y0_real<=x0_real+x1tf_real;
+ y0_imag<=x0_imag+x1tf_imag;
+
+ y1_real<=x0_real-x1tf_real;
+ y1_real<=x0_imag-x1tf_imag;
+
+end if;
+end process;
+
+end Behavioral;
+
Index: phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/complex_mult.vhd
===================================================================
--- phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/complex_mult.vhd (nonexistent)
+++ phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/complex_mult.vhd (revision 348)
@@ -0,0 +1,78 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:25:36 11/02/2011
+-- Design Name:
+-- Module Name: complex_mult - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity complex_mult is
+ Generic(NB : integer :=16);
+ Port ( a_real : in signed(NB-1 downto 0);
+ b_real : in signed (NB-1 downto 0);
+ a_imag : in signed (NB-1 downto 0);
+ b_imag : in signed (NB-1 downto 0);
+ o_real : out signed (NB-1 downto 0);
+ o_imag : out signed (NB-1 downto 0);
+ clk : in STD_LOGIC);
+end complex_mult;
+
+architecture Behavioral of complex_mult is
+
+signal arbr_full : signed(2*NB-1 downto 0);
+signal arbi_full : signed(2*NB-1 downto 0);
+signal aibr_full : signed(2*NB-1 downto 0);
+signal aibi_full : signed(2*NB-1 downto 0);
+
+signal arbr : signed(2*NB-1 downto 0);
+signal arbi : signed(2*NB-1 downto 0);
+signal aibr : signed(2*NB-1 downto 0);
+signal aibi : signed(2*NB-1 downto 0);
+
+begin
+
+arbr_full <= a_real*b_real;
+arbi_full <= a_real*b_imag;
+aibr_full <= a_imag*b_real;
+aibi_full <= a_imag*b_imag;
+
+asignacion_de_productos : process(clk)
+begin
+ if rising_edge(clk) then
+ arbr <= arbr_full(2*NB-1 downto NB);
+ arbi <= arbi_full(2*NB-1 downto NB);
+ aibr <= aibr_full(2*NB-1 downto NB);
+ aibi <= aibi_full(2*NB-1 downto NB);
+ end if;
+end process asignacion_de_productos;
+
+asignacion_de_salida : process(clk)
+begin
+ if rising_edge(clk) then
+ o_real <= arbr - aibi;
+ o_imag <= arbi + aibr;
+ end if;
+end process asignacion_de_salida;
+
+end Behavioral;
+
Index: phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/misc.vhd
===================================================================
--- phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/misc.vhd (nonexistent)
+++ phr/trunk/codigo/implementaciones/fft/vhdl/template/fparedes/misc.vhd (revision 348)
@@ -0,0 +1,86 @@
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package misc is
+
+function log2 (n : in natural) return natural;
+function get_i(log_step : natural;
+ bt_idx : natural;
+ N : natural
+ ) return natural;
+
+function get_j(log_step : natural;
+ bt_idx : natural;
+ N : natural
+ ) return natural;
+
+end misc;
+
+
+package body misc is
+
+ function log2 (n : natural) return natural is
+ variable lc : natural:=0;
+ variable ni : natural;
+ begin
+ ni:=n;
+ while ni>1 loop
+ lc:=lc+1;
+ ni:=ni/2;
+ end loop;
+ return lc;
+ end function log2;
+
+
+ function get_i(log_step : natural;
+ bt_idx : natural;
+ N : natural
+ ) return natural is
+ variable i : natural;
+ variable j : natural;
+ variable step : natural;
+ variable cuenta : natural;
+ begin
+ cuenta:=1;
+ step:=2**log_step;
+ for j in 0 to step-1 loop
+ while i <= N-j loop
+ if cuenta=bt_idx then
+ return i;
+ end if;
+ cuenta:=cuenta+1;
+ i:=i+2*step;
+ end loop;
+ end loop;
+ return i;
+ end function get_i;
+
+ function get_j(log_step : natural;
+ bt_idx : natural;
+ N : natural
+ ) return natural is
+ variable i : natural;
+ variable j : natural;
+ variable step : natural;
+ variable cuenta : natural;
+ begin
+ cuenta:=1;
+ step:=2**log_step;
+ for j in 0 to step-1 loop
+ while i <= N-j loop
+ if cuenta=bt_idx then
+ return j;
+ end if;
+ cuenta:=cuenta+1;
+ i:=i+2*step;
+ end loop;
+ end loop;
+ return j;
+ end function get_j;
+end misc;