URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 348 to Rev 349
- ↔ Reverse comparison
Rev 348 → Rev 349
/trunk/or1ksim/cpu/or32/execute.c
419,7 → 419,8
|
if(!DEBUG_ENABLED && !OverrideFetch(&_insn)) |
{ |
_insn = eval_mem32 (pc_phy, &breakpoint); |
// _insn = eval_mem32 (pc_phy, &breakpoint); |
_insn = eval_insn (pc_phy, &breakpoint); |
iqueue[0].insn_addr = pc; |
} |
else |
444,7 → 445,7
pcnext = t_pcnext; |
|
/* Simulate instruction cache and IMMU. */ |
pc_phy = simulate_ic_mmu_fetch(pc); |
pc_phy = translate_vrt_to_phy_add(pc); |
|
if(!verify_memoryarea(pc_phy)) |
except_handle(EXCEPT_BUSERR, pc); |
/trunk/or1ksim/cpu/common/abstract.c
78,7 → 78,7
j++; |
} else { |
int breakpoint; |
unsigned int _insn = eval_mem32(i, &breakpoint); |
unsigned int _insn = read_mem(i, &breakpoint); |
int index = insn_decode (_insn); |
int len = insn_len (index); |
|
104,22 → 104,18
} |
} |
|
/* Calls IMMU translation routines before simulating insn |
cache for virtually indexed insn cache or after simulating insn cache |
for physically indexed insn cache. It returns physical address. */ |
|
unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr) |
/* It returns physical address. */ |
unsigned long translate_vrt_to_phy_add(unsigned long virtaddr) |
{ |
if (config.ic.tagtype == NONE) |
return virtaddr; |
else |
if (config.ic.tagtype == VIRTUAL) { |
ic_simulate_fetch(virtaddr); |
return immu_translate(virtaddr); |
} |
else if (config.dc.tagtype == PHYSICAL) { |
unsigned long phyaddr = immu_translate(virtaddr); |
ic_simulate_fetch(phyaddr); |
return phyaddr; |
} |
else { |
130,6 → 126,26
return -1; |
} |
|
/* Calls IMMU translation routines before simulating insn |
cache for virtually indexed insn cache or after simulating insn cache |
for physically indexed insn cache. It returns physical address. */ |
|
unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr) |
{ |
|
unsigned long phyaddr; |
|
if ((phyaddr = translate_vrt_to_phy_add(virtaddr)) != -1) { |
ic_simulate_fetch(phyaddr); |
return phyaddr; |
} |
else { |
printf("INTERNAL ERROR: Unknown insn cache type.\n"); |
cont_run = 0; |
} |
return -1; |
} |
|
/* Calls DMMU translation routines (load cycles) before simulating data |
cache for virtually indexed data cache or after simulating data cache |
for physically indexed data cache. It returns physical address. */ |
261,6 → 277,22
} |
|
/* Returns 32-bit values from mem array. Big endian version. */ |
unsigned long read_mem(unsigned long memaddr,int* breakpoint) |
{ |
|
unsigned long temp; |
struct dev_memarea *dev; |
|
slp_checkaccess(memaddr, SLP_MEMREAD); |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
temp = evalsim_mem32(memaddr); |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
return temp; |
} |
|
/* Returns 32-bit values from mem array. Big endian version. */ |
unsigned long eval_mem32(unsigned long memaddr,int* breakpoint) |
{ |
|
277,6 → 309,23
return temp; |
} |
|
/* Returns 32-bit values from mem array. Big endian version. */ |
unsigned long eval_insn(unsigned long memaddr,int* breakpoint) |
{ |
|
unsigned long temp; |
struct dev_memarea *dev; |
|
slp_checkaccess(memaddr, SLP_MEMREAD); |
memaddr = simulate_ic_mmu_fetch(memaddr); |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ |
temp = evalsim_mem32(memaddr); |
if (DEBUG_ENABLED) |
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ |
return temp; |
} |
|
unsigned long evalsim_mem32(unsigned long memaddr) |
{ |
unsigned long temp; |
/trunk/or1ksim/pic/pic.c
98,7 → 98,8
setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */ |
setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */ |
|
printf("Asserting interrupt %d.\n", line); |
/* printf("Asserting interrupt %d.\n", line); |
*/ |
if (getsprbit(SPR_PICMR, line) || line < 2) |
setsprbit(SPR_PICSR, line, 1); |
} |
/trunk/or1ksim/testbench/cache.c
186,9 → 186,7
unsigned long base, add; |
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base = (((unsigned long)&dummy / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE; |
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icache_enable(); |
|
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/* Copy jr to various location */ |
add = base; |
for(i = 0; i < IC_WAYS; i++) { |
235,6 → 233,8
/* Initilalize table index */ |
REG32(0) = 0; |
|
icache_enable(); |
|
/* Go */ |
call(base); |
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