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Rev 35 → Rev 36

/trunk/rtl/verilog/aeMB_core.v
1,5 → 1,5
/*
* $Id: aeMB_core.v,v 1.5 2007-04-27 00:23:55 sybreon Exp $
* $Id: aeMB_core.v,v 1.6 2007-05-17 09:08:21 sybreon Exp $
*
* AEMB 32-bit Microblaze Compatible Core
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
26,6 → 26,10
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.5 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
*
* Revision 1.4 2007/04/25 22:15:04 sybreon
* Added support for 8-bit and 16-bit data types.
*
80,8 → 84,8
wire drun; // From control of aeMB_control.v
wire frun; // From control of aeMB_control.v
wire nclk; // From control of aeMB_control.v
wire nrst; // From control of aeMB_control.v
wire nrun; // From control of aeMB_control.v
wire prst; // From control of aeMB_control.v
wire prun; // From control of aeMB_control.v
wire rBRA; // From decode of aeMB_decode.v
wire rDLY; // From decode of aeMB_decode.v
wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
132,9 → 136,9
.rLNK (rLNK),
.rRWE (rRWE),
.nclk (nclk),
.nrst (nrst),
.prst (prst),
.drun (drun),
.nrun (nrun));
.prun (prun));
 
aeMB_fetch #(ISIZ)
fetch (/*AUTOINST*/
146,8 → 150,8
// Inputs
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
.nrst (nrst),
.nrun (nrun),
.prst (prst),
.prun (prun),
.rFSM (rFSM[1:0]),
.rBRA (rBRA),
.rRESULT (rRESULT[31:0]));
157,8 → 161,8
// Outputs
.rFSM (rFSM[1:0]),
.nclk (nclk),
.nrst (nrst),
.nrun (nrun),
.prst (prst),
.prun (prun),
.frun (frun),
.drun (drun),
// Inputs
197,9 → 201,9
.rRA (rRA[4:0]),
.rMXLDST (rMXLDST[1:0]),
.nclk (nclk),
.nrst (nrst),
.prst (prst),
.drun (drun),
.nrun (nrun));
.prun (prun));
aeMB_decode
decode (/*AUTOINST*/
229,9 → 233,9
.rRESULT (rRESULT[31:0]),
.iwb_dat_i (iwb_dat_i[31:0]),
.nclk (nclk),
.nrst (nrst),
.prst (prst),
.drun (drun),
.frun (frun),
.nrun (nrun));
.prun (prun));
endmodule // aeMB_core
/trunk/rtl/verilog/aeMB_fetch.v
1,5 → 1,5
/*
* $Id: aeMB_fetch.v,v 1.4 2007-04-27 00:23:55 sybreon Exp $
* $Id: aeMB_fetch.v,v 1.5 2007-05-17 09:08:21 sybreon Exp $
*
* AEMB Instruction Fetch
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
25,6 → 25,10
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.4 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
*
* Revision 1.3 2007/04/11 04:30:43 sybreon
* Added pipeline stalling from incomplete bus cycles.
* Separated sync and async portions of code.
41,7 → 45,7
// Outputs
iwb_adr_o, iwb_stb_o, rPC, rIWBSTB,
// Inputs
iwb_dat_i, nclk, nrst, nrun, rFSM, rBRA, rRESULT
iwb_dat_i, nclk, prst, prun, rFSM, rBRA, rRESULT
);
parameter ISIZ = 32;
 
51,7 → 55,7
input [31:0] iwb_dat_i;
// System
input nclk, nrst, nrun;
input nclk, prst, prun;
// Internal
output [31:0] rPC;
87,14 → 91,14
 
// PIPELINE REGISTERS //////////////////////////////////////////////////
always @(negedge nclk or negedge nrst)
if (!nrst) begin
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rIWBADR <= 32'h0;
rPC <= 32'h0;
// End of automatics
end else if (nrun) begin
end else if (prun) begin
rPC <= #1 xPC;
rIWBADR <= #1 xIWBADR;
end
/trunk/rtl/verilog/aeMB_regfile.v
1,5 → 1,5
/*
* $Id: aeMB_regfile.v,v 1.16 2007-05-15 22:44:57 sybreon Exp $
* $Id: aeMB_regfile.v,v 1.17 2007-05-17 09:08:21 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
27,6 → 27,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.16 2007/05/15 22:44:57 sybreon
* Corrected speed issues after rev 1.9 update.
*
* Revision 1.15 2007/04/30 15:56:50 sybreon
* Removed byte acrobatics.
*
82,7 → 85,7
dwb_dat_o, rREGA, rREGB, sDWBDAT,
// Inputs
dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
rOPC, rDWBSEL, rLNK, rRWE, nclk, prst, drun, prun
);
// FIXME: This parameter is not used here.
parameter DSIZ = 32;
102,7 → 105,7
input [5:0] rOPC;
input [3:0] rDWBSEL;
input rLNK, rRWE;
input nclk, nrst, drun, nrun;
input nclk, prst, drun, prun;
 
/**
Delay Latches
162,12 → 165,10
reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
wire wDWE = (fLD | fLNK | fWE) & |rRD_ & nrun;
wire wDWE = (fLD | fLNK | fWE) & |rRD_ & prun;
assign wDDAT = (fLD) ? sDWBDAT :
(fLNK) ? {rPC_,2'd0} :
rRESULT;
//assign wWBDAT = (fDFWD) ? wRESULT : wREGD;
//assign wRESULT = (fMFWD) ? sDWBDAT : rRESULT;
assign rREGA = rMEMA[rRA];
assign rREGB = rMEMB[rRB];
174,7 → 175,7
assign wREGD = rMEMD[rRD];
always @(negedge nclk)
if (wDWE | !nrst) begin
if (wDWE | prst) begin
rMEMA[rRD_] <= wDDAT;
rMEMB[rRD_] <= wDDAT;
rMEMD[rRD_] <= wDDAT;
200,7 → 201,7
// 32-bit
3'o2, 3'o3: xDWBDAT <= wREGD;
3'o6, 3'o7: xDWBDAT <= rRESULT;
endcase // case (rOPC[1:0])
endcase // case ({fDFWD,rOPC[1:0]})
 
always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
case (rDWBSEL)
218,8 → 219,8
 
// PIPELINE REGISTERS //////////////////////////////////////////////////
always @(negedge nclk or negedge nrst)
if (!nrst) begin
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDAT <= 32'h0;
226,7 → 227,7
rPC_ <= 30'h0;
rRD_ <= 5'h0;
// End of automatics
end else if (nrun) begin
end else if (prun) begin
rDWBDAT <= #1 xDWBDAT;
rPC_ <= xPC_;
rRD_ <= xRD_;
/trunk/rtl/verilog/aeMB_control.v
1,5 → 1,5
/*
* $Id: aeMB_control.v,v 1.5 2007-05-16 12:32:21 sybreon Exp $
* $Id: aeMB_control.v,v 1.6 2007-05-17 09:08:21 sybreon Exp $
*
* AE68 System Control Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
24,6 → 24,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.5 2007/05/16 12:32:21 sybreon
* Added async BRA/DLY signals for future clock, reset, and interrupt features.
*
* Revision 1.4 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
42,7 → 45,7
 
module aeMB_control (/*AUTOARG*/
// Outputs
rFSM, nclk, nrst, nrun, frun, drun,
rFSM, nclk, prst, prun, frun, drun,
// Inputs
sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
rDWBSTB, dwb_ack_i, rBRA, rDLY
64,7 → 67,7
input rBRA, rDLY;
output [1:0] rFSM;
//, rLDST;
output nclk, nrst, nrun;
output nclk, prst, prun;
output frun, drun;
/**
74,36 → 77,23
will pause for any incomplete bus transaction.
*/
assign nrun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
assign prun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
 
/**
Debounce
--------
The following external signals are debounced and synchronised:
- Reset
- Interrupt
*/
reg [1:0] rRST;
always @(negedge nclk or negedge sys_rst_i)
if (!sys_rst_i) begin
//rNRST <= 2'h3;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rRST <= 2'h0;
// End of automatics
end else begin
rRST <= {rRST[0],1'b1};
end
 
reg [2:0] rEXC, rINT;
always @(negedge nclk or negedge nrst)
if (!nrst) begin
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rINT <= 3'h0;
// End of automatics
end else if (nrun) begin
end else if (prun) begin
//rEXC <= #1 {rEXC[1:0], sys_exc_i};
rINT <= #1 {rINT[1:0], sys_int_i};
end
124,13 → 114,13
FSM_HWINT = 2'o1;
reg [1:0] rFSM, rNXT;
always @(negedge nclk or negedge nrst)
if (!nrst) begin
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rFSM <= 2'h0;
// End of automatics
end else if (nrun) begin
end else if (prun) begin
rFSM <= #1 rNXT;
end
 
155,19 → 145,11
*/
reg [1:0] rRUN, xRUN;
assign {drun,frun} = rRUN;
assign {drun,frun} = xRUN;
 
always @(/*AUTOSENSE*/rBRA or rDLY) begin
xRUN <= {~(rBRA ^ rDLY), ~rBRA};
end
always @(posedge nclk or negedge nrst)
if (!nrst) begin
rRUN <= 2'h3;
/*AUTORESET*/
end else begin
rRUN <= #1 xRUN;
end
 
/**
Clock/Reset
176,8 → 158,17
DCM/PLL/DPLL can be instantiated here if needed.
*/
reg [1:0] rRST;
assign nclk = sys_clk_i;
assign nrst = rRST[1];
assign prst = rRST[1];
 
always @(negedge nclk)
if (!sys_rst_i) begin
rRST <= 2'h3;
/*AUTORESET*/
end else begin
rRST <= {rRST[0],1'b0};
end
 
endmodule // aeMB_control
/trunk/rtl/verilog/aeMB_decode.v
1,5 → 1,5
/*
* $Id: aeMB_decode.v,v 1.8 2007-04-30 15:58:31 sybreon Exp $
* $Id: aeMB_decode.v,v 1.9 2007-05-17 09:08:21 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
24,6 → 24,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.8 2007/04/30 15:58:31 sybreon
* Fixed minor data hazard bug spotted by Matt Ettus.
*
* Revision 1.7 2007/04/27 04:23:17 sybreon
* Removed some unnecessary bubble control.
*
54,8 → 57,8
rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rOPC, rIMM, rDWBSTB,
rDWBWE, rDLY, rLNK, rBRA, rRWE, rMXLDST, dwb_stb_o, dwb_we_o,
// Inputs
sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, nrst, drun,
frun, nrun
sDWBDAT, rDWBSEL, rREGA, rRESULT, iwb_dat_i, nclk, prst, drun,
frun, prun
);
// Internal I/F
output [31:0] rSIMM;
76,7 → 79,7
output dwb_stb_o, dwb_we_o;
// System I/F
input nclk, nrst, drun, frun, nrun;
input nclk, prst, drun, frun, prun;
 
/**
rOPC/rRD/rRA/rRB/rIMM
103,6 → 106,14
reg [5:0] xOPC;
reg [4:0] xRD, xRA, xRB;
reg [15:0] xIMM;
 
/*
assign rOPC = wOPC;
assign rRA = wRA;
assign rRB = wRB;
assign rRD = wRD;
assign rIMM = wIMM;
*/
always @(/*AUTOSENSE*/frun or wIMM or wOPC or wRA or wRB or wRD)
if (frun) begin
402,8 → 413,8
// PIPELINE REGISTERS ///////////////////////////////////////////////
 
always @(negedge nclk or negedge nrst)
if (!nrst) begin
always @(negedge nclk)
if (prst) begin
//rOPC <= 6'o40;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
430,7 → 441,7
rRWE <= 1'h0;
rSIMM <= 32'h0;
// End of automatics
end else if (nrun) begin // if (!nrst)
end else if (prun) begin // if (prst)
rIMM <= #1 xIMM;
rOPC <= #1 xOPC;
rRA <= #1 xRA;
457,7 → 468,7
rRWE <= #1 xRWE;
rDWBSTB <= #1 xDWBSTB;
rDWBWE <= #1 xDWBWE;
end // if (nrun)
end // if (prun)
endmodule // aeMB_decode
 
/trunk/rtl/verilog/aeMB_aslu.v
1,5 → 1,5
/*
* $Id: aeMB_aslu.v,v 1.8 2007-04-30 15:56:50 sybreon Exp $
* $Id: aeMB_aslu.v,v 1.9 2007-05-17 09:08:21 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
25,6 → 25,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.8 2007/04/30 15:56:50 sybreon
* Removed byte acrobatics.
*
* Revision 1.7 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
55,7 → 58,7
dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL,
// Inputs
sDWBDAT, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, nrst, drun, nrun
rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, prst, drun, prun
);
parameter DSIZ = 32;
 
76,7 → 79,7
input [4:0] rRD, rRA;
input [1:0] rMXLDST;
input nclk, nrst, drun, nrun;
input nclk, prst, drun, prun;
 
reg [31:0] rRESULT, xRESULT;
reg rMSR_C, xMSR_C;
258,8 → 261,8
// PIPELINE REGISTER //////////////////////////////////////////////////
always @(negedge nclk or negedge nrst)
if (!nrst) begin
always @(negedge nclk)
if (prst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBSEL <= 4'h0;
266,7 → 269,7
rMSR_C <= 1'h0;
rRESULT <= 32'h0;
// End of automatics
end else if (nrun) begin
end else if (prun) begin
rRESULT <= #1 xRESULT;
rMSR_C <= #1 xMSR_C;
rDWBSEL <= #1 xDWBSEL;

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