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Rev 35 → Rev 36

/trunk/rtl/verilog/can_top.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.15 2003/02/12 14:25:30 mohor
// abort_tx added.
//
165,12 → 168,14
wire reset_mode;
wire listen_only_mode;
wire acceptance_filter_mode;
wire sleep_mode;
wire self_test_mode;
 
/* Command register */
wire release_buffer;
wire tx_request;
wire abort_tx;
wire self_rx_request;
wire single_shot_transmission;
 
/* Bus Timing 0 register */
wire [5:0] baud_r_presc;
262,9 → 267,14
wire need_to_tx;
wire overrun;
wire info_empty;
wire go_error_frame;
wire priority_lost;
wire node_error_passive;
wire node_error_active;
 
 
 
 
/* Connecting can_registers module */
can_registers i_can_registers
(
290,12 → 300,17
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.go_error_frame(go_error_frame),
.priority_lost(priority_lost),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
 
 
/* Mode register */
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.sleep_mode(sleep_mode),
.self_test_mode(self_test_mode),
 
/* Command register */
.clear_data_overrun(),
302,7 → 317,8
.release_buffer(release_buffer),
.abort_tx(abort_tx),
.tx_request(tx_request),
.self_rx_request(),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
 
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
433,13 → 449,18
 
/* Mode register */
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
/* Command register */
.release_buffer(release_buffer),
.tx_request(tx_request),
.abort_tx(abort_tx),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
 
 
/* Error Warning Limit register */
.error_warning_limit(error_warning_limit),
 
467,6 → 488,10
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.go_error_frame(go_error_frame),
.priority_lost(priority_lost),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
/trunk/rtl/verilog/can_bsp.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.23 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.22 2003/02/12 14:23:59 mohor
// abort_tx added. Bit destuff fixed.
//
152,12 → 155,16
 
/* Mode register */
reset_mode,
listen_only_mode,
acceptance_filter_mode,
self_test_mode,
 
/* Command register */
release_buffer,
tx_request,
abort_tx,
self_rx_request,
single_shot_transmission,
 
/* Error Warning Limit register */
error_warning_limit,
185,8 → 192,13
need_to_tx,
overrun,
info_empty,
go_error_frame,
priority_lost,
node_error_passive,
node_error_active,
 
 
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
acceptance_code_0,
244,8 → 256,10
 
 
input reset_mode;
input listen_only_mode;
input acceptance_filter_mode;
input extended_mode;
input self_test_mode;
 
 
/* Command register */
252,6 → 266,8
input release_buffer;
input tx_request;
input abort_tx;
input self_rx_request;
input single_shot_transmission;
 
/* Error Warning Limit register */
input [7:0] error_warning_limit;
276,6 → 292,10
output need_to_tx;
output overrun;
output info_empty;
output go_error_frame;
output priority_lost;
output node_error_passive;
output node_error_active;
 
 
/* This section is for BASIC and EXTENDED mode */
438,7 → 458,6
wire go_rx_ack;
wire go_rx_ack_lim;
wire go_rx_eof;
wire go_error_frame;
wire go_overload_frame;
wire go_rx_inter;
 
464,7 → 483,7
wire stuff_err;
// of intermission, it starts reading the identifier (and transmitting its own).
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
// be send in a row. This is not implemented because host can not send an overload request. FIX ME !!!!
// be send in a row. This is not implemented because host can not send an overload request.
 
wire id_ok; // If received ID matches ID set in registers
wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
549,7 → 568,7
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
 
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state;
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
assign bit_err_exc1 = tx_state & arbitration_field & tx;
assign bit_err_exc2 = rx_ack & tx;
830,9 → 849,9
begin
if (rst)
byte_cnt <= 0;
else if (reset_mode | write_data_to_tmp_fifo)
else if (write_data_to_tmp_fifo)
byte_cnt <=#Tp byte_cnt + 1;
else if (sample_point & go_rx_crc_lim)
else if (reset_mode | (sample_point & go_rx_crc_lim))
byte_cnt <=#Tp 0;
end
 
1180,8 → 1199,7
wr_fifo <= 1'b0;
else if (reset_wr_fifo)
wr_fifo <=#Tp 1'b0;
else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
// else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) // FIX ME !!! This line is the correct one. The above line is for easier debugging only.
else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
wr_fifo <=#Tp 1'b1;
end
 
1441,7 → 1459,7
end
 
 
assign send_ack = (~tx_state) & rx_ack & (~err);
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
 
 
always @ (posedge clk or posedge rst)
1554,17 → 1572,17
end
end
 
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 38 ) | // arbitration + control for extended format
((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 18 ) | // arbitration + control for extended format
((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
( tx_point & rx_crc_lim ) | // crc
(go_rx_idle ) | // at the end
(reset_mode ) |
(overload_frame ) |
(error_frame ) ;
 
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & tx_pointer == 38 ) | // arbitration + control for extended format
((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
( tx_point & rx_crc_lim ) | // crc
(go_rx_idle ) | // at the end
(reset_mode ) |
(overload_frame ) |
(error_frame ) ;
 
always @ (posedge clk or posedge rst)
begin
if (rst)
1576,7 → 1594,7
end
 
 
assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~priority_lost);
assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~priority_lost) | single_shot_transmission);
 
 
always @ (posedge clk or posedge rst)
1591,8 → 1609,8
 
 
 
assign go_early_tx = need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_tx = need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
 
 
// Tx state
1702,23 → 1720,26
rx_err_cnt <=#Tp 'h0;
else
begin
if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
if (~listen_only_mode)
begin
if (rx_err_cnt > 127)
rx_err_cnt <=#Tp 127;
else
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
begin
if (rx_err_cnt > 127)
rx_err_cnt <=#Tp 127;
else
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
end
else if ((rx_err_cnt < 248) & (~transmitter)) // 248 + 8 = 256
begin
if (go_error_frame_q & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
(go_error_frame_q & rule5 ) | // 5
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
)
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
end
end
else if ((rx_err_cnt < 248) & (~transmitter)) // 248 + 8 = 256
begin
if (go_error_frame_q & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
(go_error_frame_q & rule5 ) | // 5
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
)
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
end
end
end
 
1771,6 → 1792,9
end
 
 
assign node_error_active = ~(node_error_passive | node_bus_off);
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
/trunk/rtl/verilog/can_registers.v
50,6 → 50,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14 2003/02/14 20:17:01 mohor
// Several registers added. Not finished, yet.
//
// Revision 1.13 2003/02/12 14:25:30 mohor
// abort_tx added.
//
125,6 → 128,10
need_to_tx,
overrun,
info_empty,
go_error_frame,
priority_lost,
node_error_passive,
node_error_active,
 
 
/* Mode register */
131,7 → 138,7
reset_mode,
listen_only_mode,
acceptance_filter_mode,
sleep_mode,
self_test_mode,
 
 
/* Command register */
140,6 → 147,7
abort_tx,
tx_request,
self_rx_request,
single_shot_transmission,
 
/* Bus Timing 0 register */
baud_r_presc,
234,6 → 242,10
input need_to_tx;
input overrun;
input info_empty;
input go_error_frame;
input priority_lost;
input node_error_passive;
input node_error_active;
 
 
 
241,7 → 253,7
output reset_mode;
output listen_only_mode;
output acceptance_filter_mode;
output sleep_mode;
output self_test_mode;
 
/* Command register */
output clear_data_overrun;
249,6 → 261,7
output abort_tx;
output tx_request;
output self_rx_request;
output single_shot_transmission;
 
/* Bus Timing 0 register */
output [5:0] baud_r_presc;
316,6 → 329,20
/* End: Tx data registers */
 
 
reg tx_successful_q;
reg overrun_q;
reg overrun_status;
reg transmission_complete;
reg transmit_buffer_status_q;
reg receive_buffer_status;
reg info_empty_q;
reg error_status_q;
reg node_bus_off_q;
reg priority_lost_q;
reg node_error_passive_q;
reg transmit_buffer_status;
reg single_shot_transmission;
 
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
wire data_overrun_irq_en;
wire error_warning_irq_en;
322,7 → 349,6
wire transmit_irq_en;
wire receive_irq_en;
 
reg transmit_buffer_status;
 
wire [7:0] irq_reg;
 
374,6 → 400,17
 
 
 
always @ (posedge clk)
begin
tx_successful_q <=#Tp tx_successful;
overrun_q <=#Tp overrun;
transmit_buffer_status_q <=#Tp transmit_buffer_status;
info_empty_q <=#Tp info_empty;
error_status_q <=#Tp error_status;
node_bus_off_q <=#Tp node_bus_off;
priority_lost_q <=#Tp priority_lost;
node_error_passive_q <=#Tp node_error_passive;
end
 
 
 
380,7 → 417,7
/* Mode register */
wire [0:0] mode;
wire [4:1] mode_basic;
wire [4:1] mode_ext;
wire [3:1] mode_ext;
wire receive_irq_en_basic;
wire transmit_irq_en_basic;
wire error_irq_en_basic;
403,10 → 440,10
.rst(rst)
);
 
can_register_asyn #(4, 0) MODE_REG_EXT
( .data_in(data_in[4:1]),
.data_out(mode_ext[4:1]),
.we(we_mode),
can_register_asyn #(3, 0) MODE_REG_EXT
( .data_in(data_in[3:1]),
.data_out(mode_ext[3:1]),
.we(we_mode & reset_mode),
.clk(clk),
.rst(rst)
);
413,8 → 450,8
 
assign reset_mode = mode[0];
assign listen_only_mode = mode_ext[1];
assign self_test_mode = mode_ext[2];
assign acceptance_filter_mode = mode_ext[3];
assign sleep_mode = mode_ext[4];
 
assign receive_irq_en_basic = mode_basic[1];
assign transmit_irq_en_basic = mode_basic[2];
443,20 → 480,43
.rst_sync(abort_tx & ~transmitting)
);
 
can_register_asyn_syn #(3, 3'h0) COMMAND_REG
( .data_in(data_in[4:2]),
.data_out(command[4:2]),
can_register_asyn_syn #(2, 2'h0) COMMAND_REG
( .data_in(data_in[3:2]),
.data_out(command[3:2]),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(|command[4:2])
.rst_sync(|command[3:2])
);
 
assign self_rx_request = command[4];
can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
( .data_in(data_in[4]),
.data_out(command[4]),
.we(we_command),
.clk(clk),
.rst(rst),
.rst_sync(tx_successful & (~tx_successful_q) | abort_tx)
);
 
assign self_rx_request = command[4] & (~command[0]);
assign clear_data_overrun = command[3];
assign release_buffer = command[2];
assign abort_tx = command[1];
assign tx_request = command[0];
assign abort_tx = command[1] & (~command[0]) & (~command[4]);
assign tx_request = command[0] | command[4];
 
 
always @ (posedge clk or posedge rst)
begin
if (rst)
single_shot_transmission <= 1'b0;
else if (we_command & data_in[1] & (data_in[1] | data_in[4]))
single_shot_transmission <=#Tp 1'b1;
else if (tx_successful & (~tx_successful_q))
single_shot_transmission <=#Tp 1'b0;
end
 
 
 
/* End Command register */
 
 
463,13 → 523,6
/* Status register */
 
wire [7:0] status;
reg tx_successful_q;
reg overrun_q;
reg overrun_status;
reg transmission_complete;
reg transmit_buffer_status_q;
reg receive_buffer_status;
reg info_empty_q;
 
assign status[7] = node_bus_off;
assign status[6] = error_status;
481,13 → 534,6
assign status[0] = receive_buffer_status;
 
 
always @ (posedge clk)
begin
tx_successful_q <=#Tp tx_successful;
overrun_q <=#Tp overrun;
transmit_buffer_status_q <=#Tp transmit_buffer_status;
info_empty_q <=#Tp info_empty;
end
 
always @ (posedge clk or posedge rst)
begin
525,7 → 571,7
always @ (posedge clk or posedge rst)
begin
if (rst)
receive_buffer_status <= 1'b1;
receive_buffer_status <= 1'b0;
else if (release_buffer)
receive_buffer_status <=#Tp 1'b0;
else if (~info_empty)
532,96 → 578,6
receive_buffer_status <=#Tp 1'b1;
end
 
/*
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn_syn #(1, 0) BUS_STATUS_REG_0
( .data_in(),
.data_out(status[0]),
.we(),
.clk(clk)
.rst(rst),
.rst_sync()
);
 
can_register_asyn #(1, 0) BUS_STATUS_REG_7
( .data_in(),
.data_out(status[7]),
.we(),
.clk(clk)
.rst(rst)
);
*/
/* End Status register */
 
 
963,7 → 919,7
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
begin
case(addr)
8'd0 : data_out <= {3'b000, mode_ext[4:1], mode[0]};
8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
8'd1 : data_out <= 8'h0;
8'd2 : data_out <= status;
8'd3 : data_out <= irq_reg;
1059,7 → 1015,7
always @ (posedge clk or posedge rst)
begin
if (rst)
receive_irq <= 1'b1;
receive_irq <= 1'b0;
else if (release_buffer)
receive_irq <=#Tp 1'b0;
else if ((~info_empty) & (~receive_irq) & receive_irq_en)
1067,13 → 1023,61
end
 
 
reg error_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
error_irq <= 1'b0;
else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
error_irq <=#Tp 1'b1;
else if (read_irq_reg)
error_irq <=#Tp 1'b0;
end
 
 
reg bus_error_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
bus_error_irq <= 1'b0;
else if (go_error_frame & bus_error_irq_en)
bus_error_irq <=#Tp 1'b1;
else if (read_irq_reg)
bus_error_irq <=#Tp 1'b0;
end
 
 
reg arbitration_lost_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
arbitration_lost_irq <= 1'b0;
else if (priority_lost & (~priority_lost_q) & arbitration_lost_irq_en)
arbitration_lost_irq <=#Tp 1'b1;
else if (read_irq_reg)
arbitration_lost_irq <=#Tp 1'b0;
end
 
 
 
reg error_passive_irq;
always @ (posedge clk or posedge rst)
begin
if (rst)
error_passive_irq <= 1'b0;
else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
error_passive_irq <=#Tp 1'b1;
else if (read_irq_reg)
error_passive_irq <=#Tp 1'b0;
end
 
 
 
// FIX ME !!!
assign irq_reg = {4'h0, data_overrun_irq, 1'b0, transmit_irq, 1'b0};
assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};
 
// FIX ME !!!
assign irq = data_overrun_irq | transmit_irq;
assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;
 
 
 

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