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    from Rev 35 to Rev 36
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Rev 35 → Rev 36

/trunk/generic_memories/rtl/verilog/generic_spram.v
67,6 → 67,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/11/08 19:32:59 samg
// corrected output: output not valid if ce low
//
// Revision 1.1.1.1 2001/09/14 09:57:09 rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
79,11 → 82,11
//
//
 
`include "timescale.v"
//`include "timescale.v"
 
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
//`define VENDOR_FPGA
 
module generic_spram(
// Generic synchronous single-port RAM interface
291,6 → 294,17
if (ce && we)
mem[addr] <= #1 di;
 
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [aw-1:0] start;
input [aw-1:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %h",rnum,mem[rnum]);
end
endtask
 
`endif // !VIRTUALSILICON_SSP
`endif // !VIRAGE_SSP
/trunk/generic_memories/rtl/verilog/generic_dpram.v
66,6 → 66,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/11/08 19:11:31 samg
// added valid checks to behvioral model
//
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
87,7 → 90,7
//
//
 
`include "timescale.v"
//`include "timescale.v"
 
//`define VENDOR_FPGA
//`define VENDOR_XILINX
323,7 → 326,7
 
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task ram_print;
task print_ram;
input [aw-1:0] start;
input [aw-1:0] finish;
integer rnum;
/trunk/generic_memories/rtl/verilog/generic_tpram.v
61,6 → 61,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/11/07 18:10:21 samg
// added checks and task in behavioral section
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
79,11 → 82,11
//
 
// synopsys translate_off
`include "timescale.v"
//`include "timescale.v"
// synopsys translate_on
`include "defines.v"
//`include "defines.v"
 
module generic_tpram_32x32(
module generic_tpram(
// Generic synchronous two-port RAM interface
clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
296,7 → 299,7
 
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task ram_print;
task print_ram;
input [aw-1:0] start;
input [aw-1:0] finish;
integer rnum;

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