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/trunk/pcores/fsl_dct_v1_00_a/hdl/vhdl/fsl_dct.vhd
0,0 → 1,194
------------------------------------------------------------------------------
-- fsl_dct - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: fsl_dct
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Fri Jul 21 08:31:12 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
 
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
 
entity fsl_dct is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
 
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
 
end fsl_dct;
 
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
 
-- In this section, we povide an example implementation of ENTITY fsl_dct
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY fsl_dct to implement your coprocessor
 
architecture EXAMPLE of fsl_dct is
 
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 8;
 
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 8;
 
type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);
 
signal state : STATE_TYPE;
 
-- Accumulator to hold sum of inputs read at any point in time
signal sum : std_logic_vector(0 to 31);
 
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
 
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's fsl_dct.c file
 
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0';
 
FSL_M_Data <= sum;
 
The_SW_accelerator : process (FSL_Clk) is
begin -- process The_SW_accelerator
if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= (others => '0');
else
case state is
when Idle =>
if (FSL_S_Exists = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= (others => '0');
end if;
 
when Read_Inputs =>
if (FSL_S_Exists = '1') then
-- Coprocessor function (Adding) happens here
sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
 
when Write_Outputs =>
if (nr_of_writes = 0) then
state <= Idle;
else
if (FSL_M_Full = '0') then
nr_of_writes <= nr_of_writes - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
/trunk/pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.pao
0,0 → 1,7
##############################################################################
## Filename: D:\mb-jpeg\pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Fri Jul 21 08:31:12 2006 (by Create and Import Peripheral Wizard)
##############################################################################
 
lib fsl_dct_v1_00_a fsl_dct vhdl
/trunk/pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.mpd
0,0 → 1,33
##############################################################################
## Filename: D:\mb-jpeg\pcores/fsl_dct_v1_00_a/data/fsl_dct_v2_1_0.mpd
## Description: Microprocessor Peripheral Description
## Date: Fri Jul 21 08:31:12 2006 (by Create and Import Peripheral Wizard)
##############################################################################
 
BEGIN fsl_dct
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION CORE_STATE = DEVELOPMENT
OPTION HDL = VHDL
 
## Bus Interfaces
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=MASTER
 
## Peripheral ports
PORT FSL_Clk = "", DIR=I, SIGIS=Clk, BUS=MFSL:SFSL
PORT FSL_Rst = OPB_Rst, DIR=I, BUS=MFSL:SFSL
PORT FSL_S_Clk = FSL_S_Clk, DIR=O, SIGIS=Clk, BUS=SFSL
PORT FSL_S_Read = FSL_S_Read, DIR=O, BUS=SFSL
PORT FSL_S_Data = FSL_S_Data, DIR=I, VEC=[0:31], BUS=SFSL
PORT FSL_S_Control = FSL_S_Control, DIR=I, BUS=SFSL
PORT FSL_S_Exists = FSL_S_Exists, DIR=I, BUS=SFSL
PORT FSL_M_Clk = FSL_M_Clk, DIR=O, SIGIS=Clk, BUS=MFSL
PORT FSL_M_Write = FSL_M_Write, DIR=O, BUS=MFSL
PORT FSL_M_Data = FSL_M_Data, DIR=O, VEC=[0:31], BUS=MFSL
PORT FSL_M_Control = FSL_M_Control, DIR=O, BUS=MFSL
PORT FSL_M_Full = FSL_M_Full, DIR=I, BUS=MFSL
 
END

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