URL
https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk
Subversion Repositories mkjpeg
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- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/mkjpeg/trunk/doc/JPEG.doc
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/mkjpeg/trunk/tb/wave.do
375,9 → 375,6
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/dbuf_data |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/dbuf_q |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/dbuf_we |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/rd_cnt |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/rd_en_d |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/rd_en |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/rle_runlength |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/rle_size |
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_rle_top/rle_amplitude |
410,21 → 407,30
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/rst |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/clk |
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/di |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/divalid |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/wr_cnt |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/start_pb |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/sof |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/rle_sm_settings |
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_rle_top/u_rle/runlength |
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_rle_top/u_rle/size |
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/amplitude |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/dovalid |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/rd_addr |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/prev_dc_reg_0 |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/prev_dc_reg_1 |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/prev_dc_reg_2 |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/acc_reg |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/size_reg |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/ampli_vli_reg |
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/ampli_vli_reg |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/runlength_reg |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/dovalid_reg |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/zero_cnt |
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_rle_top/u_rle/zero_cnt |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/wr_cnt_d1 |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/dovalid |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/runlength |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/size |
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/amplitude |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/wr_cnt |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/rd_cnt |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/u_rle/rd_en_d |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/rd_en |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/divalid |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rle/zrl_proc |
add wave -noupdate -divider HUFFMAN |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_huffman/clk |
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_huffman/rst |
563,7 → 569,7
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_outmux/ram_wren |
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_outmux/ram_wraddr |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 4} {444348 ps} 0} |
WaveRestoreCursors {{Cursor 4} {705443843 ps} 0} |
configure wave -namecolwidth 150 |
configure wave -valuecolwidth 55 |
configure wave -justifyvalue left |
578,4 → 584,4
configure wave -timeline 0 |
configure wave -timelineunits ps |
update |
WaveRestoreZoom {0 ps} {1050 ns} |
WaveRestoreZoom {705315540 ps} {705572146 ps} |
/mkjpeg/trunk/tb/COMPILE.do
74,6 → 74,8
vcom ../design/huffman/DoubleFifo.vhd |
vcom ../design/huffman/DC_ROM.vhd |
vcom ../design/huffman/AC_ROM.vhd |
vcom ../design/huffman/DC_CR_ROM.vhd |
vcom ../design/huffman/AC_CR_ROM.vhd |
vcom ../design/huffman/Huffman.vhd |
|
# bytestuffer |
/mkjpeg/trunk/tb/header.hex
211,6 → 211,39
FF |
C4 |
00 |
1F |
01 |
00 |
03 |
01 |
01 |
01 |
01 |
01 |
01 |
01 |
01 |
01 |
00 |
00 |
00 |
00 |
00 |
00 |
01 |
02 |
03 |
04 |
05 |
06 |
07 |
08 |
09 |
0A |
0B |
FF |
C4 |
00 |
B5 |
10 |
00 |
391,6 → 424,189
F8 |
F9 |
FA |
FF |
C4 |
00 |
B5 |
11 |
00 |
02 |
01 |
02 |
04 |
04 |
03 |
04 |
07 |
05 |
04 |
04 |
00 |
01 |
02 |
77 |
00 |
01 |
02 |
03 |
11 |
04 |
05 |
21 |
31 |
06 |
12 |
41 |
51 |
07 |
61 |
71 |
13 |
22 |
32 |
81 |
08 |
14 |
42 |
91 |
A1 |
B1 |
C1 |
09 |
23 |
33 |
52 |
F0 |
15 |
62 |
72 |
D1 |
0A |
16 |
24 |
34 |
E1 |
25 |
F1 |
17 |
18 |
19 |
1A |
26 |
27 |
28 |
29 |
2A |
35 |
36 |
37 |
38 |
39 |
3A |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
4A |
53 |
54 |
55 |
56 |
57 |
58 |
59 |
5A |
63 |
64 |
65 |
66 |
67 |
68 |
69 |
6A |
73 |
74 |
75 |
76 |
77 |
78 |
79 |
7A |
82 |
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85 |
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8A |
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9A |
A2 |
A3 |
A4 |
A5 |
A6 |
A7 |
A8 |
A9 |
AA |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
B8 |
B9 |
BA |
C2 |
C3 |
C4 |
C5 |
C6 |
C7 |
C8 |
C9 |
CA |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
D8 |
D9 |
DA |
E2 |
E3 |
E4 |
E5 |
E6 |
E7 |
E8 |
E9 |
EA |
F2 |
F3 |
F4 |
F5 |
F6 |
F7 |
F8 |
F9 |
FA |
FF |
DA |
00 |
399,9 → 615,9
01 |
00 |
02 |
00 |
11 |
03 |
11 |
00 |
00 |
3F |
00 |
/mkjpeg/trunk/tb/vhdl/HostBFM.vhd
346,15 → 346,15
|
constant qrom_chr : ROMQ_TYPE := |
( |
-- 50% for luminance! but used as chrominance, TODO!! |
X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E", |
X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28", |
X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25", |
X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33", |
X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44", |
X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57", |
X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71", |
X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63" |
-- 50% for chrominance |
X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A", |
X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63", |
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", |
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", |
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", |
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", |
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63", |
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63" |
); |
|
variable data_read : unsigned(31 downto 0); |
/mkjpeg/trunk/design/bytestuffer/ByteStuffer.vhd
94,9 → 94,7
|
huf_buf_sel <= huf_buf_sel_s; |
huf_rd_req <= huf_rd_req_s; |
|
num_enc_bytes <= std_logic_vector(wraddr); |
|
|
------------------------------------------------------------------- |
-- CTRL_SM |
------------------------------------------------------------------- |
201,6 → 199,19
end if; |
end if; |
end process; |
|
------------------------------------------------------------------- |
-- num_enc_bytes |
------------------------------------------------------------------- |
p_num_enc_bytes : process(CLK, RST) |
begin |
if RST = '1' then |
num_enc_bytes <= (others => '0'); |
elsif CLK'event and CLK = '1' then |
-- plus 2 for EOI marker last bytes |
num_enc_bytes <= std_logic_vector(wraddr + 2); |
end if; |
end process; |
|
|
end architecture RTL; |
/mkjpeg/trunk/design/rle/RLE.VHD
40,7 → 40,6
rst : in STD_LOGIC; |
clk : in STD_LOGIC; |
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); |
divalid : in STD_LOGIC; |
start_pb : in std_logic; |
sof : in std_logic; |
rle_sm_settings : in T_SM_SETTINGS; |
48,7 → 47,8
runlength : out STD_LOGIC_VECTOR(3 downto 0); |
size : out STD_LOGIC_VECTOR(3 downto 0); |
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); |
dovalid : out STD_LOGIC |
dovalid : out STD_LOGIC; |
rd_addr : out STD_LOGIC_VECTOR(5 downto 0) |
); |
end rle; |
|
67,104 → 67,166
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0); |
signal runlength_reg : UNSIGNED(3 downto 0); |
signal dovalid_reg : STD_LOGIC; |
signal zero_cnt : unsigned(3 downto 0); |
signal zero_cnt : unsigned(5 downto 0); |
signal wr_cnt_d1 : unsigned(5 downto 0); |
signal wr_cnt : unsigned(5 downto 0); |
|
signal rd_cnt : unsigned(5 downto 0); |
signal rd_en : std_logic; |
|
signal divalid : STD_LOGIC; |
signal zrl_proc : std_logic; |
signal zrl_proc_d1 : std_logic; |
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0); |
begin |
|
size <= STD_LOGIC_VECTOR(size_reg); |
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0)); |
|
rd_addr <= STD_LOGIC_VECTOR(rd_cnt); |
|
------------------------------------------- |
-- Counter1 |
------------------------------------------- |
process(clk,rst) |
begin |
if rst = '1' then |
rd_en <= '0'; |
rd_cnt <= (others => '0'); |
elsif clk = '1' and clk'event then |
if start_pb = '1' then |
rd_cnt <= (others => '0'); |
rd_en <= '1'; |
end if; |
|
-- input read enable |
if rd_en = '1' and zrl_proc = '0' then |
if rd_cnt = 64-1 then |
rd_cnt <= (others => '0'); |
rd_en <= '0'; |
else |
rd_cnt <= rd_cnt + 1; |
end if; |
end if; |
end if; |
end process; |
|
------------------------------------------- |
-- MAIN PROCESSING |
------------------------------------------- |
process(clk) |
process(clk,rst) |
begin |
if clk = '1' and clk'event then |
if rst = '1' then |
wr_cnt_d1 <= (others => '0'); |
prev_dc_reg_0 <= (others => '0'); |
prev_dc_reg_1 <= (others => '0'); |
prev_dc_reg_2 <= (others => '0'); |
dovalid_reg <= '0'; |
acc_reg <= (others => '0'); |
runlength_reg <= (others => '0'); |
runlength <= (others => '0'); |
dovalid <= '0'; |
zero_cnt <= (others => '0'); |
else |
dovalid_reg <= '0'; |
runlength_reg <= (others => '0'); |
|
wr_cnt_d1 <= wr_cnt; |
runlength <= std_logic_vector(runlength_reg); |
dovalid <= dovalid_reg; |
|
-- input data valid |
if divalid = '1' then |
wr_cnt <= wr_cnt + 1; |
|
-- first DCT coefficient received, DC data |
if wr_cnt = 0 then |
-- differental coding of DC data per component |
case rle_sm_settings.cmp_idx is |
when "00" => |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1); |
prev_dc_reg_0 <= SIGNED(di); |
when "01" => |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1); |
prev_dc_reg_1 <= SIGNED(di); |
when "10" => |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1); |
prev_dc_reg_2 <= SIGNED(di); |
when others => |
null; |
end case; |
runlength_reg <= (others => '0'); |
dovalid_reg <= '1'; |
-- AC coefficient |
if rst = '1' then |
wr_cnt_d1 <= (others => '0'); |
prev_dc_reg_0 <= (others => '0'); |
prev_dc_reg_1 <= (others => '0'); |
prev_dc_reg_2 <= (others => '0'); |
dovalid_reg <= '0'; |
acc_reg <= (others => '0'); |
runlength_reg <= (others => '0'); |
runlength <= (others => '0'); |
dovalid <= '0'; |
zero_cnt <= (others => '0'); |
zrl_proc <= '0'; |
zrl_proc_d1 <= '0'; |
elsif clk = '1' and clk'event then |
dovalid_reg <= '0'; |
runlength_reg <= (others => '0'); |
wr_cnt_d1 <= wr_cnt; |
runlength <= std_logic_vector(runlength_reg); |
dovalid <= dovalid_reg; |
divalid <= rd_en; |
zrl_proc_d1 <= zrl_proc; |
|
-- input data valid |
if divalid = '1' and zrl_proc_d1 = '0' then |
wr_cnt <= wr_cnt + 1; |
|
-- first DCT coefficient received, DC data |
if wr_cnt = 0 then |
-- differental coding of DC data per component |
case rle_sm_settings.cmp_idx is |
when "00" => |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1); |
prev_dc_reg_0 <= SIGNED(di); |
when "01" => |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1); |
prev_dc_reg_1 <= SIGNED(di); |
when "10" => |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1); |
prev_dc_reg_2 <= SIGNED(di); |
when others => |
null; |
end case; |
runlength_reg <= (others => '0'); |
dovalid_reg <= '1'; |
-- AC coefficient |
else |
-- zero AC |
if signed(di) = 0 then |
-- EOB |
if wr_cnt = 63 then |
acc_reg <= (others => '0'); |
runlength_reg <= (others => '0'); |
dovalid_reg <= '1'; |
-- no EOB |
else |
zero_cnt <= zero_cnt + 1; |
end if; |
-- non-zero AC |
else |
-- zero AC |
if signed(di) = 0 then |
-- EOB |
if wr_cnt = 63 then |
acc_reg <= (others => '0'); |
runlength_reg <= (others => '0'); |
dovalid_reg <= '1'; |
-- zero extension symbol |
elsif zero_cnt = 15 then |
acc_reg <= (others => '0'); |
runlength_reg <= to_unsigned(15, runlength_reg'length); |
dovalid_reg <= '1'; |
zero_cnt <= (others => '0'); |
-- zero_cnt < 15 and no EOB |
else |
zero_cnt <= zero_cnt + 1; |
end if; |
-- non-zero AC |
else |
-- normal RLE case |
if zero_cnt <= 15 then |
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1); |
runlength_reg <= zero_cnt; |
runlength_reg <= zero_cnt(3 downto 0); |
zero_cnt <= (others => '0'); |
dovalid_reg <= '1'; |
-- zero_cnt > 15 |
else |
-- generate ZRL |
acc_reg <= (others => '0'); |
runlength_reg <= X"F"; |
zero_cnt <= zero_cnt - 16; |
dovalid_reg <= '1'; |
-- stall input until ZRL is handled |
zrl_proc <= '1'; |
zrl_di <= di; |
end if; |
end if; |
end if; |
|
-- start of 8x8 block processing |
if start_pb = '1' then |
zero_cnt <= (others => '0'); |
wr_cnt <= (others => '0'); |
end if; |
|
if sof = '1' then |
prev_dc_reg_0 <= (others => '0'); |
prev_dc_reg_1 <= (others => '0'); |
prev_dc_reg_2 <= (others => '0'); |
end if; |
end if; |
|
-- ZRL processing |
if zrl_proc = '1' then |
if zero_cnt <= 15 then |
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1); |
runlength_reg <= zero_cnt(3 downto 0); |
zero_cnt <= (others => '0'); |
dovalid_reg <= '1'; |
-- continue input handling |
zrl_proc <= '0'; |
-- zero_cnt > 15 |
else |
-- generate ZRL |
acc_reg <= (others => '0'); |
runlength_reg <= X"F"; |
zero_cnt <= zero_cnt - 16; |
dovalid_reg <= '1'; |
end if; |
end if; |
|
-- start of 8x8 block processing |
if start_pb = '1' then |
zero_cnt <= (others => '0'); |
wr_cnt <= (others => '0'); |
end if; |
|
if sof = '1' then |
prev_dc_reg_0 <= (others => '0'); |
prev_dc_reg_1 <= (others => '0'); |
prev_dc_reg_2 <= (others => '0'); |
end if; |
|
end if; |
end if; |
end process; |
|
/mkjpeg/trunk/design/rle/RLE_TOP.VHD
81,10 → 81,6
signal dbuf_q : std_logic_vector(19 downto 0); |
signal dbuf_we : std_logic; |
|
signal rd_cnt : unsigned(5 downto 0); |
signal rd_en_d : std_logic_vector(5 downto 0); |
signal rd_en : std_logic; |
|
signal rle_runlength : std_logic_vector(3 downto 0); |
signal rle_size : std_logic_vector(3 downto 0); |
signal rle_amplitude : std_logic_vector(11 downto 0); |
102,7 → 98,6
------------------------------------------------------------------------------- |
begin |
|
qua_rd_addr <= std_logic_vector(rd_cnt); |
huf_runlength <= dbuf_q(19 downto 16); |
huf_size <= dbuf_q(15 downto 12); |
huf_amplitude <= dbuf_q(11 downto 0); |
122,7 → 117,6
rst => RST, |
clk => CLK, |
di => rle_di, |
divalid => rle_divalid, |
start_pb => start_pb, |
sof => sof, |
rle_sm_settings => rle_sm_settings, |
130,11 → 124,11
runlength => rle_runlength, |
size => rle_size, |
amplitude => rle_amplitude, |
dovalid => rle_dovalid |
dovalid => rle_dovalid, |
rd_addr => qua_rd_addr |
); |
|
rle_di <= qua_data; |
rle_divalid <= rd_en_d(0); |
|
------------------------------------------------------------------- |
-- Double Fifo |
157,35 → 151,8
dbuf_we <= rle_dovalid; |
|
|
------------------------------------------------------------------- |
-- Counter1 |
------------------------------------------------------------------- |
p_counter1 : process(CLK, RST) |
begin |
if RST = '1' then |
rd_en <= '0'; |
rd_en_d <= (others => '0'); |
rd_cnt <= (others => '0'); |
elsif CLK'event and CLK = '1' then |
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en; |
|
if start_pb = '1' then |
rd_cnt <= (others => '0'); |
rd_en <= '1'; |
end if; |
|
if rd_en = '1' then |
if rd_cnt = 64-1 then |
rd_cnt <= (others => '0'); |
rd_en <= '0'; |
else |
rd_cnt <= rd_cnt + 1; |
end if; |
end if; |
|
end if; |
end process; |
|
|
------------------------------------------------------------------- |
-- ready_pb |
------------------------------------------------------------------- |
/mkjpeg/trunk/design/top/JpegEnc.vhd
406,6 → 406,7
-- CTRL |
start_pb => huf_start, |
ready_pb => huf_ready, |
huf_sm_settings => huf_sm_settings, |
|
-- HOST IF |
sof => sof, |
422,7 → 423,6
d_val => huf_dval, |
rle_fifo_empty => huf_fifo_empty, |
|
|
-- Byte Stuffer |
bs_buf_sel => bs_buf_sel, |
bs_fifo_empty => bs_fifo_empty, |
/mkjpeg/trunk/design/huffman/Huffman.vhd
34,7 → 34,8
------------------------------------------------------------------------------- |
-- user packages/libraries: |
------------------------------------------------------------------------------- |
|
library work; |
use work.JPEG_PKG.all; |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- ENTITY ------------------------------------ |
48,6 → 49,7
-- CTRL |
start_pb : in std_logic; |
ready_pb : out std_logic; |
huf_sm_settings : in T_SM_SETTINGS; |
|
-- HOST IF |
sof : in std_logic; |
121,6 → 123,10
signal rd_en_s : std_logic; |
signal pad_byte : std_logic_vector(7 downto 0); |
signal pad_reg : std_logic; |
signal VLC_CR_DC_size : std_logic_vector(3 downto 0); |
signal VLC_CR_DC : unsigned(10 downto 0); |
signal VLC_CR_AC_size : unsigned(4 downto 0); |
signal VLC_CR_AC : unsigned(15 downto 0); |
|
------------------------------------------------------------------------------- |
-- Architecture: begin |
149,7 → 155,7
end process; |
|
------------------------------------------------------------------- |
-- DC_ROM |
-- DC_ROM Luminance |
------------------------------------------------------------------- |
U_DC_ROM : entity work.DC_ROM |
port map |
163,7 → 169,7
); |
|
------------------------------------------------------------------- |
-- AC_ROM |
-- AC_ROM Luminance |
------------------------------------------------------------------- |
U_AC_ROM : entity work.AC_ROM |
port map |
176,6 → 182,35
VLC_AC_size => VLC_AC_size, |
VLC_AC => VLC_AC |
); |
|
------------------------------------------------------------------- |
-- DC_ROM Chrominance |
------------------------------------------------------------------- |
U_DC_CR_ROM : entity work.DC_CR_ROM |
port map |
( |
CLK => CLK, |
RST => RST, |
VLI_size => VLI_size, |
|
VLC_DC_size => VLC_CR_DC_size, |
VLC_DC => VLC_CR_DC |
); |
|
------------------------------------------------------------------- |
-- AC_ROM Chrominance |
------------------------------------------------------------------- |
U_AC_CR_ROM : entity work.AC_CR_ROM |
port map |
( |
CLK => CLK, |
RST => RST, |
runlength => runlength, |
VLI_size => VLI_size, |
|
VLC_AC_size => VLC_CR_AC_size, |
VLC_AC => VLC_CR_AC |
); |
|
------------------------------------------------------------------- |
-- Double Fifo |
210,7 → 245,7
end process; |
|
------------------------------------------------------------------- |
-- mux for DC/AC ROM |
-- mux for DC/AC ROM Luminance/Chrominance |
------------------------------------------------------------------- |
p_mux : process(CLK, RST) |
begin |
218,12 → 253,28
VLC_size <= (others => '0'); |
VLC <= (others => '0'); |
elsif CLK'event and CLK = '1' then |
-- DC |
if first_rle_word = '1' then |
VLC_size <= unsigned('0' & VLC_DC_size); |
VLC <= resize(VLC_DC, VLC'length); |
-- luminance |
if huf_sm_settings.cmp_idx = 0 then |
VLC_size <= unsigned('0' & VLC_DC_size); |
VLC <= resize(VLC_DC, VLC'length); |
-- chrominance |
else |
VLC_size <= unsigned('0' & VLC_CR_DC_size); |
VLC <= resize(VLC_CR_DC, VLC'length); |
end if; |
-- AC |
else |
VLC_size <= VLC_AC_size; |
VLC <= VLC_AC; |
-- luminance |
if huf_sm_settings.cmp_idx = 0 then |
VLC_size <= VLC_AC_size; |
VLC <= VLC_AC; |
-- chrominance |
else |
VLC_size <= VLC_CR_AC_size; |
VLC <= VLC_CR_AC; |
end if; |
end if; |
end if; |
end process; |
/mkjpeg/trunk/design/huffman/AC_CR_ROM.vhd
0,0 → 1,708
------------------------------------------------------------------------------- |
-- File Name : AC_CR_ROM.vhd |
-- |
-- Project : JPEG_ENC |
-- |
-- Module : AC_CR_ROM |
-- |
-- Content : AC_CR_ROM Chrominance |
-- |
-- Description : |
-- |
-- Spec. : |
-- |
-- Author : Michal Krepa |
-- |
------------------------------------------------------------------------------- |
-- History : |
-- 20090329: (MK): Initial Creation. |
------------------------------------------------------------------------------- |
|
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- LIBRARY/PACKAGE --------------------------- |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
|
------------------------------------------------------------------------------- |
-- generic packages/libraries: |
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
------------------------------------------------------------------------------- |
-- user packages/libraries: |
------------------------------------------------------------------------------- |
|
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- ENTITY ------------------------------------ |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
entity AC_CR_ROM is |
port |
( |
CLK : in std_logic; |
RST : in std_logic; |
runlength : in std_logic_vector(3 downto 0); |
VLI_size : in std_logic_vector(3 downto 0); |
|
VLC_AC_size : out unsigned(4 downto 0); |
VLC_AC : out unsigned(15 downto 0) |
); |
end entity AC_CR_ROM; |
|
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- ARCHITECTURE ------------------------------ |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
architecture RTL of AC_CR_ROM is |
|
signal rom_addr : std_logic_vector(7 downto 0); |
|
------------------------------------------------------------------------------- |
-- Architecture: begin |
------------------------------------------------------------------------------- |
begin |
|
rom_addr <= runlength & VLI_size; |
|
------------------------------------------------------------------- |
-- AC-ROM |
------------------------------------------------------------------- |
p_AC_CR_ROM : process(CLK, RST) |
begin |
if RST = '1' then |
VLC_AC_size <= (others => '0'); |
VLC_AC <= (others => '0'); |
elsif CLK'event and CLK = '1' then |
case runlength is |
when X"0" => |
|
case VLI_size is |
when X"0" => |
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); |
VLC_AC <= resize("00", VLC_AC'length); |
when X"1" => |
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); |
VLC_AC <= resize("01", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); |
VLC_AC <= resize("100", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); |
VLC_AC <= resize("1010", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); |
VLC_AC <= resize("11000", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); |
VLC_AC <= resize("11001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); |
VLC_AC <= resize("111000", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); |
VLC_AC <= resize("1111000", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111110100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); |
VLC_AC <= resize("1111110110", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); |
VLC_AC <= resize("111111110100", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"1" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); |
VLC_AC <= resize("1011", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); |
VLC_AC <= resize("111001", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); |
VLC_AC <= resize("11110110", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111110101", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); |
VLC_AC <= resize("11111110110", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); |
VLC_AC <= resize("111111110101", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001000", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001001", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001010", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001011", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"2" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); |
VLC_AC <= resize("11010", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); |
VLC_AC <= resize("11110111", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); |
VLC_AC <= resize("1111110111", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); |
VLC_AC <= resize("111111110110", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); |
VLC_AC <= resize("111111111000010", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001100", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001101", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001110", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110001111", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010000", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"3" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); |
VLC_AC <= resize("11011", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); |
VLC_AC <= resize("11111000", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); |
VLC_AC <= resize("1111111000", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); |
VLC_AC <= resize("111111110111", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010010", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010011", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010101", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010110", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"4" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); |
VLC_AC <= resize("111010", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111110110", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110010111", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011000", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011010", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011011", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011101", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011110", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"5" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); |
VLC_AC <= resize("111011", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); |
VLC_AC <= resize("1111111001", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110011111", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100000", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100010", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100011", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100101", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100110", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"6" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); |
VLC_AC <= resize("1111001", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); |
VLC_AC <= resize("11111110111", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110100111", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101000", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101010", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101011", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101101", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101110", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"7" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); |
VLC_AC <= resize("1111010", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); |
VLC_AC <= resize("11111111000", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110101111", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110000", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110010", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110011", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110101", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110110", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"8" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); |
VLC_AC <= resize("11111001", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110110111", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111000", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111001", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111010", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111011", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111100", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111101", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111110", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111110111111", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"9" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111110111", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000000", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000001", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000010", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000011", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000100", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000101", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000110", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111000111", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001000", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"A" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111111000", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001001", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001010", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001011", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001100", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001101", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001110", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111001111", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010000", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010001", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"B" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111111001", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010010", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010011", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010100", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010101", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010110", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111010111", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011000", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011001", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011010", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"C" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); |
VLC_AC <= resize("111111010", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011011", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011100", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011101", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011110", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111011111", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100000", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100001", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100010", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100011", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"D" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); |
VLC_AC <= resize("11111111001", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100100", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100101", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100110", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111100111", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101000", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101001", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101010", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101011", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101100", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"E" => |
|
case VLI_size is |
when X"1" => |
VLC_AC_size <= to_unsigned(14, VLC_AC_size'length); |
VLC_AC <= resize("11111111100000", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101101", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101110", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111101111", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110000", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110001", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110010", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110011", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110100", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110101", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when X"F" => |
|
case VLI_size is |
when X"0" => |
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); |
VLC_AC <= resize("1111111010", VLC_AC'length); |
when X"1" => |
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); |
VLC_AC <= resize("111111111000011", VLC_AC'length); |
when X"2" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110110", VLC_AC'length); |
when X"3" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111110111", VLC_AC'length); |
when X"4" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111000", VLC_AC'length); |
when X"5" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111001", VLC_AC'length); |
when X"6" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111010", VLC_AC'length); |
when X"7" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111011", VLC_AC'length); |
when X"8" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111100", VLC_AC'length); |
when X"9" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111101", VLC_AC'length); |
when X"A" => |
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); |
VLC_AC <= resize("1111111111111110", VLC_AC'length); |
when others => |
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); |
VLC_AC <= resize("0", VLC_AC'length); |
end case; |
|
when others => |
VLC_AC_size <= (others => '0'); |
VLC_AC <= (others => '0'); |
end case; |
end if; |
end process; |
|
|
|
end architecture RTL; |
------------------------------------------------------------------------------- |
-- Architecture: end |
------------------------------------------------------------------------------- |
/mkjpeg/trunk/design/huffman/DC_CR_ROM.vhd
0,0 → 1,127
------------------------------------------------------------------------------- |
-- File Name : DC_CR_ROM.vhd |
-- |
-- Project : JPEG_ENC |
-- |
-- Module : DC_CR_ROM |
-- |
-- Content : DC_CR_ROM Chrominance |
-- |
-- Description : |
-- |
-- Spec. : |
-- |
-- Author : Michal Krepa |
-- |
------------------------------------------------------------------------------- |
-- History : |
-- 20090329: (MK): Initial Creation. |
------------------------------------------------------------------------------- |
|
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- LIBRARY/PACKAGE --------------------------- |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
|
------------------------------------------------------------------------------- |
-- generic packages/libraries: |
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
------------------------------------------------------------------------------- |
-- user packages/libraries: |
------------------------------------------------------------------------------- |
|
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- ENTITY ------------------------------------ |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
entity DC_CR_ROM is |
port |
( |
CLK : in std_logic; |
RST : in std_logic; |
VLI_size : in std_logic_vector(3 downto 0); |
|
VLC_DC_size : out std_logic_vector(3 downto 0); |
VLC_DC : out unsigned(10 downto 0) |
); |
end entity DC_CR_ROM; |
|
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
----------------------------------- ARCHITECTURE ------------------------------ |
------------------------------------------------------------------------------- |
------------------------------------------------------------------------------- |
architecture RTL of DC_CR_ROM is |
|
|
|
------------------------------------------------------------------------------- |
-- Architecture: begin |
------------------------------------------------------------------------------- |
begin |
|
------------------------------------------------------------------- |
-- DC-ROM |
------------------------------------------------------------------- |
p_DC_CR_ROM : process(CLK, RST) |
begin |
if RST = '1' then |
VLC_DC_size <= X"0"; |
VLC_DC <= (others => '0'); |
elsif CLK'event and CLK = '1' then |
case VLI_size is |
when X"0" => |
VLC_DC_size <= X"2"; |
VLC_DC <= resize("00", VLC_DC'length); |
when X"1" => |
VLC_DC_size <= X"2"; |
VLC_DC <= resize("01", VLC_DC'length); |
when X"2" => |
VLC_DC_size <= X"2"; |
VLC_DC <= resize("10", VLC_DC'length); |
when X"3" => |
VLC_DC_size <= X"3"; |
VLC_DC <= resize("110", VLC_DC'length); |
when X"4" => |
VLC_DC_size <= X"4"; |
VLC_DC <= resize("1110", VLC_DC'length); |
when X"5" => |
VLC_DC_size <= X"5"; |
VLC_DC <= resize("11110", VLC_DC'length); |
when X"6" => |
VLC_DC_size <= X"6"; |
VLC_DC <= resize("111110", VLC_DC'length); |
when X"7" => |
VLC_DC_size <= X"7"; |
VLC_DC <= resize("1111110", VLC_DC'length); |
when X"8" => |
VLC_DC_size <= X"8"; |
VLC_DC <= resize("11111110", VLC_DC'length); |
when X"9" => |
VLC_DC_size <= X"9"; |
VLC_DC <= resize("111111110", VLC_DC'length); |
when X"A" => |
VLC_DC_size <= X"A"; |
VLC_DC <= resize("1111111110", VLC_DC'length); |
when X"B" => |
VLC_DC_size <= X"B"; |
VLC_DC <= resize("11111111110", VLC_DC'length); |
when others => |
VLC_DC_size <= X"0"; |
VLC_DC <= (others => '0'); |
end case; |
end if; |
end process; |
|
|
|
end architecture RTL; |
------------------------------------------------------------------------------- |
-- Architecture: end |
------------------------------------------------------------------------------- |
/mkjpeg/trunk/design/JFIFGen/JFIFGen.vhd
88,17 → 88,17
|
|
signal hr_data : std_logic_vector(7 downto 0); |
signal hr_waddr : std_logic_vector(8 downto 0); |
signal hr_raddr : std_logic_vector(8 downto 0); |
signal hr_waddr : std_logic_vector(9 downto 0); |
signal hr_raddr : std_logic_vector(9 downto 0); |
signal hr_we : std_logic; |
signal hr_q : std_logic_vector(7 downto 0); |
signal size_wr_cnt : unsigned(2 downto 0); |
signal size_wr : std_logic; |
signal rd_cnt : unsigned(8 downto 0); |
signal rd_cnt : unsigned(9 downto 0); |
signal rd_en : std_logic; |
signal rd_en_d1 : std_logic; |
signal rd_cnt_d1 : unsigned(8 downto 0); |
signal rd_cnt_d2 : unsigned(8 downto 0); |
signal rd_cnt_d1 : unsigned(rd_cnt'range); |
signal rd_cnt_d2 : unsigned(rd_cnt'range); |
signal eoi_cnt : unsigned(1 downto 0); |
signal eoi_wr : std_logic; |
signal eoi_wr_d1 : std_logic; |
114,7 → 114,7
U_Header_RAM : entity work.RAMZ |
generic map |
( |
RAMADDR_W => 9, |
RAMADDR_W => 10, |
RAMDATA_W => 8 |
) |
port map |
/mkjpeg/trunk/design/common/JPEG_PKG.vhd
27,7 → 27,7
package JPEG_PKG is |
|
-- do not change, constant |
constant C_HDR_SIZE : integer := 407; |
constant C_HDR_SIZE : integer := 623; |
|
-- warning! this parameter heavily affects memory size required |
-- if expected image width is known change this parameter to match this |