URL
https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk
Subversion Repositories usbhostslave
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- This comparison shows the changes necessary to convert path
/
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/trunk/RTL/include/usbHostSlave_h.v
48,10 → 48,18
// Replaced individual timescale directives with `include "timescale.v |
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to |
// 'usbHostSlaveAvalonWrap' |
// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added |
// synchronizer to incoming USB wire data to avoid |
// metastability, and delay hazards. Not entirely sure, but it appears that |
// this bug caused more problems with some of the newer low power FPGAs |
// Maybe because they are more prone to problems with metastable |
// inputs that feed logic functions causing excessive high speed |
// toggle activity, and disrupting nearby cicuits. |
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// Most significant nibble corresponds to major revision. |
// Least significant nibble corresponds to minor revision. |
`define USBHOSTSLAVE_VERSION_NUM 8'h12 |
`define USBHOSTSLAVE_VERSION_NUM 8'h13 |
|
//Host slave common registers |
`define HOST_SLAVE_CONTROL_REG 1'b0 |
/trunk/RTL/serialInterfaceEngine/readUSBWireData.v
115,6 → 115,8
reg RxWireEdgeDetect; |
reg RxWireActiveReg; |
reg RxWireActiveReg2; |
reg [1:0] RxBitsInSyncReg1; |
reg [1:0] RxBitsInSyncReg2; |
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// buffer output state machine state codes: |
`define WAIT_BUFFER_NOT_EMPTY 2'b00 |
121,6 → 123,12
`define WAIT_SIE_RX_READY 2'b01 |
`define SIE_RX_WRITE 2'b10 |
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// re-synchronize incoming bits |
always @(posedge clk) begin |
RxBitsInSyncReg1 <= RxBitsIn; |
RxBitsInSyncReg2 <= RxBitsInSyncReg1; |
end |
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reg [1:0] bufferOutStMachCurrState; |
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|
158,10 → 166,10
end |
else begin |
RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset |
RxBitsInReg <= RxBitsIn; |
RxBitsInReg <= RxBitsInSyncReg2; |
oldRxBitsIn <= RxBitsInReg; |
incBufferCnt <= 1'b0; //default value |
if ( (TxWireActiveDrive == 1'b0) && (RxBitsIn != RxBitsInReg)) begin //if edge detected then |
if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then |
sampleCnt <= 5'b00000; |
RxWireEdgeDetect <= 1'b1; // flag receive activity |
RxWireActiveReg <= 1'b1; |