URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 350 to Rev 351
- ↔ Reverse comparison
Rev 350 → Rev 351
/trunk/or1200/rtl/verilog/cpu.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.13 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
260,6 → 263,11
wire mac_stall; |
|
// |
// Send exceptions to Debug Unit |
// |
assign du_except = except_type; |
|
// |
// Data cache enable |
// |
//assign dc_en = 1'b1; |
347,6 → 355,7
.if_pc(if_pc), |
.branch_op(branch_op), |
.except_type(except_type), |
.flushpipe(flushpipe), |
.except_start(except_start), |
.branch_addrofs(branch_addrofs), |
.lr_restor(operand_b), |
/trunk/or1200/rtl/verilog/except.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.10 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
362,7 → 365,13
esr <= #1 datain[`SR_WIDTH-1:0]; |
end |
`EXCEPTFSM_FLU1: |
if (!if_stall & !id_freeze) |
if (except_type == `EXCEPT_TRAP) begin |
state <= #1 `EXCEPTFSM_IDLE; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; |
except_type <= #1 `EXCEPT_NONE; |
end |
else if (!if_stall & !id_freeze) |
state <= #1 `EXCEPTFSM_FLU2; |
`EXCEPTFSM_FLU2: |
if (!if_stall & !id_freeze) |
379,16 → 388,9
state <= #1 `EXCEPTFSM_FLU4; |
end |
`EXCEPTFSM_FLU4: begin |
if (except_type != `EXCEPT_TRAP) begin |
state <= #1 `EXCEPTFSM_FLU5; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b1; |
end |
else begin |
state <= #1 `EXCEPTFSM_IDLE; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; |
end |
state <= #1 `EXCEPTFSM_FLU5; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b1; |
end |
`EXCEPTFSM_FLU5: begin |
`ifdef OR1200_VERBOSE |
/trunk/or1200/rtl/verilog/ifetch.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.7 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
72,7 → 75,7
ic_insn, ic_addr, ic_stall, ic_fetchop, |
|
// Internal i/f |
if_freeze, if_insn, if_pc, branch_op, except_type, |
if_freeze, if_insn, if_pc, branch_op, except_type, flushpipe, |
branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start, |
epcr, force_dslot_fetch, if_stall, branch_stall, |
spr_dat_i, spr_pc_we |
104,6 → 107,7
output [31:0] if_pc; |
input [`BRANCHOP_WIDTH-1:0] branch_op; |
input [`EXCEPT_WIDTH-1:0] except_type; |
input flushpipe; |
input [31:2] branch_addrofs; |
input [31:0] lr_restor; |
input flag; |
271,7 → 275,7
pcreg <= #1 30'd64; |
else if (spr_pc_we) |
pcreg <= #1 spr_dat_i[31:2]; |
else if (!if_freeze && !ic_stall) begin |
else if (!if_freeze && !ic_stall && !flushpipe) begin |
pcreg <= #1 ic_addr[31:2]; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |