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https://opencores.org/ocsvn/or1k/or1k/trunk
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- from Rev 352 to Rev 353
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Rev 352 → Rev 353
/trunk/or1200/rtl/verilog/defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
// Revision 1.13 2001/11/12 01:45:40 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
99,12 → 102,12
// |
// Data cache not implemented |
// |
//`define OR1200_NO_DC |
`define OR1200_NO_DC |
|
// |
// Insn cache not implemented |
// |
//`define OR1200_NO_IC |
`define OR1200_NO_IC |
|
// |
// Data MMU not implemented |