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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 355 to Rev 356
- ↔ Reverse comparison
Rev 355 → Rev 356
/trunk/or1200/rtl/verilog/id.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.11 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
373,6 → 376,8
id_insn[31:26] <= #1 `OR32_NOP; |
id_insn[25:0] <= #1 26'd0; |
end |
else if (flushpipe) |
id_insn <= #1 {`OR32_NOP, 26'h000_444F}; // id_insn[0] must be 1 |
else if (!id_freeze) begin |
id_insn <= #1 if_insn; |
`ifdef OR1200_VERBOSE |
/trunk/or1200/rtl/verilog/except.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2001/11/18 09:58:28 lampret |
// Fixed some l.trap typos. |
// |
// Revision 1.11 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
365,16 → 368,16
esr <= #1 datain[`SR_WIDTH-1:0]; |
end |
`EXCEPTFSM_FLU1: |
if (except_type == `EXCEPT_TRAP) begin |
if (!if_stall & !id_freeze) |
state <= #1 `EXCEPTFSM_FLU2; |
`EXCEPTFSM_FLU2: |
if (except_type == `EXCEPT_TRAP) begin |
state <= #1 `EXCEPTFSM_IDLE; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; |
except_type <= #1 `EXCEPT_NONE; |
end |
else if (!if_stall & !id_freeze) |
state <= #1 `EXCEPTFSM_FLU2; |
`EXCEPTFSM_FLU2: |
if (!if_stall & !id_freeze) |
else if (!if_stall & !id_freeze) |
state <= #1 `EXCEPTFSM_FLU3; |
`EXCEPTFSM_FLU3: |
if (!if_stall && !id_freeze) |
/trunk/or1200/rtl/verilog/ifetch.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2001/11/18 09:58:28 lampret |
// Fixed some l.trap typos. |
// |
// Revision 1.8 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
144,12 → 147,12
// |
// Control access to IC subsystem |
// |
assign ic_fetchop = (if_saved[32] & !if_stall) ? `FETCHOP_NOP : `FETCHOP_LW; |
assign ic_fetchop = (if_saved[32] & !if_stall | flushpipe) ? `FETCHOP_NOP : `FETCHOP_LW; |
|
// |
// Just fetched instruction |
// |
assign if_insn = (if_saved[32]) ? if_saved[31:0] : (ic_stall) ? 32'h1500FFFF : ic_insn; // if_insn[0] must be 1 |
assign if_insn = (if_saved[32]) ? if_saved[31:0] : (ic_stall | flushpipe) ? 32'h1500FFFF : ic_insn; // if_insn[0] must be 1 |
|
// |
// Delay slot PC saved |
292,6 → 295,8
if (rst) begin |
if_saved <= #1 33'b0; |
end |
else if (flushpipe) |
if_saved <= #1 {1'b0, `OR32_NOP, 26'h000_444F}; |
else if (if_freeze && !if_saved[32] && !ic_stall) begin // && !taken |
if_saved <= #1 {1'b1, ic_insn}; |
`ifdef OR1200_VERBOSE |
/trunk/or1200/rtl/verilog/rf.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
// Revision 1.11 2001/11/12 01:45:40 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
184,21 → 187,23
// |
// RF write enable is either from SPRS or normal from CPU control |
// |
assign rf_we = ((spr_valid & spr_write) | we) & ~flushpipe; |
assign rf_we = ((spr_valid & spr_write) | (we & ~id_freeze)) & ~flushpipe; |
|
// |
// CS RF A asserted when instruction reads operand A and ID stage |
// is not stalled |
// |
// assign rf_ena = rda & ~id_freeze; |
assign rf_ena = 1'b1; |
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils |
// assign rf_ena = 1'b1; // does not work with single-stepping |
assign rf_ena = ~id_freeze | spr_valid; // probably works with broken binutils |
|
// |
// CS RF B asserted when instruction reads operand B and ID stage |
// is not stalled |
// |
// assign rf_enb = rdb & ~id_freeze; |
assign rf_enb = 1'b1; |
// assign rf_enb = rdb & ~id_freeze | spr_valid; |
// assign rf_enb = 1'b1; |
assign rf_enb = ~id_freeze | spr_valid; // probably works with broken binutils |
|
// |
// Stores operand from RF_A into temp reg when pipeline is frozen |
/trunk/or1200/rtl/verilog/du.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.7 2001/10/21 18:09:53 lampret |
// Fixed sensitivity list. |
// |
238,12 → 241,14
// dbg_bp_r <= #1 1'b1; |
dbg_bp_r <= #1 1'b0; |
else |
dbg_bp_r <= |except_masked |
dbg_bp_r <= #1 |except_masked |
`ifdef DU_DMR1_ST |
| ~ex_freeze & ~((ex_insn[31:26] == `OR32_NOP) & ex_insn[0]) & dmr1[`DU_DMR1_ST] |
| ~ex_freeze & ~((ex_insn[31:26] == `OR32_NOP) & ex_insn[0]) & dmr1[`DU_DMR1_ST] |
// DAMJAN | ~ex_freeze & ~((ex_insn[31:26] == `OR32_NOP) & ex_insn[0]) & dmr1[`DU_DMR1_ST] |
`endif |
`ifdef DU_DMR1_BT |
| ~ex_freeze & ~((ex_insn[31:26] == `OR32_NOP) & ex_insn[0]) & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT] |
// DAMJAN | ~ex_freeze & ~((ex_insn[31:26] == `OR32_NOP) & ex_insn[0]) & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT] |
| ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT] |
`endif |
; |
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