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Rev 36 → Rev 37

/opencpu32/trunk/hdl/opencpu32/testOpenCpu.vhd
10,11 → 10,14
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! Adding library for File I/O (Synposys Text I/O package)
--! Adding library for File I/O
-- More information on this site:
-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
use std.textio.ALL;
use ieee.std_logic_textio.all;
ENTITY testOpenCpu IS
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
END testOpenCpu;
--! @brief openCpu Testbench file
23,30 → 26,30
--! Component declaration to instantiate the Multiplexer circuit
COMPONENT openCpu
PORT(
rst : IN std_logic;
clk : IN std_logic;
mem_rd : OUT std_logic;
mem_rd_addr : OUT std_logic_vector(31 downto 0);
mem_wr : OUT std_logic;
mem_wr_addr : OUT std_logic_vector(31 downto 0);
mem_data_in : IN std_logic_vector(31 downto 0);
mem_data_out : OUT std_logic_vector(31 downto 0)
);
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( rst : in STD_LOGIC; --! Reset signal
clk : in STD_LOGIC; --! Clock signal
mem_rd : out STD_LOGIC; --! Main memory Read enable
mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
mem_wr : out STD_LOGIC; --! Main memory Write enable
mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
);
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal mem_data_in : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0'; --! Wire to connect Test signal to component
signal clk : std_logic := '0'; --! Wire to connect Test signal to component
signal mem_data_in : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
 
--Outputs
signal mem_rd : std_logic;
signal mem_rd_addr : std_logic_vector(31 downto 0);
signal mem_wr : std_logic;
signal mem_wr_addr : std_logic_vector(31 downto 0);
signal mem_data_out : std_logic_vector(31 downto 0);
signal mem_rd : std_logic; --! Wire to connect Test signal to component
signal mem_rd_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
signal mem_wr : std_logic; --! Wire to connect Test signal to component
signal mem_wr_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
signal mem_data_out : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
 
-- Clock period definitions
constant clk_period : time := 10 ns;
53,7 → 56,7
BEGIN
--!Instantiate the Unit Under Test (openCpu) (Doxygen bug if it's not commented!)
--! Instantiate the Unit Under Test (openCpu) (Doxygen bug if it's not commented!)
uut: openCpu PORT MAP (
rst => rst,
clk => clk,
/opencpu32/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,5 → 8,8
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testOpenCpu.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
187,7 → 187,6
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="openCpu.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="openCpu.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="openCpu.ngc"/>
224,7 → 223,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334496821" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334496821">
<transform xil_pn:end_ts="1334529518" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334529518">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
256,7 → 255,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334496821" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334496821">
<transform xil_pn:end_ts="1334529518" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334529518">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
276,21 → 275,19
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334496823" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334496821">
<transform xil_pn:end_ts="1334529522" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334529518">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testOpenCpu_beh.prj"/>
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334496824" xil_pn:in_ck="-7416607345915100494" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334496823">
<transform xil_pn:end_ts="1334529522" xil_pn:in_ck="-7416607345915100494" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334529522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testOpenCpu_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1333971566" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333971566">

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