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URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

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    from Rev 36 to Rev 37
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Rev 36 → Rev 37

/trunk/rtl/vhdl/rx_ver_reg.vhd
45,14 → 45,17
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/04 15:55:07 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1 2004/06/03 17:51:41 gedra
-- Receiver version register.
--
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity rx_ver_reg is
generic (DATA_WIDTH: integer;
75,12 → 78,13
G32: if DATA_WIDTH = 32 generate
version(4) <= '1';
version(31 downto 20) <= (others => '0');
version(19 downto 16) <= CONV_STD_LOGIC_VECTOR(CH_ST_CAPTURE, 4);
version(19 downto 16) <=
std_logic_vector(to_unsigned(CH_ST_CAPTURE, 4));
end generate G32;
G16: if DATA_WIDTH = 16 generate
version(4) <= '0';
end generate G16;
version(11 downto 5) <= CONV_STD_LOGIC_VECTOR(ADDR_WIDTH, 7);
version(11 downto 5) <= std_logic_vector(to_unsigned(ADDR_WIDTH, 7));
version(15 downto 12) <= (others => '0');
end rtl;
/trunk/rtl/vhdl/dpram_rtl.vhd
48,6 → 48,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/10 18:57:36 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1 2004/06/09 19:24:31 gedra
-- Generic dual port ram model.
--
55,7 → 58,7
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity dpram is
generic (DATA_WIDTH: positive;
89,7 → 92,7
begin
if rising_edge(clk) then
if wr_en = '1' then
memory(CONV_INTEGER(wr_addr)) <= din;
memory(to_integer(unsigned(wr_addr))) <= din;
end if;
end if;
end process;
98,7 → 101,7
begin
if rising_edge(clk) then
if rd_en = '1' then
dout <= memory(CONV_INTEGER(rd_addr));
dout <= memory(to_integer(unsigned(rd_addr)));
end if;
end if;
end process;
/trunk/rtl/vhdl/rx_package.vhd
45,6 → 45,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2004/06/23 18:10:17 gedra
-- Added Wishbone bus cycle decoder.
--
-- Revision 1.5 2004/06/16 19:03:45 gedra
-- Changed status reg. declaration
--
196,7 → 199,7
rx_channel_a: in std_logic;
wr_en: out std_logic;
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH downto 0);
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
stat_paritya: out std_logic;
stat_parityb: out std_logic;
stat_lsbf: out std_logic;
233,5 → 236,5
ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
end component;
 
end rx_package;
/trunk/rtl/vhdl/gen_control_reg.vhd
45,6 → 45,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/06/06 15:42:19 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2 2004/06/04 15:55:07 gedra
-- Cleaned up lint warnings.
--
53,9 → 56,8
--
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library ieee;
use ieee.std_logic_1164.all;
 
entity gen_control_reg is
generic (DATA_WIDTH: integer;
/trunk/rtl/vhdl/rx_wb_decoder.vhd
45,15 → 45,17
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/24 19:25:03 gedra
-- Added data output.
--
-- Revision 1.1 2004/06/23 18:09:57 gedra
-- Wishbone bus cycle decoder.
--
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity rx_wb_decoder is
generic (DATA_WIDTH: integer;
169,7 → 171,7
end process DREG;
-- sample memory read address. This needs special attention due to read latency
mem_addr <= CONV_STD_LOGIC_VECTOR(acnt, ADDR_WIDTH - 1) when
mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when
wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
185,7 → 187,7
if wb_adr_i = all_ones then
acnt <= 0;
else
acnt <= CONV_INTEGER(wb_adr_i) + 1;
acnt <= to_integer(unsigned(wb_adr_i)) + 1;
end if;
else
if acnt < 2**(ADDR_WIDTH - 1) - 1 then
222,13 → 224,13
CR32: if DATA_WIDTH = 32 generate
CRST: for k in 0 to 7 generate
ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k,4)
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
else '0';
ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k,4)
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
else '0';
ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k+1,4)
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1,4))
else '0';
end generate CRST;
end generate CR32;
/trunk/rtl/vhdl/rx_cap_reg.vhd
45,11 → 45,14
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/06/05 17:16:46 gedra
-- Channel status/user data capture register
--
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rx_package.all;
 
entity rx_cap_reg is
98,10 → 101,10
ctrl_dout => cap_ctrl_dout,
ctrl_bits => cap_ctrl_bits);
bitlen <= CONV_INTEGER(cap_ctrl_bits(5 downto 0));
bitlen <= to_integer(unsigned(cap_ctrl_bits(5 downto 0)));
chid <= cap_ctrl_bits(6);
cdata <= cap_ctrl_bits(7);
bitpos <= CONV_INTEGER(cap_ctrl_bits(15 downto 8));
bitpos <= to_integer(unsigned(cap_ctrl_bits(15 downto 8)));
-- capture data register
CDAT: process (clk, rst)
158,7 → 161,7
if cap_len = bitlen and compared = '0' then
compared <= '1';
-- event generated if captured bits differ
if CONV_INTEGER(cap_reg) /= CONV_INTEGER(cap_new) then
if cap_reg /= cap_new then
cap_evt <= '1';
end if;
cap_reg <= cap_new;
/trunk/rtl/vhdl/rx_status_reg.vhd
45,14 → 45,16
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/16 19:03:10 gedra
-- Added channel status decoding.
--
-- Revision 1.1 2004/06/05 17:17:12 gedra
-- Recevier status register
--
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library ieee;
use ieee.std_logic_1164.all;
 
entity rx_status_reg is
generic (DATA_WIDTH: integer);
/trunk/rtl/vhdl/dpram_altera.vhd
46,6 → 46,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/19 09:55:19 gedra
-- Delint'ed and changed name of architecture.
--
-- Revision 1.1 2004/06/18 18:40:04 gedra
-- Alternate dual port memory implementation for Altera FPGA's.
--
53,7 → 56,7
 
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
 
library lpm;
use lpm.lpm_components.all;
 
101,7 → 104,7
ram: lpm_ram_dp
generic map(LPM_WIDTH => DATA_WIDTH,
LPM_WIDTHAD => RAM_WIDTH,
LPM_NUMWORDS => 2**(RAM_WIDTH - 1))
LPM_NUMWORDS => 2**RAM_WIDTH)
port map (data => din,
rdaddress => rd_addr,
wraddress => wr_addr,
/trunk/rtl/vhdl/rx_decode.vhd
46,6 → 46,9
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/16 19:04:09 gedra
-- Fixed a few bugs.
--
-- Revision 1.1 2004/06/13 18:07:47 gedra
-- Frame decoder and sample extractor
--
53,7 → 56,7
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
entity rx_decode is
generic (DATA_WIDTH: integer range 16 to 32;
77,7 → 80,7
rx_channel_a: in std_logic;
wr_en: out std_logic;
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH -1 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
stat_paritya: out std_logic;
stat_parityb: out std_logic;
stat_lsbf: out std_logic;
91,7 → 94,7
signal sampst : samp_states;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal samp_start : integer range 0 to 15;
signal tmp_data : std_logic_vector(DATA_WIDTH - 6 downto 0);
signal tmp_data : std_logic_vector(26 downto 0);
signal tmp_stat : std_logic_vector(4 downto 0);
signal valid, next_is_a, blk_start : std_logic;
128,7 → 131,7
sampst <= CHA_SYNC;
end if;
when CHA_SYNC =>
wr_addr <= CONV_STD_LOGIC_VECTOR(adr_cnt, ADDR_WIDTH - 1);
wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
wr_en <= '0';
bit_cnt <= 0;
valid <= '0';
137,7 → 140,7
stat_parityb <= '0';
stat_lsbf <= '0';
stat_hsbf <= '0';
tmp_data(DATA_WIDTH - 6 downto 0) <= (others => '0');
tmp_data(26 downto 0) <= (others => '0');
if rx_block_start = '1' and conf_blken = '1' then
blk_start <= '1';
end if;

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