OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

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    from Rev 36 to Rev 37
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Rev 36 → Rev 37

/uart_block/trunk/hdl/iseProject/testSerial_receiver.vhd
13,25 → 13,24
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT serial_receiver
PORT(
rst : IN std_logic;
baudOverSampleClk : IN std_logic;
serial_in : IN std_logic;
data_ready : OUT std_logic;
data_byte : OUT std_logic_vector((nBits-1) downto 0)
);
Port (
rst : in STD_LOGIC; --! Reset input
baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
serial_in : in STD_LOGIC; --! Uart serial input
data_ready : out STD_LOGIC; --! Data received and ready to be read
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal baudClk : std_logic := '0';
signal baudOverSampleClk : std_logic := '0';
signal serial_in : std_logic := '0';
signal rst : std_logic := '0'; --! Signal to connect with UUT
signal baudClk : std_logic := '0'; --! Signal to connect with UUT
signal baudOverSampleClk : std_logic := '0'; --! Signal to connect with UUT
signal serial_in : std_logic := '0'; --! Signal to connect with UUT
 
--Outputs
signal data_ready : std_logic;
signal data_byte : std_logic_vector((nBits-1) downto 0);
signal data_ready : std_logic; --! Signal to connect with UUT
signal data_byte : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
 
-- Clock period definitions
constant baudClk_period : time := 8.6805 us;
/uart_block/trunk/hdl/iseProject/testUart_control.vhd
15,42 → 15,42
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_control
Port ( rst : in std_logic; -- Global reset
clk : in std_logic; -- Global clock
WE : in std_logic; -- Write enable
reg_addr : in std_logic_vector (1 downto 0); -- Register address
start : in std_logic; -- Start (Strobe)
done : out std_logic; -- Done (ACK)
DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
tx_start : out std_logic; -- Signal to start sending serial data...
rst_comm_blocks : out std_logic; -- Reset Communication blocks
Port ( rst : in std_logic; --! Global reset
clk : in std_logic; --! Global clock
WE : in std_logic; --! Write enable
reg_addr : in std_logic_vector (1 downto 0); --! Register address
start : in std_logic; --! Start (Strobe)
done : out std_logic; --! Done (ACK)
DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); --! Data Input (Wishbone)
DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); --! Data output (Wishbone)
baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); --! Signal to control the baud rate frequency
data_byte_tx : out std_logic_vector((nBits-1) downto 0); --! 1 Byte to be send to serial_transmitter
data_byte_rx : in std_logic_vector((nBits-1) downto 0); --! 1 Byte to be received by serial_receiver
tx_data_sent : in std_logic; --! Signal comming from serial_transmitter
tx_start : out std_logic; --! Signal to start sending serial data...
rst_comm_blocks : out std_logic; --! Reset Communication blocks
rx_data_ready : in std_logic);
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal WE : std_logic := '0';
signal reg_addr : std_logic_vector(1 downto 0) := (others => '0');
signal start : std_logic := '0';
signal DAT_I : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
signal data_byte_rx : std_logic_vector((nBits-1) downto 0) := (others => '0');
signal tx_data_sent : std_logic := '0';
signal rx_data_ready : std_logic := '0';
signal rst : std_logic := '0'; --! Signal to connect with UUT
signal clk : std_logic := '0'; --! Signal to connect with UUT
signal WE : std_logic := '0'; --! Signal to connect with UUT
signal reg_addr : std_logic_vector(1 downto 0) := (others => '0'); --! Signal to connect with UUT
signal start : std_logic := '0'; --! Signal to connect with UUT
signal DAT_I : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
signal data_byte_rx : std_logic_vector((nBits-1) downto 0) := (others => '0'); --! Signal to connect with UUT
signal tx_data_sent : std_logic := '0'; --! Signal to connect with UUT
signal rx_data_ready : std_logic := '0'; --! Signal to connect with UUT
 
--Outputs
signal done : std_logic;
signal tx_start : std_logic;
signal rst_comm_blocks : std_logic;
signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);
signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
signal data_byte_tx : std_logic_vector((nBits-1) downto 0);
signal done : std_logic; --! Signal to connect with UUT
signal tx_start : std_logic; --! Signal to connect with UUT
signal rst_comm_blocks : std_logic; --! Signal to connect with UUT
signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
signal data_byte_tx : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
 
-- Clock period definitions
constant clk_period : time := 20 ns; -- 20ns (50Mhz)
/uart_block/trunk/hdl/iseProject/testDivisor.vhd
14,27 → 14,25
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT divisor
PORT(
rst : IN std_logic;
clk : IN std_logic;
quotient : OUT std_logic_vector((nBitsLarge-1) downto 0);
reminder : OUT std_logic_vector((nBitsLarge-1) downto 0);
numerator : IN std_logic_vector((nBitsLarge-1) downto 0);
divident : IN std_logic_vector((nBitsLarge-1) downto 0);
done : OUT std_logic
);
Port ( rst : in STD_LOGIC; --! Reset input
clk : in STD_LOGIC; --! Clock input
quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Division result (32 bits)
reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Reminder result (32 bits)
numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Numerator (32 bits)
divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! "Divide by" number (32 bits)
done : out STD_LOGIC);
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
signal rst : std_logic := '0'; --! Signal to connect with UUT
signal clk : std_logic := '0'; --! Signal to connect with UUT
signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
 
--Outputs
signal quotient : std_logic_vector((nBitsLarge-1) downto 0);
signal reminder : std_logic_vector((nBitsLarge-1) downto 0);
signal quotient : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
signal reminder : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
signal done : std_logic;
 
-- Clock period definitions
/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
15,36 → 15,37
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_wishbone_slave
PORT(
RST_I : IN std_logic;
CLK_I : IN std_logic;
ADR_I0 : IN std_logic_vector(1 downto 0);
DAT_I0 : IN std_logic_vector(31 downto 0);
DAT_O0 : OUT std_logic_vector(31 downto 0);
WE_I : IN std_logic;
STB_I : IN std_logic;
ACK_O : OUT std_logic;
serial_in : IN std_logic;
data_Avaible : out std_logic; -- Indicate that the receiver module got something
serial_out : OUT std_logic
);
Port ( RST_I : in STD_LOGIC; --! Reset Input
CLK_I : in STD_LOGIC; --! Clock Input
ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0); --! Address input
DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0); --! Data Input 0
DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0); --! Data Output 0
WE_I : in STD_LOGIC; --! Write enable input
STB_I : in STD_LOGIC; --! Strobe input (Works like a chip select)
ACK_O : out STD_LOGIC; --! Ack output
-- NON-WISHBONE Signals
serial_in : in std_logic; --! Uart serial input
data_Avaible : out std_logic; --! Flag to indicate data avaible
serial_out : out std_logic
);
END COMPONENT;
 
--Inputs
signal RST_I : std_logic := '0';
signal CLK_I : std_logic := '0';
signal ADR_I0 : std_logic_vector(1 downto 0) := (others => '0');
signal DAT_I0 : std_logic_vector(31 downto 0) := (others => '0');
signal RST_I : std_logic := '0'; --! Signal to connect with UUT
signal CLK_I : std_logic := '0'; --! Signal to connect with UUT
signal ADR_I0 : std_logic_vector(1 downto 0) := (others => '0'); --! Signal to connect with UUT
signal DAT_I0 : std_logic_vector(31 downto 0) := (others => '0'); --! Signal to connect with UUT
signal WE_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal serial_in : std_logic := '0';
 
--Outputs
signal DAT_O0 : std_logic_vector(31 downto 0);
signal ACK_O : std_logic;
signal serial_out : std_logic;
signal data_Avaible : std_logic;
signal DAT_O0 : std_logic_vector(31 downto 0); --! Signal to connect with UUT
signal ACK_O : std_logic; --! Signal to connect with UUT
signal serial_out : std_logic; --! Signal to connect with UUT
signal data_Avaible : std_logic; --! Signal to connect with UUT
 
-- Clock period definitions (1.8432MHz)
constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
/uart_block/trunk/hdl/iseProject/webtalk_pn.xml
3,7 → 3,7
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Tue May 08 23:40:28 2012">
<application name="pn" timeStamp="Wed May 09 00:20:31 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="31" type="project"/>
/uart_block/trunk/hdl/iseProject/testSerial_transmitter.vhd
13,24 → 13,22
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT serial_transmitter
PORT(
rst : IN std_logic;
baudClk : IN std_logic;
data_byte : IN std_logic_vector(7 downto 0);
data_sent : OUT std_logic;
serial_out : OUT std_logic
);
Port ( rst : in STD_LOGIC; --! Reset input
baudClk : in STD_LOGIC; --! Baud rate clock input
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
data_sent : out STD_LOGIC; --! Indicate that byte has been sent
serial_out : out STD_LOGIC); --! Uart serial output
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal baudClk : std_logic := '0';
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
signal rst : std_logic := '0'; --! Signal to connect with UUT
signal baudClk : std_logic := '0'; --! Signal to connect with UUT
signal data_byte : std_logic_vector(7 downto 0) := (others => '0'); --! Signal to connect with UUT
 
--Outputs
signal data_sent : std_logic;
signal serial_out : std_logic;
signal data_sent : std_logic; --! Signal to connect with UUT
signal serial_out : std_logic; --! Signal to connect with UUT
 
-- Clock period definitions
constant baudClk_period : time := 10 ns;
/uart_block/trunk/hdl/iseProject/baud_generator.vhd
1,5 → 1,5
--! Baud generator
--! http://www.fpga4fun.com/SerialInterface.html
--! @file
--! @brief Baud generator http://www.fpga4fun.com/SerialInterface.html
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
10,13 → 10,15
use work.pkgDefinitions.all;
 
entity baud_generator is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : out STD_LOGIC);
Port ( rst : in STD_LOGIC; --! Reset Input
clk : in STD_LOGIC; --! Clock input
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Number of cycles to wait for baud generation
baud_oversample : out std_logic; --! Oversample(8x) version of baud (Used on serial_receiver)
baud : out STD_LOGIC); --! Baud generation output (Used on serial_transmitter)
end baud_generator;
 
--! @brief Baud generator http://www.fpga4fun.com/SerialInterface.html
--! @details Implement block that will generate the desired baud (115200, 9600, etc...) from main clock (50Mhz)
architecture Behavioral of baud_generator is
signal genTick : std_logic;
signal genTickOverSample : std_logic;
/uart_block/trunk/hdl/iseProject/xst/work/hdpdeps.ref
11,74 → 11,74
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.17:56:59 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/02.08:07:03 O.87xd
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/08.22:34:17 O.87xd
EN work/baud_generator 1336513192 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/08.23:47:51 O.87xd
EN work/baud_generator 1336515634 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336513191
AR work/baud_generator/Behavioral 1336513193 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336513192
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336515633
AR work/baud_generator/Behavioral 1336515635 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336515634
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/08.23:23:27 O.87xd
EN work/divisor 1336513198 FL E:/uart_block/hdl/iseProject/divisor.vhd \
EN work/divisor 1336515640 FL E:/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1336513191
AR work/divisor/Behavioral 1336513199 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336513198
PB work/pkgDefinitions 1336515633
AR work/divisor/Behavioral 1336515641 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336515640
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/08.22:54:12 O.87xd
EN work/INTERCON_P2P 1336513210 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \
EN work/INTERCON_P2P 1336515652 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \
PB ieee/std_logic_1164 1325952872
AR work/INTERCON_P2P/Behavioral 1336513211 \
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336513210 \
AR work/INTERCON_P2P/Behavioral 1336515653 \
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336515652 \
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/08.22:34:17 O.87xd
PH work/pkgDefinitions 1336513190 \
PH work/pkgDefinitions 1336515632 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1336513191 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336513190
PB work/pkgDefinitions 1336515633 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336515632
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/08.23:01:15 O.87xd
EN work/SERIALMASTER 1336513206 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \
EN work/SERIALMASTER 1336515648 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336513191
AR work/SERIALMASTER/Behavioral 1336513207 \
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336513206
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/08.22:34:17 O.87xd
EN work/serial_receiver 1336513196 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336515633
AR work/SERIALMASTER/Behavioral 1336515649 \
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336515648
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/09.00:19:50 O.87xd
EN work/serial_receiver 1336515638 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1336513191
AR work/serial_receiver/Behavioral 1336513197 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336513196
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1336513194 \
PB work/pkgDefinitions 1336515633
AR work/serial_receiver/Behavioral 1336515639 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336515638
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/05/09.00:09:31 O.87xd
EN work/serial_transmitter 1336515636 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336513191
AR work/serial_transmitter/Behavioral 1336513195 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336515633
AR work/serial_transmitter/Behavioral 1336515637 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1336513194
EN work/serial_transmitter 1336515636
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/08.22:58:32 O.87xd
EN work/SYC0001a 1336513204 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \
EN work/SYC0001a 1336515646 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \
PB ieee/std_logic_1164 1325952872
AR work/SYC0001a/SYC0001a1 1336513205 \
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336513204
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/05/08.23:34:57 O.87xd
EN work/uart_communication_blocks 1336513202 \
AR work/SYC0001a/SYC0001a1 1336515647 \
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336515646
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/05/09.00:17:49 O.87xd
EN work/uart_communication_blocks 1336515644 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336513191
AR work/uart_communication_blocks/Behavioral 1336513203 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336515633
AR work/uart_communication_blocks/Behavioral 1336515645 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
EN work/uart_communication_blocks 1336513202 CP baud_generator \
EN work/uart_communication_blocks 1336515644 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/08.23:25:39 O.87xd
EN work/uart_control 1336513200 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
EN work/uart_control 1336515642 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336513191
AR work/uart_control/Behavioral 1336513201 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336513200 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336515633
AR work/uart_control/Behavioral 1336515643 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336515642 \
CP divisor
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/08.23:31:19 O.87xd
EN work/uart_wishbone_slave 1336513208 \
EN work/uart_wishbone_slave 1336515650 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336513191
AR work/uart_wishbone_slave/Behavioral 1336513209 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336515633
AR work/uart_wishbone_slave/Behavioral 1336515651 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
EN work/uart_wishbone_slave 1336513208 CP uart_control \
EN work/uart_wishbone_slave 1336515650 CP uart_control \
CP uart_communication_blocks
/uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
1,22 → 1,22
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336513203
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336513201
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336513205
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336513210
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336513191
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336513196
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336513209
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336513195
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336513202
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336513198
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336513199
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336513193
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336513204
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336513206
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336513200
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336513211
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336513194
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336513190
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336513207
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336513208
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336513192
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336513197
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336515645
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336515643
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336515647
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336515652
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336515633
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336515638
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336515651
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336515637
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336515644
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336515640
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336515641
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336515635
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336515646
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336515648
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336515642
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336515653
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336515636
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336515632
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336515649
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336515650
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336515634
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336515639
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl02.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl03.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/uart_block/trunk/hdl/iseProject/serial_receiver.vhd
1,5 → 1,5
--! Data receiver
--! http://www.fpga4fun.com/SerialInterface.html
--! @file
--! @brief Serial receiver http://www.fpga4fun.com/SerialInterface.html
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
8,13 → 8,15
 
entity serial_receiver is
Port (
rst : in STD_LOGIC;
baudOverSampleClk : in STD_LOGIC;
serial_in : in STD_LOGIC;
data_ready : out STD_LOGIC;
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
rst : in STD_LOGIC; --! Reset input
baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
serial_in : in STD_LOGIC; --! Uart serial input
data_ready : out STD_LOGIC; --! Data received and ready to be read
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
end serial_receiver;
 
--! @brief Serial receiver http://www.fpga4fun.com/SerialInterface.html
--! @details Implement block that create a byte from the serial stream of data.
architecture Behavioral of serial_receiver is
signal current_s: rxStates;
signal filterRx : rxFilterStates;
21,7 → 23,7
signal syncDetected : std_logic;
 
begin
-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC (By detecting the start bit)
process (rst, baudOverSampleClk, serial_in, current_s)
begin
if rst = '1' then
31,11 → 33,7
case filterRx is
when s0 =>
syncDetected <= '0';
-- Spike down detected, verify if it's valid for at least 3 cycles
-- We shoose a little bit on the end to enforce the baud clk to sample
-- the data at the right time... iE we're going to start sampling when
-- the stop has been detected and we already for some of the first bit
-- signal
-- Spike down detected, verify if it's valid for at least 4 cycles
if serial_in = '0' then
filterRx <= s1;
else
/uart_block/trunk/hdl/iseProject/iseProject.gise
319,12 → 319,10
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336513199" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336513183">
<transform xil_pn:end_ts="1336515643" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336515631">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.lso"/>
<outfile xil_pn:name="INTERCON_P2P.ngc"/>
<outfile xil_pn:name="INTERCON_P2P.ngr"/>
352,6 → 350,8
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.bld"/>
<outfile xil_pn:name="INTERCON_P2P.ngd"/>
<outfile xil_pn:name="INTERCON_P2P_cs.blc"/>
364,6 → 364,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.pcf"/>
<outfile xil_pn:name="INTERCON_P2P_map.map"/>
<outfile xil_pn:name="INTERCON_P2P_map.mrp"/>
378,6 → 381,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="INTERCON_P2P.ncd"/>
<outfile xil_pn:name="INTERCON_P2P.pad"/>
<outfile xil_pn:name="INTERCON_P2P.par"/>
393,6 → 397,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="intercon_p2p.bgn"/>
406,6 → 413,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
413,6 → 421,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
420,6 → 429,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
427,6 → 437,7
<transform xil_pn:end_ts="1336513241" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336513238">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="INTERCON_P2P.twr"/>
<outfile xil_pn:name="INTERCON_P2P.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
/uart_block/trunk/hdl/iseProject/testUart_communication_block.vhd
15,32 → 15,32
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_communication_blocks
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent_tx : out STD_LOGIC;
data_received_rx : out STD_LOGIC;
serial_out : out std_logic;
serial_in : in std_logic;
start_tx : in STD_LOGIC);
Port ( rst : in STD_LOGIC; --! Global reset
clk : in STD_LOGIC; --! Global clock
cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0); --! Number of cycles to wait in order to generate desired baud
byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to transmit
byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to receive
data_sent_tx : out STD_LOGIC; --! Indicate that byte has been sent
data_received_rx : out STD_LOGIC; --! Indicate that we got a byte
serial_out : out std_logic; --! Uart serial out
serial_in : in std_logic; --! Uart serial in
start_tx : in STD_LOGIC); --! Initiate transmission
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0');
signal serial_in : std_logic := '0';
signal start_tx : std_logic := '0';
signal rst : std_logic := '0'; --! Signal to connect with UUT
signal clk : std_logic := '0'; --! Signal to connect with UUT
signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0'); --! Signal to connect with UUT
signal serial_in : std_logic := '0'; --! Signal to connect with UUT
signal start_tx : std_logic := '0'; --! Signal to connect with UUT
 
--Outputs
signal byte_rx : std_logic_vector((nBits-1) downto 0);
signal data_sent_tx : std_logic;
signal data_received_rx : std_logic;
signal serial_out : std_logic;
signal byte_rx : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
signal data_sent_tx : std_logic; --! Signal to connect with UUT
signal data_received_rx : std_logic; --! Signal to connect with UUT
signal serial_out : std_logic; --! Signal to connect with UUT
 
-- Clock period definitions
constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
/uart_block/trunk/hdl/iseProject/serial_transmitter.vhd
1,5 → 1,5
--! Data transmitter
--! http://www.fpga4fun.com/SerialInterface.html
--! @file
--! @brief Serial transmitter http://www.fpga4fun.com/SerialInterface.html
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
7,13 → 7,15
use work.pkgDefinitions.all;
 
entity serial_transmitter is
Port ( rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent : out STD_LOGIC;
serial_out : out STD_LOGIC);
Port ( rst : in STD_LOGIC; --! Reset input
baudClk : in STD_LOGIC; --! Baud rate clock input
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
data_sent : out STD_LOGIC; --! Indicate that byte has been sent
serial_out : out STD_LOGIC); --! Uart serial output
end serial_transmitter;
 
--! @brief Serial transmitter http://www.fpga4fun.com/SerialInterface.html
--! @details Implement block that serialize the "data_byte" signal on a stream of bits clocked out by "baudClk"
architecture Behavioral of serial_transmitter is
signal current_s,next_s: txStates;
begin
/uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testBaud_generator.vhd&quot; into library work</arg>
</msg>
 
</messages>
/uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
5,19 → 5,19
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">88</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">CYC_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">88</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">CYC_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">88</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">SEL_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">88</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">SEL_O</arg>&apos; of component &apos;<arg fmt="%s" index="4">SERIALMASTER</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">104</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">data_Avaible</arg>&apos; of component &apos;<arg fmt="%s" index="4">uart_wishbone_slave</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>&quot; line <arg fmt="%d" index="2">104</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">data_Avaible</arg>&apos; of component &apos;<arg fmt="%s" index="4">uart_wishbone_slave</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="1610" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>&quot; line <arg fmt="%d" index="2">49</arg>: Width mismatch. &lt;<arg fmt="%s" index="3">byteIncome</arg>&gt; has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide.
<msg type="warning" file="Xst" num="1610" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>&quot; line <arg fmt="%d" index="2">49</arg>: Width mismatch. &lt;<arg fmt="%s" index="3">byteIncome</arg>&gt; has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide.
</msg>
 
<msg type="warning" file="Xst" num="753" delta="new" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">65</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">reminder</arg>&apos; of component &apos;<arg fmt="%s" index="4">divisor</arg>&apos;.
<msg type="warning" file="Xst" num="753" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>&quot; line <arg fmt="%d" index="2">65</arg>: Unconnected output port &apos;<arg fmt="%s" index="3">reminder</arg>&apos; of component &apos;<arg fmt="%s" index="4">divisor</arg>&apos;.
</msg>
 
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DAT_I&lt;31:8&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
/uart_block/trunk/hdl/iseProject/testBaud_generator.vhd
13,24 → 13,22
ARCHITECTURE behavior OF testBaud_generator IS
COMPONENT baud_generator
PORT(
rst : IN std_logic;
clk : IN std_logic;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : OUT std_logic
);
Port ( rst : in STD_LOGIC; --! Reset Input
clk : in STD_LOGIC; --! Clock input
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Number of cycles to wait for baud generation
baud_oversample : out std_logic; --! Oversample(8x) version of baud (Used on serial_receiver)
baud : out STD_LOGIC); --! Baud generation output (Used on serial_transmitter)
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
signal rst : std_logic := '0'; --! Signal to connect with UUT
signal clk : std_logic := '0'; --! Signal to connect with UUT
signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
 
--Outputs
signal baud : std_logic;
signal baud_oversample : std_logic;
signal baud : std_logic; --! Signal to connect with UUT
signal baud_oversample : std_logic; --! Signal to connect with UUT
 
-- Clock period definitions (1.8432MHz)
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
/uart_block/trunk/hdl/iseProject/uart_communication_blocks.vhd
1,4 → 1,5
--! Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
--! @file
--! @brief Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
18,32 → 19,34
start_tx : in STD_LOGIC); --! Initiate transmission
end uart_communication_blocks;
 
--! @brief Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
--! @details Declare used components for instantiation
architecture Behavioral of uart_communication_blocks is
 
-- Declare components...
component baud_generator is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : out STD_LOGIC);
Port ( rst : in STD_LOGIC; --! Reset Input
clk : in STD_LOGIC; --! Clock input
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Number of cycles to wait for baud generation
baud_oversample : out std_logic; --! Oversample(8x) version of baud (Used on serial_receiver)
baud : out STD_LOGIC); --! Baud generation output (Used on serial_transmitter)
end component;
 
component serial_transmitter is
Port ( rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent : out STD_LOGIC;
serial_out : out STD_LOGIC);
Port ( rst : in STD_LOGIC; --! Reset input
baudClk : in STD_LOGIC; --! Baud rate clock input
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
data_sent : out STD_LOGIC; --! Indicate that byte has been sent
serial_out : out STD_LOGIC); --! Uart serial output
end component;
 
component serial_receiver is
Port (
rst : in STD_LOGIC;
baudOverSampleClk : in STD_LOGIC;
serial_in : in STD_LOGIC;
data_ready : out STD_LOGIC;
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
rst : in STD_LOGIC; --! Reset input
baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
serial_in : in STD_LOGIC; --! Uart serial input
data_ready : out STD_LOGIC; --! Data received and ready to be read
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
end component;
signal baud_tick : std_logic;
signal baud_tick_oversample : std_logic;

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